From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31B21C433DF for ; Fri, 9 Oct 2020 10:01:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CFB2022275 for ; Fri, 9 Oct 2020 10:01:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ffwll.ch header.i=@ffwll.ch header.b="UzMeV+rw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387446AbgJIKBy (ORCPT ); Fri, 9 Oct 2020 06:01:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387438AbgJIKBw (ORCPT ); Fri, 9 Oct 2020 06:01:52 -0400 Received: from mail-oo1-xc44.google.com (mail-oo1-xc44.google.com [IPv6:2607:f8b0:4864:20::c44]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FE4DC0613D5 for ; Fri, 9 Oct 2020 03:01:52 -0700 (PDT) Received: by mail-oo1-xc44.google.com with SMTP id h8so2225337ooc.12 for ; Fri, 09 Oct 2020 03:01:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=ftHJzNt4bERnNP+SIXIGo56JCvpL8TcP22nYSQKOV5k=; b=UzMeV+rwKkunQlHgHNSlVY990btw6GRORlFmsAYBx1gPA8SEXpEqpXIa8uGJFLzTQw b8BMC7q8QXr1fDrrdZMhmylgPVoMLs2HnzRpCUYwl2q2F4u0Dr/m3fS3LlJ3o6+Ejdce Wcj4zRQKhHrsGCyXRc5pfd4UfW1pvcEdIaWfc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=ftHJzNt4bERnNP+SIXIGo56JCvpL8TcP22nYSQKOV5k=; b=su62xTShB3axruisUcssdBwP31mqxkP8XjQiXwwt8l06phlif7arNCy+oJqeggIeOw Y+zYo8SX1siHh40GY6DpppzqWL1xAhga0q1Y+EJ3lmusV7X4tOgWQr6wnz0wmAI9xAte cBKzp1Akm4LC3vrcp4rqNCyhoDQeG07BzqTvREfvjEsNMNL8MLJxKmRX/ybZqngf+sxB x6SJfp/mg9EFyIUQNhOVYpQzX8rVO8OKujh9m9hk6LnAt/XltZ2xMygFLNPdMN90owi0 O/kAGmCj0ZaJzbvc85Qj58DpJzUIZ9paDt/BB9nb8D84UGG8QRneDlp7E5trspHxfBUr aZXg== X-Gm-Message-State: AOAM5336hYl9jHFKQ9AJAZ+j8VF1ENX7XlxmxxokYZXQeHGogYu3Dh3y iWe1BlKMF0ZpcUSAeT2S1gPGb4trEhtg46vdO0u1og== X-Google-Smtp-Source: ABdhPJyck/sz2r8nAE1vOQ+mmU8ZRo9mJI1evvAL5G2Nq41icTgyJhGztZHNyIlc3HZk+r5jBb8vWdtCG7CV4AmWN/U= X-Received: by 2002:a4a:e592:: with SMTP id o18mr8337874oov.28.1602237711175; Fri, 09 Oct 2020 03:01:51 -0700 (PDT) MIME-Version: 1.0 References: <20201009075934.3509076-1-daniel.vetter@ffwll.ch> <20201009075934.3509076-18-daniel.vetter@ffwll.ch> <20201009094750.GQ6112@intel.com> In-Reply-To: <20201009094750.GQ6112@intel.com> From: Daniel Vetter Date: Fri, 9 Oct 2020 12:01:39 +0200 Message-ID: Subject: Re: [PATCH v2 17/17] drm/i915: Properly request PCI BARs To: =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= Cc: DRI Development , LKML , linux-s390 , linux-samsung-soc , Jan Kara , Kees Cook , KVM list , Jason Gunthorpe , Linux PCI , Linux MM , =?UTF-8?B?SsOpcsO0bWUgR2xpc3Nl?= , John Hubbard , Bjorn Helgaas , Daniel Vetter , Dan Williams , Andrew Morton , Linux ARM , "open list:DMA BUFFER SHARING FRAMEWORK" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org On Fri, Oct 9, 2020 at 11:47 AM Ville Syrj=C3=A4l=C3=A4 wrote: > > On Fri, Oct 09, 2020 at 09:59:34AM +0200, Daniel Vetter wrote: > > When trying to test my CONFIG_IO_STRICT_DEVMEM changes I realized they > > do nothing for i915. Because i915 doesn't request any regions, like > > pretty much all drm pci drivers. I guess this is some very old > > remnants from the userspace modesetting days, when we wanted to > > co-exist with the fbdev driver. Which usually requested these > > resources. > > > > But makes me wonder why the pci subsystem doesn't just request > > resource automatically when we map a bar and a pci driver is bound? > > > > Knowledge about which pci bars we need kludged together from > > intel_uncore.c and intel_gtt.c from i915 and intel-gtt.c over in the > > fake agp driver. > > > > Signed-off-by: Daniel Vetter > > Cc: Jason Gunthorpe > > Cc: Kees Cook > > Cc: Dan Williams > > Cc: Andrew Morton > > Cc: John Hubbard > > Cc: J=C3=A9r=C3=B4me Glisse > > Cc: Jan Kara > > Cc: Dan Williams > > Cc: linux-mm@kvack.org > > Cc: linux-arm-kernel@lists.infradead.org > > Cc: linux-samsung-soc@vger.kernel.org > > Cc: linux-media@vger.kernel.org > > Cc: Bjorn Helgaas > > Cc: linux-pci@vger.kernel.org > > --- > > drivers/gpu/drm/i915/intel_uncore.c | 25 +++++++++++++++++++++++-- > > 1 file changed, 23 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915= /intel_uncore.c > > index 54e201fdeba4..ce39049d8919 100644 > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > @@ -1692,10 +1692,13 @@ static int uncore_mmio_setup(struct intel_uncor= e *uncore) > > struct pci_dev *pdev =3D i915->drm.pdev; > > int mmio_bar; > > int mmio_size; > > + int bar_selection; > > Signed bitmasks always make me uneasy. But looks like > that's what it is in the pci api. So meh. Yeah it's surprising. > > + int ret; > > > > mmio_bar =3D IS_GEN(i915, 2) ? 1 : 0; > > + bar_selection =3D BIT (2) | BIT(mmio_bar); > ^ > spurious space > > That's also not correct for gen2 I think. > > gen2: > 0 =3D GMADR > 1 =3D MMADR > 2 =3D IOBAR > > gen3: > 0 =3D MMADR > 1 =3D IOBAR > 2 =3D GMADR > 3 =3D GTTADR > > gen4+: > 0+1 =3D GTTMMADR > 2+3 =3D GMADR > 4 =3D IOBAR > > Maybe we should just have an explicit list of bars like that in a > comment? > > I'd also suggest sucking this bitmask calculation into a small helper > so you can reuse it for the release. tbh I just hacked this up for testing. Given how almost no other drm driver does this, I'm wondering whether we should or not. Also the only reason why I didn't just use the pci_request_regions helper is to avoid the vga ioport range, since that's managed by vgaarbiter. So I think if we go for this for real we should: - register the vga ioport range in the vgaarbiter - have a pci_request_iomem_regions helper that grabs all mem bars - roll that out to all drm pci drivers Or something like that. The other complication is when we resize the iobar. So not really sure what to do here. -Daniel > > > /* > > - * Before gen4, the registers and the GTT are behind different BA= Rs. > > + * On gen3 the registers and the GTT are behind different BARs. > > * However, from gen4 onwards, the registers and the GTT are shar= ed > > * in the same BAR, so we want to restrict this ioremap from > > * clobbering the GTT which we want ioremap_wc instead. Fortunate= ly, > > @@ -1703,6 +1706,8 @@ static int uncore_mmio_setup(struct intel_uncore = *uncore) > > * generations up to Ironlake. > > * For dgfx chips register range is expanded to 4MB. > > */ > > + if (INTEL_GEN(i915) =3D=3D 3) > > + bar_selection |=3D BIT(3); > > if (INTEL_GEN(i915) < 5) > > mmio_size =3D 512 * 1024; > > else if (IS_DGFX(i915)) > > @@ -1710,8 +1715,15 @@ static int uncore_mmio_setup(struct intel_uncore= *uncore) > > else > > mmio_size =3D 2 * 1024 * 1024; > > > > + ret =3D pci_request_selected_regions(pdev, bar_selection, "i915")= ; > > + if (ret < 0) { > > + drm_err(&i915->drm, "failed to request pci bars\n"); > > + return ret; > > + } > > + > > uncore->regs =3D pci_iomap(pdev, mmio_bar, mmio_size); > > if (uncore->regs =3D=3D NULL) { > > + pci_release_selected_regions(pdev, bar_selection); > > drm_err(&i915->drm, "failed to map registers\n"); > > return -EIO; > > } > > @@ -1721,9 +1733,18 @@ static int uncore_mmio_setup(struct intel_uncore= *uncore) > > > > static void uncore_mmio_cleanup(struct intel_uncore *uncore) > > { > > - struct pci_dev *pdev =3D uncore->i915->drm.pdev; > > + struct drm_i915_private *i915 =3D uncore->i915; > > + struct pci_dev *pdev =3D i915->drm.pdev; > > + int mmio_bar; > > + int bar_selection; > > + > > + mmio_bar =3D IS_GEN(i915, 2) ? 1 : 0; > > + bar_selection =3D BIT (2) | BIT(mmio_bar); > > + if (INTEL_GEN(i915) =3D=3D 3) > > + bar_selection |=3D BIT(3); > > > > pci_iounmap(pdev, uncore->regs); > > + pci_release_selected_regions(pdev, bar_selection); > > } > > > > void intel_uncore_init_early(struct intel_uncore *uncore, > > -- > > 2.28.0 > > > > _______________________________________________ > > dri-devel mailing list > > dri-devel@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > -- > Ville Syrj=C3=A4l=C3=A4 > Intel --=20 Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch