From: Jagan Teki <jagan@amarulasolutions.com>
To: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Yong Deng <yong.deng@magewell.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Chen-Yu Tsai <wens@csie.org>,
Hans Verkuil <hans.verkuil@cisco.com>,
Sakari Ailus <sakari.ailus@linux.intel.com>,
linux-media <linux-media@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Mylene Josserand <mylene.josserand@bootlin.com>
Subject: Re: [PATCH v2 3/4] ARM: dts: sun8i: Add the H3/H5 CSI controller
Date: Thu, 22 Nov 2018 17:15:27 +0530 [thread overview]
Message-ID: <CAMty3ZDFsaFR1zb3Wt0wJ0XkeNuSHGxDsmZZKgWy=wxJpNTnHQ@mail.gmail.com> (raw)
In-Reply-To: <20181114145934.26855-4-maxime.ripard@bootlin.com>
On Wed, Nov 14, 2018 at 8:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> From: Mylène Josserand <mylene.josserand@bootlin.com>
>
> The H3 and H5 features the same CSI controller that was initially found on
> the A31.
>
> Add a DT node for it.
>
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> index 4b1530ebe427..8779ee750bd8 100644
> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> @@ -393,6 +393,13 @@
> interrupt-controller;
> #interrupt-cells = <3>;
>
> + csi_pins: csi {
> + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> + "PE5", "PE6", "PE7", "PE8", "PE9",
> + "PE10", "PE11";
> + function = "csi";
> + };
> +
> emac_rgmii_pins: emac0 {
> pins = "PD0", "PD1", "PD2", "PD3", "PD4",
> "PD5", "PD7", "PD8", "PD9", "PD10",
> @@ -744,6 +751,21 @@
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> };
>
> + csi: camera@1cb0000 {
> + compatible = "allwinner,sun8i-h3-csi",
> + "allwinner,sun6i-a31-csi";
> + reg = <0x01cb0000 0x1000>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI_SCLK>,
> + <&ccu CLK_DRAM_CSI>;
> + clock-names = "bus", "mod", "ram";
Don't we need CLK_CSI_MCLK which can be pinout via PE1?
next prev parent reply other threads:[~2018-11-22 22:24 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-14 14:59 [PATCH v2 0/4] media: sun6i: Add support for the H3 CSI controller Maxime Ripard
2018-11-14 14:59 ` [PATCH v2 1/4] dt-bindings: media: sun6i: Add A31 and H3 compatibles Maxime Ripard
2018-11-14 15:27 ` Chen-Yu Tsai
2018-11-14 14:59 ` [PATCH v2 2/4] media: sun6i: Add A31 compatible Maxime Ripard
2018-11-14 15:27 ` Chen-Yu Tsai
2018-11-14 14:59 ` [PATCH v2 3/4] ARM: dts: sun8i: Add the H3/H5 CSI controller Maxime Ripard
2018-11-14 15:26 ` Chen-Yu Tsai
2018-11-22 11:45 ` Jagan Teki [this message]
2018-11-22 12:33 ` Chen-Yu Tsai
2018-11-14 14:59 ` [PATCH v2 4/4] [DO NOT MERGE] ARM: dts: sun8i: Add CAM500B camera module to the Nano Pi M1+ Maxime Ripard
2018-11-23 6:21 ` Jagan Teki
2018-11-27 7:08 ` Maxime Ripard
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