Re: (EXT) Re: (EXT) Re: Sony IMX290 link frequency

[Dave Stevenson <dave.stevenson@raspberrypi.com>]

On Thu, 23 Sept 2021 at 14:44, Stein, Alexander
<Alexander.Stein@tq-group.com> wrote:
>
> Hello Dave,
>
> On Tue, 21 Sept 2021 at 11:41 +0100, Dave Stevenson:
> > Whilst the spec is restricted, there are a few introductions that
> > give
> > a basic understanding, eg [1]
>
> Thanks, this helped a bit.
>
> > Clock lanes and data lanes may do slightly different things. It is
> > not
> > uncommon for the clock lane to remain in HS mode at all times, but
> > the
> > data lanes will almost always drop to LP-11. Device tree has a
> > clock-noncontinuous property to denote that the clock lane drops to
> > LP, which maps to the V4L2 flag V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK.
> > There is no mention in the datasheet as to whether IMX290/327
> > produces
> > a continuous clock signal or not, and I can't say that I've checked.
> > Some receivers can get confused if the clock is continuous and they
> > miss the initial state change from LP to HS.
>
> Who drives the clock lane? The sensor or the host processor? If it is
> the sensor how do you support several sensors on the same bus?

The sensor.
With MIPI D-PHY a source (CSI2 or DSI) will always have one clock lane
and one or more data lanes.
Some SoC's allow you to reconfigure how lanes are used, but I've never
known a way to combine multiple sensors into a single CSI-2 receiver.

> > > > > > > I assume now that my current problem regarding settle time is
> > > somewhere
> else. I can currently only assume the escape clock is not correct,
> > > but
> there is pretty much no documentation at all on that topic.
> >
> > What platform are you working with?
>
> I'm working on an i.MX8QM based board. A public RM is available since
> several days [1]. The MIPI-CSI subsystem chapters are a bit lacking.
> Also I am aware that the ISI does some strange things with CSI input,
> see also [1], but that is a different issue.
>
> As far as I understand different documents, the escape clock is used
> during LP-11 and shall be from 10 to 20 MHz.
> The device tree configures some clock to 72MHz [2], but I do not know
> what's happening internally.
>
> I used the same approach for calculating the settle time as [3]. But I
> have to use a value slightly below the maximum rather than the average

I don't know the details of iMX8.
For BCM283x we supply an LP clock of 100MHz, and indeed that clocks
the block state machine for handling LP state transitions. LP mode is
relatively low speed in comparison to that - typically 10-20MHz if
memory serves correctly.

I vaguely remember one of the SoCs being very fussy about when the
sensor is left at LP-11. Looking at history, that appears to be
Renesas, but may apply to iMX8.
The IMX290 datasheet implies that the sensor will exit ULPS (LP-00)
state 20usecs after XCLR goes high, and remain in LP-11 standby mode
is cancelled (the clock lane then enters HS mode).

  Dave

> > There are registers in the IMX290/327 which configure the MIPI
> > timings
> > - 0x3445-0x3455. The values do differ based on the link frequency,
> > but
> > checking our driver to the datasheet they appear to be all correct.
>
> Agreed.
>
> [1] https://www.nxp.com/docs/en/reference-manual/IMX8QMRM.pdf
> [2]
> https://yhbt.net/lore/all/20200226151431.GY5379@paasikivi.fi.intel.com/T/
>
> [3]
> https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi?h=lf-5.10.y#n516
>
> [4]
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/staging/media/imx/imx8mq-mipi-csi2.c#n343
>
> --
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>
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