From: Vishal Sagar <vsagar@xilinx.com>
To: Luca Ceresoli <luca@lucaceresoli.net>,
Vishal Sagar <vishal.sagar@xilinx.com>,
Hyun Kwon <hyunk@xilinx.com>,
"laurent.pinchart@ideasonboard.com"
<laurent.pinchart@ideasonboard.com>,
"mchehab@kernel.org" <mchehab@kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
Michal Simek <michals@xilinx.com>,
"linux-media@vger.kernel.org" <linux-media@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"sakari.ailus@linux.intel.com" <sakari.ailus@linux.intel.com>,
"hans.verkuil@cisco.com" <hans.verkuil@cisco.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Dinesh Kumar <dineshk@xilinx.com>,
Sandip Kothari <sandipk@xilinx.com>
Subject: RE: [PATCH v3 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
Date: Fri, 22 Feb 2019 12:05:55 +0000 [thread overview]
Message-ID: <CY4PR02MB2709DC93D6F6F1BA181B9607A77F0@CY4PR02MB2709.namprd02.prod.outlook.com> (raw)
In-Reply-To: <7fc3bd7b-4537-3df5-12ee-55ebec17a8bd@lucaceresoli.net>
Hi Luca,
Apologies for the delayed response.
> -----Original Message-----
> From: Luca Ceresoli [mailto:luca@lucaceresoli.net]
> Sent: Monday, February 11, 2019 8:01 PM
> To: Vishal Sagar <vsagar@xilinx.com>; Vishal Sagar <vishal.sagar@xilinx.com>;
> Hyun Kwon <hyunk@xilinx.com>; laurent.pinchart@ideasonboard.com;
> mchehab@kernel.org; robh+dt@kernel.org; mark.rutland@arm.com; Michal
> Simek <michals@xilinx.com>; linux-media@vger.kernel.org;
> devicetree@vger.kernel.org; sakari.ailus@linux.intel.com;
> hans.verkuil@cisco.com; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; Dinesh Kumar <dineshk@xilinx.com>; Sandip Kothari
> <sandipk@xilinx.com>
> Subject: Re: [PATCH v3 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem
>
> Hi,
>
> thanks for the quick reply.
>
> On 11/02/19 13:43, Vishal Sagar wrote:
> >>> +static int xcsi2rxss_start_stream(struct xcsi2rxss_state *state)
> >>> +{
> >>> + struct xcsi2rxss_core *core = &state->core;
> >>> + int ret = 0;
> >>> +
> >>> + xcsi2rxss_enable(core);
> >>> +
> >>> + ret = xcsi2rxss_reset(core);
> >>> + if (ret < 0) {
> >>> + state->streaming = false;
> >>> + return ret;
> >>> + }
> >>> +
> >>> + xcsi2rxss_intr_enable(core);
> >>> + state->streaming = true;
> >>
> >> Shouldn't you propagate s_stream to the upstream subdev here calling
> >> v4l2_subdev_call(..., ..., s_stream, 1)?
> >>
> >
> > This is done by the xvip_pipeline_start_stop() in xilinx-dma.c for Xilinx Video
> pipeline.
>
> Indeed it does, however other CSI2 RX drivers do propagate s_stream in
> their own s_stream. Not strictly related to this driver, but what's the
> logic for having these two different behaviors?
>
I am not really sure about this. I agree with what you say but
in case the s_stream() is implemented here, then the sensor's s_stream() will be called twice.
I don't think this would be the correct behavior.
> Also xvip_pipeline_start_stop() only follows the graph through
> entity->pads[0], so it looks like it cannot handle entities with
> multiple sink pads. How would it be able to handle e.g. the AXI4-Stream
> Switch [0], which has 2+ sink pads?
>
I agree with you about this. There should be a different mechanism for this.
Regards
Vishal Sagar
> [0]
> https://www.xilinx.com/support/documentation/ip_documentation/axis_infra
> structure_ip_suite/v1_1/pg085-axi4stream-infrastructure.pdf
> (page 16).
>
> --
> Luca
next prev parent reply other threads:[~2019-02-22 12:06 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-01 12:56 [PATCH v3 0/2] Add support for Xilinx CSI2 Receiver Subsystem Vishal Sagar
2019-02-01 12:56 ` [PATCH v3 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem Vishal Sagar
2019-02-11 10:42 ` Luca Ceresoli
2019-03-08 19:04 ` Vishal Sagar
2019-03-11 12:08 ` Luca Ceresoli
2019-03-12 4:36 ` Vishal Sagar
2019-02-01 12:56 ` [PATCH v3 2/2] media: v4l: " Vishal Sagar
2019-02-11 10:42 ` Luca Ceresoli
2019-02-11 12:43 ` Vishal Sagar
2019-02-11 14:30 ` Luca Ceresoli
2019-02-22 12:05 ` Vishal Sagar [this message]
2019-02-13 19:45 ` [v3,2/2] " Hyun Kwon
2019-02-22 12:06 ` Vishal Sagar
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