From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74C00C32774 for ; Tue, 23 Aug 2022 02:20:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239387AbiHWCUJ (ORCPT ); Mon, 22 Aug 2022 22:20:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239414AbiHWCUH (ORCPT ); Mon, 22 Aug 2022 22:20:07 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FA2F5AC78; Mon, 22 Aug 2022 19:20:03 -0700 (PDT) X-UUID: 0c4fad0124e24e3fb830deb36982348e-20220823 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; 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Tue, 23 Aug 2022 10:19:58 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 23 Aug 2022 10:19:58 +0800 Message-ID: Subject: Re: [PATCH v25 2/4] dt-binding: mediatek: add bindings for MediaTek CCORR and WDMA From: moudy ho To: Matthias Brugger , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Hans Verkuil CC: Chun-Kuang Hu , Rob Landley , Laurent Pinchart , , , , , , Alexandre Courbot , , , , , Benjamin Gaignard , AngeloGioacchino Del Regno , , Date: Tue, 23 Aug 2022 10:19:58 +0800 In-Reply-To: <19c4e6ec-8252-1b25-6999-a0b24bbf7dbb@gmail.com> References: <20220817095629.29911-1-moudy.ho@mediatek.com> <20220817095629.29911-3-moudy.ho@mediatek.com> <19c4e6ec-8252-1b25-6999-a0b24bbf7dbb@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Hi Matthias, On Mon, 2022-08-22 at 16:32 +0200, Matthias Brugger wrote: > > On 17/08/2022 11:56, Moudy Ho wrote: > > This patch adds DT binding documentation for MediaTek's CCORR and > > WDMA components. > > These components exist in both MediaTek's Media Data Path 3(MDP3) > > and DRM, > > and the bindings are placed under the folder "./soc/mediatek" to > > prevent > > duplicate builds. > > > > Signed-off-by: Moudy Ho > > Reviewed-by: Rob Herring > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > .../bindings/soc/mediatek/mediatek,ccorr.yaml | 68 > > ++++++++++++++++ > > .../bindings/soc/mediatek/mediatek,wdma.yaml | 81 > > +++++++++++++++++++ > > 2 files changed, 149 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam > > l > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam > > l > > new file mode 100644 > > index 000000000000..10786d769750 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam > > l > > @@ -0,0 +1,68 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml*__;Iw!!CTRNKA9wMg0ARbw!3h7qYnjiwvN90iwxMZCIpxo-QWZqllWu4mMpB6NSjDHPKnuM4mITblmweAeVniXJ$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3h7qYnjiwvN90iwxMZCIpxo-QWZqllWu4mMpB6NSjDHPKnuM4mITblmweCOWt0j9$ > > > > + > > +title: MediaTek color correction > > + > > +maintainers: > > + - Matthias Brugger > > + - Ping-Hsun Wu > > Same here. > > Regards, > Matthias > Thanks for the reminder, I'll deal with it together with the previous patch Regards, Moudy > > + > > +description: | > > + MediaTek color correction with 3X3 matrix. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8183-mdp3-ccorr > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/-gce.h. > > + > > + mediatek,gce-events: > > + description: > > + The event id which is mapping to the specific hardware event > > signal > > + to gce. The event id is defined in the gce header > > + include/dt-bindings/gce/-gce.h of each chips. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + > > + clocks: > > + minItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - mediatek,gce-events > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + #include > > + > > + mdp3_ccorr: mdp3-ccorr@1401c000 { > > + compatible = "mediatek,mt8183-mdp3-ccorr"; > > + reg = <0x1401c000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 > > 0x1000>; > > + mediatek,gce-events = , > > + ; > > + clocks = <&mmsys CLK_MM_MDP_CCORR>; > > + }; > > diff --git > > a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > new file mode 100644 > > index 000000000000..95ec19543945 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > @@ -0,0 +1,81 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!3h7qYnjiwvN90iwxMZCIpxo-QWZqllWu4mMpB6NSjDHPKnuM4mITblmweNEpTeKs$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3h7qYnjiwvN90iwxMZCIpxo-QWZqllWu4mMpB6NSjDHPKnuM4mITblmweCOWt0j9$ > > > > + > > +title: MediaTek Write Direct Memory Access > > + > > +maintainers: > > + - Matthias Brugger > > + - Ping-Hsun Wu > > + > > +description: | > > + MediaTek Write Direct Memory Access(WDMA) component used to > > write > > + the data into DMA. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8183-mdp3-wdma > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/-gce.h. > > + > > + mediatek,gce-events: > > + description: > > + The event id which is mapping to the specific hardware event > > signal > > + to gce. The event id is defined in the gce header > > + include/dt-bindings/gce/-gce.h of each chips. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + minItems: 1 > > + > > + iommus: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - mediatek,gce-events > > + - power-domains > > + - clocks > > + - iommus > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + #include > > + #include > > + #include > > + > > + mdp3_wdma: mdp3-wdma@14006000 { > > + compatible = "mediatek,mt8183-mdp3-wdma"; > > + reg = <0x14006000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 > > 0x1000>; > > + mediatek,gce-events = , > > + ; > > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_MDP_WDMA0>; > > + iommus = <&iommu>; > > + };