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Subject: Re: [RFC PATCH v5 12/14] gpu: host1x: mipi: Keep MIPI clock enabled
 till calibration is done
To:     Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
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From:   Sowjanya Komatineni <skomatineni@nvidia.com>
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Date:   Wed, 29 Jul 2020 10:55:16 -0700
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On 7/29/20 10:08 AM, Dmitry Osipenko wrote:
> 28.07.2020 19:04, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
> ...
>>>> +void tegra_mipi_cancel_calibration(struct tegra_mipi_device *device)
>>>> +{
>>> Doesn't MIPI_CAL need to be reset here?
>> No need to reset MIPI CAL
> Could you please explain why. There is a calibration state-machine that
> apparently needs to be returned into initial state, does it return by
> itself?
>
> TRM says that MIPI block needs to be reset before of starting
> calibration process. The reset is completely missing in the driver, I
> assume it needs to be corrected with another patch.

TRM documented incorrectly. There is no need to reset MIPI_CAL.

MIPI CAL is FSM and it does not hang and done bit is to indicate if=20
results are applied to pads or not.

If we don't see done bit set meaning, MIPI CAL did not see LP-11 and=20
results are not applied to pads.

Also while multiple streams can happen in parallel and we can't reset=20
MIPI CAL as other CSI channel streams (using other pads) may also be=20
going thru calibration process in parallel depending and also DSI pads=20
also are calibrated thru same MIPI CAL controller.