From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 016DEC11F66 for ; Wed, 14 Jul 2021 18:08:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DA725613C3 for ; Wed, 14 Jul 2021 18:08:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230091AbhGNSLM (ORCPT ); Wed, 14 Jul 2021 14:11:12 -0400 Received: from comms.puri.sm ([159.203.221.185]:55388 "EHLO comms.puri.sm" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229651AbhGNSLM (ORCPT ); Wed, 14 Jul 2021 14:11:12 -0400 Received: from localhost (localhost [127.0.0.1]) by comms.puri.sm (Postfix) with ESMTP id 9AC38DFCFB; Wed, 14 Jul 2021 11:07:50 -0700 (PDT) Received: from comms.puri.sm ([127.0.0.1]) by localhost (comms.puri.sm [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4QRBzjwfMO9H; Wed, 14 Jul 2021 11:07:49 -0700 (PDT) Message-ID: Subject: Re: [PATCH v6 1/3] dt-bindings: media: document the nxp,imx8mq-mipi-csi2 receiver phy and controller From: Martin Kepplinger To: Laurent Pinchart Cc: festevam@gmail.com, krzk@kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de, kernel@puri.sm, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, m.felsch@pengutronix.de, mchehab@kernel.org, phone-devel@vger.kernel.org, robh@kernel.org, shawnguo@kernel.org, slongerbeam@gmail.com Date: Wed, 14 Jul 2021 20:07:44 +0200 In-Reply-To: References: <20210714111931.324485-1-martin.kepplinger@puri.sm> <20210714111931.324485-2-martin.kepplinger@puri.sm> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.38.3-1 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Am Mittwoch, dem 14.07.2021 um 20:53 +0300 schrieb Laurent Pinchart: > Hi Martin, > > Thank you for the patch. > > On Wed, Jul 14, 2021 at 01:19:29PM +0200, Martin Kepplinger wrote: > > The i.MX8MQ SoC integrates a different MIPI CSI receiver as the > > i.MX8MM so > > describe the DT bindings for it. > > > > Signed-off-by: Martin Kepplinger > > Reviewed-by: Rob Herring > > --- > >  .../bindings/media/nxp,imx8mq-mipi-csi2.yaml  | 173 > > ++++++++++++++++++ > >  1 file changed, 173 insertions(+) > >  create mode 100644 > > Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq- > > mipi-csi2.yaml > > b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > > new file mode 100644 > > index 000000000000..97222485f223 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi- > > csi2.yaml > > @@ -0,0 +1,173 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: NXP i.MX8MQ MIPI CSI-2 receiver > > + > > +maintainers: > > +  - Martin Kepplinger > > + > > +description: |- > > +  This binding covers the CSI-2 RX PHY and host controller > > included in the > > +  NXP i.MX8MQ SoC. It handles the sensor/image input and process > > for all the > > +  input imaging devices. > > + > > +properties: > > +  compatible: > > +    enum: > > +      - fsl,imx8mq-mipi-csi2 > > + > > +  reg: > > +    maxItems: 1 > > + > > +  clocks: > > +    items: > > +      - description: core is the RX Controller Core Clock input. > > This clock > > +                     must be exactly equal to or faster than the > > receive > > +                     byteclock from the RX DPHY. > > +      - description: esc is the Rx Escape Clock. This must be the > > same escape > > +                     clock that the RX DPHY receives. > > +      - description: ui is the pixel clock (phy_ref up to 333Mhz). > > Where did you get the 333MHz limit from ? The information I've > received > indicate a limit of 125MHz for the UI clock (and 266 and 133 MHz for > the > core and esc clocks respectively). The latest ref.manual revison has this corrected to 333Mhz. Look at the "changelog" they have in the RM, to find it quickly. > > With this addressed, > > Reviewed-by: Laurent Pinchart > > > +                     See the reference manual for details. > > + > > +  clock-names: > > +    items: > > +      - const: core > > +      - const: esc > > +      - const: ui > > + > > +  power-domains: > > +    maxItems: 1 > > + > > +  resets: > > +    items: > > +      - description: CORE_RESET reset register bit definition > > +      - description: PHY_REF_RESET reset register bit definition > > +      - description: ESC_RESET reset register bit definition > > + > > +  fsl,mipi-phy-gpr: > > +    description: | > > +      The phandle to the imx8mq syscon iomux-gpr with the register > > +      for setting RX_ENABLE for the mipi receiver. > > + > > +      The format should be as follows: > > +      > > +      gpr is the phandle to general purpose register node. > > +      req_gpr is the gpr register offset of RX_ENABLE for the mipi > > phy. > > +    $ref: /schemas/types.yaml#/definitions/phandle-array > > +    items: > > +      items: > > +        - description: The 'gpr' is the phandle to general purpose > > register node. > > +        - description: The 'req_gpr' is the gpr register offset > > containing > > +                       CSI2_1_RX_ENABLE or CSI2_2_RX_ENABLE > > respectively. > > +          maximum: 0xff > > + > > +  interconnects: > > +    maxItems: 1 > > + > > +  interconnect-names: > > +    const: dram > > + > > +  ports: > > +    $ref: /schemas/graph.yaml#/properties/ports > > + > > +    properties: > > +      port@0: > > +        $ref: /schemas/graph.yaml#/$defs/port-base > > +        unevaluatedProperties: false > > +        description: > > +          Input port node, single endpoint describing the CSI-2 > > transmitter. > > + > > +        properties: > > +          endpoint: > > +            $ref: video-interfaces.yaml# > > +            unevaluatedProperties: false > > + > > +            properties: > > +              data-lanes: > > +                items: > > +                  minItems: 1 > > +                  maxItems: 4 > > +                  items: > > +                    - const: 1 > > +                    - const: 2 > > +                    - const: 3 > > +                    - const: 4 > > + > > +            required: > > +              - data-lanes > > + > > +      port@1: > > +        $ref: /schemas/graph.yaml#/properties/port > > +        description: > > +          Output port node > > + > > +    required: > > +      - port@0 > > +      - port@1 > > + > > +required: > > +  - compatible > > +  - reg > > +  - clocks > > +  - clock-names > > +  - power-domains > > +  - resets > > +  - fsl,mipi-phy-gpr > > +  - ports > > + > > +additionalProperties: false > > + > > +examples: > > +  - | > > +    #include > > +    #include > > + > > +    csi@30a70000 { > > +        compatible = "fsl,imx8mq-mipi-csi2"; > > +        reg = <0x30a70000 0x1000>; > > +        clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, > > +                 <&clk IMX8MQ_CLK_CSI1_ESC>, > > +                 <&clk IMX8MQ_CLK_CSI1_PHY_REF>; > > +        clock-names = "core", "esc", "ui"; > > +        assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, > > +                          <&clk IMX8MQ_CLK_CSI1_PHY_REF>, > > +                          <&clk IMX8MQ_CLK_CSI1_ESC>; > > +        assigned-clock-rates = <266000000>, <200000000>, > > <66000000>; > > +        assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, > > +                                 <&clk IMX8MQ_SYS2_PLL_1000M>, > > +                                 <&clk IMX8MQ_SYS1_PLL_800M>; > > +        power-domains = <&pgc_mipi_csi1>; > > +        resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>, > > +                 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>, > > +                 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>; > > +        fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>; > > +        interconnects = <&noc IMX8MQ_ICM_CSI1 &noc > > IMX8MQ_ICS_DRAM>; > > +        interconnect-names = "dram"; > > + > > +        ports { > > +            #address-cells = <1>; > > +            #size-cells = <0>; > > + > > +            port@0 { > > +                reg = <0>; > > + > > +                imx8mm_mipi_csi_in: endpoint { > > +                    remote-endpoint = <&imx477_out>; > > +                    data-lanes = <1 2 3 4>; > > +                }; > > +            }; > > + > > +            port@1 { > > +                reg = <1>; > > + > > +                imx8mm_mipi_csi_out: endpoint { > > +                    remote-endpoint = <&csi_in>; > > +                }; > > +            }; > > +        }; > > +    }; > > + > > +... >