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From: Matthias Brugger <matthias.bgg@gmail.com>
To: Chao Hao <chao.hao@mediatek.com>, Joerg Roedel <joro@8bytes.org>,
	Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
	wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
	Evan Green <evgreen@chromium.org>,
	iommu@lists.linux-foundation.org,
	linux-mediatek@lists.infradead.org,
	Yong Wu <yong.wu@mediatek.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register
Date: Mon, 29 Jun 2020 11:28:11 +0200
Message-ID: <0e9ceba8-0cc4-44a1-148c-1c9a6b3844ce@gmail.com> (raw)
In-Reply-To: <20200629071310.1557-5-chao.hao@mediatek.com>



On 29/06/2020 09:13, Chao Hao wrote:
> Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition
> in MISC_CTRL register.
> F_MMU_STANDARD_AXI_MODE_BIT:
>   If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow
> standard AXI protocol), iommu will send urgent read command firstly
> compare with normal read command to improve performance.

Can you please help me to understand the phrase. Sorry I'm not a AXI specialist.
Does this mean that you will send a 'urgent read command' which is not described
in the specifications instead of a normal read command?

> F_MMU_IN_ORDER_WR_EN:
>   If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu
> will re-order write command and send more higher priority write command
> instead of sending write command in order. The feature be controlled
> by OUT_ORDER_EN macro definition.
> 
> Cc: Matthias Brugger <matthias.bgg@gmail.com>
> Suggested-by: Yong Wu <yong.wu@mediatek.com>
> Signed-off-by: Chao Hao <chao.hao@mediatek.com>
> ---
>  drivers/iommu/mtk_iommu.c | 12 +++++++++++-
>  drivers/iommu/mtk_iommu.h |  1 +
>  2 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 8f81df6cbe51..67b46b5d83d9 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -42,6 +42,9 @@
>  #define F_INVLD_EN1				BIT(1)
>  
>  #define REG_MMU_MISC_CTRL			0x048
> +#define F_MMU_IN_ORDER_WR_EN			(BIT(1) | BIT(17))
> +#define F_MMU_STANDARD_AXI_MODE_BIT		(BIT(3) | BIT(19))

Wouldn't it make more sense to name it F_MMU_STANDARD_AXI_MODE_EN?

> +
>  #define REG_MMU_DCM_DIS				0x050
>  
>  #define REG_MMU_CTRL_REG			0x110
> @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
>  	}
>  	writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
>  
> +	regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);

We only need to read regval in the else branch.

>  	if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
>  		/* The register is called STANDARD_AXI_MODE in this case */
> -		writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
> +		regval = 0;
> +	} else {
> +		/* For mm_iommu, it can improve performance by the setting */
> +		regval &= ~F_MMU_STANDARD_AXI_MODE_BIT;
> +		if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN))
> +			regval &= ~F_MMU_IN_ORDER_WR_EN;
>  	}
> +	writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
>  
>  	if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
>  			     dev_name(data->dev), (void *)data)) {
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 7cc39f729263..4b780b651ef4 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -22,6 +22,7 @@
>  #define HAS_BCLK			BIT(1)
>  #define HAS_VLD_PA_RNG			BIT(2)
>  #define RESET_AXI			BIT(3)
> +#define OUT_ORDER_EN			BIT(4)

Maybe something like OUT_ORDER_WR_EN, to make clear that it's about the the
write path.

>  
>  #define MTK_IOMMU_HAS_FLAG(pdata, _x) \
>  		((((pdata)->flags) & (_x)) == (_x))
> 

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Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-29  7:13 [PATCH v5 00/10] MT6779 IOMMU SUPPORT Chao Hao
2020-06-29  7:13 ` [PATCH v5 01/10] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-06-29  7:13 ` [PATCH v5 02/10] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL Chao Hao
2020-07-01  2:17   ` Yong Wu
2020-07-03  2:36     ` chao hao
2020-06-29  7:13 ` [PATCH v5 03/10] iommu/mediatek: Modify the usage of mtk_iommu_plat_data structure Chao Hao
2020-06-29  9:11   ` Matthias Brugger
2020-06-30 10:56   ` Yong Wu
2020-06-30 11:55     ` chao hao
2020-06-29  7:13 ` [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register Chao Hao
2020-06-29  9:28   ` Matthias Brugger [this message]
2020-06-30 10:53     ` chao hao
2020-07-01 14:58       ` Matthias Brugger
2020-07-03  2:38         ` chao hao
2020-06-29  7:13 ` [PATCH v5 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data Chao Hao
2020-06-29  7:13 ` [PATCH v5 06/10] iommu/mediatek: Add sub_comm id in translation fault Chao Hao
2020-06-30 10:55   ` Yong Wu
2020-06-30 11:07     ` chao hao
2020-06-29  7:13 ` [PATCH v5 07/10] iommu/mediatek: Add REG_MMU_WR_LEN register definition Chao Hao
2020-06-29 10:16   ` Matthias Brugger
2020-06-30 10:59     ` chao hao
2020-07-01 15:00       ` Matthias Brugger
2020-06-29  7:13 ` [PATCH v5 08/10] iommu/mediatek: Extend protect pa alignment value Chao Hao
2020-06-29 10:17   ` Matthias Brugger
2020-06-29  7:13 ` [PATCH v5 09/10] iommu/mediatek: Modify MMU_CTRL register setting Chao Hao
2020-06-29 10:28   ` Matthias Brugger
2020-06-30 11:02     ` chao hao
2020-06-29  7:13 ` [PATCH v5 10/10] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-06-29 10:29   ` Matthias Brugger

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