From: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
To: MyungJoo Ham <myungjoo.ham@samsung.com>,
Kyungmin Park <kyungmin.park@samsung.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
"Rob Herring" <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Nishanth Menon <nm@ti.com>, "Stephen Boyd" <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org,
"Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>,
srv_heupstream@mediatek.com, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org, fan.chen@mediatek.com,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [v5, PATCH 1/5] cpufreq: mediatek: add clock enable for intermediate clock
Date: Tue, 26 Nov 2019 19:50:42 +0800 [thread overview]
Message-ID: <1574769046-28449-2-git-send-email-andrew-sh.cheng@mediatek.com> (raw)
In-Reply-To: <1574769046-28449-1-git-send-email-andrew-sh.cheng@mediatek.com>
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
Intermediate clock is not always enabled by ccf in different projects,
so cpufreq should always enable it by itself.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 0c98dd08273d..4b0cc50dd93b 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -368,13 +368,17 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
goto out_free_resources;
}
+ ret = clk_prepare_enable(inter_clk);
+ if (ret)
+ goto out_free_opp_table;
+
/* Search a safe voltage for intermediate frequency. */
rate = clk_get_rate(inter_clk);
opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
if (IS_ERR(opp)) {
pr_err("failed to get intermediate opp for cpu%d\n", cpu);
ret = PTR_ERR(opp);
- goto out_free_opp_table;
+ goto out_disable_clock;
}
info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
@@ -393,6 +397,9 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
return 0;
+out_disable_clock:
+ clk_disable_unprepare(inter_clk);
+
out_free_opp_table:
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
@@ -417,8 +424,10 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
regulator_put(info->sram_reg);
if (!IS_ERR(info->cpu_clk))
clk_put(info->cpu_clk);
- if (!IS_ERR(info->inter_clk))
+ if (!IS_ERR(info->inter_clk)) {
+ clk_disable_unprepare(info->inter_clk);
clk_put(info->inter_clk);
+ }
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
}
--
2.12.5
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next prev parent reply other threads:[~2019-11-26 11:51 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20191126115058epcas1p3caa6da2508caa5fbe71c202834184b15@epcas1p3.samsung.com>
2019-11-26 11:50 ` [v5, PATCH 0/5] Add cpufreq and cci devfreq for mt8183, and SVS support Andrew-sh.Cheng
2019-11-26 11:50 ` Andrew-sh.Cheng [this message]
2019-11-26 11:50 ` [v5, PATCH 2/5] dt-bindings: devfreq: add compatible for mt8183 cci devfreq Andrew-sh.Cheng
2019-12-17 2:38 ` Chanwoo Choi
2019-11-26 11:50 ` [v5, PATCH 3/5] devfreq: add mediatek " Andrew-sh.Cheng
2019-12-17 10:08 ` Chanwoo Choi
2019-11-26 11:50 ` [v5, PATCH 4/5] cpufreq: mediatek: add opp notification for SVS support Andrew-sh.Cheng
2019-11-27 8:36 ` Viresh Kumar
2019-12-09 6:56 ` andrew-sh.cheng
2019-12-10 6:43 ` Viresh Kumar
2020-03-10 8:11 ` andrew-sh.cheng
2020-03-11 6:06 ` Viresh Kumar
2020-03-12 9:12 ` andrew-sh.cheng
2020-03-13 7:22 ` andrew-sh.cheng
2020-03-13 9:10 ` Viresh Kumar
2020-04-06 9:12 ` andrew-sh.cheng
2020-04-06 9:29 ` Viresh Kumar
2020-04-07 6:54 ` andrew-sh.cheng
2020-04-07 8:29 ` Viresh Kumar
2020-04-07 9:09 ` andrew-sh.cheng
2019-11-26 11:50 ` [v5, PATCH 5/5] devfreq: mediatek: cci devfreq register " Andrew-sh.Cheng
2019-12-17 7:31 ` [v5, PATCH 0/5] Add cpufreq and cci devfreq for mt8183, and " Chanwoo Choi
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