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Tue, 26 Nov 2019 17:59:11 -0800 Received: from mtkmbs08n1.mediatek.inc (172.21.101.55) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 26 Nov 2019 17:59:19 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 27 Nov 2019 09:58:31 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 27 Nov 2019 09:58:19 +0800 From: Dennis YC Hsieh To: Rob Herring , Matthias Brugger , Jassi Brar Subject: [PATCH v2 08/14] soc: mediatek: cmdq: add write_s function Date: Wed, 27 Nov 2019 09:58:51 +0800 Message-ID: <1574819937-6246-10-git-send-email-dennis-yc.hsieh@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1574819937-6246-1-git-send-email-dennis-yc.hsieh@mediatek.com> References: <1574819937-6246-1-git-send-email-dennis-yc.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191126_175916_977136_6C3B6083 X-CRM114-Status: GOOD ( 11.62 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, Houlong Wei , Dennis YC Hsieh , linux-mediatek@lists.infradead.org, Bibby Hsieh , CK Hu , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org add write_s function in cmdq helper functions which writes value contains in internal register to address with large dma access support. Signed-off-by: Dennis YC Hsieh --- drivers/soc/mediatek/mtk-cmdq-helper.c | 40 ++++++++++++++++++++++++ include/linux/mailbox/mtk-cmdq-mailbox.h | 2 ++ include/linux/soc/mediatek/mtk-cmdq.h | 12 +++++++ 3 files changed, 54 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 9cc234f08ec5..2edbc0954d97 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -15,11 +15,18 @@ #define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \ << 32 | CMDQ_EOC_IRQ_EN) #define CMDQ_REG_TYPE 1 +#define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0))) +#define CMDQ_ADDR_LOW_BIT BIT(1) +#define CMDQ_ADDR_LOW(addr) ((u16)(addr) | CMDQ_ADDR_LOW_BIT) struct cmdq_instruction { union { u32 value; u32 mask; + struct { + u16 arg_c; + u16 arg_b; + }; }; union { u16 offset; @@ -224,6 +231,39 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, } EXPORT_SYMBOL(cmdq_pkt_write_mask); +int cmdq_pkt_write_s(struct cmdq_pkt *pkt, phys_addr_t addr, u16 reg_idx, + u32 mask) +{ + struct cmdq_instruction inst = { {0} }; + const u16 dst_reg_idx = CMDQ_SPR_TEMP; + int err; + + if (mask != U32_MAX) { + inst.op = CMDQ_CODE_MASK; + inst.mask = ~mask; + err = cmdq_pkt_append_command(pkt, inst); + if (err < 0) + return err; + + inst.mask = 0; + inst.op = CMDQ_CODE_WRITE_S_MASK; + } else { + inst.op = CMDQ_CODE_WRITE_S; + } + + err = cmdq_pkt_assign(pkt, dst_reg_idx, CMDQ_ADDR_HIGH(addr)); + if (err < 0) + return err; + + inst.arg_b_t = CMDQ_REG_TYPE; + inst.sop = dst_reg_idx; + inst.offset = CMDQ_ADDR_LOW(addr); + inst.arg_b = reg_idx; + + return cmdq_pkt_append_command(pkt, inst); +} +EXPORT_SYMBOL(cmdq_pkt_write_s); + int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event) { struct cmdq_instruction inst = { {0} }; diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h index 121c3bb6d3de..8ef87e1bd03b 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -59,6 +59,8 @@ enum cmdq_code { CMDQ_CODE_JUMP = 0x10, CMDQ_CODE_WFE = 0x20, CMDQ_CODE_EOC = 0x40, + CMDQ_CODE_WRITE_S = 0x90, + CMDQ_CODE_WRITE_S_MASK = 0x91, CMDQ_CODE_LOGIC = 0xa0, }; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index c66b3a0da2a2..56ff1970197c 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -106,6 +106,18 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value); int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value, u32 mask); +/** + * cmdq_pkt_write_s_mask() - append write_s command to the CMDQ packet + * @pkt: the CMDQ packet + * @addr: the physical address of register or dma + * @reg_idx: the CMDQ internal register ID which cache source value + * @mask: the specified target register mask + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_write_s(struct cmdq_pkt *pkt, phys_addr_t addr, u16 reg_idx, + u32 mask); + /** * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet * @pkt: the CMDQ packet -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek