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Mon, 02 Dec 2019 00:31:49 -0800 Received: from MTKMBS31DR.mediatek.inc (172.27.6.102) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 2 Dec 2019 00:32:29 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 2 Dec 2019 16:31:27 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 2 Dec 2019 16:31:28 +0800 Message-ID: <1575275504.31913.3.camel@mtksdaap41> Subject: Re: [PATCH v1] drm/mediatek: add ctm property support From: CK Hu To: Date: Mon, 2 Dec 2019 16:31:44 +0800 In-Reply-To: <1575275040.31913.1.camel@mtksdaap41> References: <1575271892-25117-1-git-send-email-yongqiang.niu@mediatek.com> <1575275040.31913.1.camel@mtksdaap41> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: EC37C633580B1C78F6E94A205743CD10F5331807D1C261A3CCCA324DBA6BEE902000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191202_003156_723074_76B5AE02 X-CRM114-Status: GOOD ( 20.97 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, Yongqiang: On Mon, 2019-12-02 at 16:24 +0800, CK Hu wrote: > Hi, Yongqiang: > > On Mon, 2019-12-02 at 15:31 +0800, yongqiang.niu@mediatek.com wrote: > > From: Yongqiang Niu > > > > add ctm property support > > > > Signed-off-by: Yongqiang Niu > > --- > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 7 +++- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 59 ++++++++++++++++++++++++++++- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++ > > 3 files changed, 72 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > > index 4fb346c..e7e3aa9 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > > @@ -666,10 +666,13 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, > > int i; > > > > if (crtc->state->color_mgmt_changed) > > - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) > > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { > > mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], > > crtc->state, > > mtk_crtc_state->cmdq_handle); > > + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); > > This patch is based on another patch which support cmdq. So I think this > patch would also support cmdq. > > > + } > > + > > #ifdef CONFIG_MTK_CMDQ > > if (mtk_crtc->cmdq_client) { > > drm_atomic_state_get(old_atomic_state); > > @@ -891,7 +894,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > > if (ret < 0) > > return ret; > > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); > > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE); > > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, true, MTK_LUT_SIZE); > > Only MT8183 has CCORR, I think you should enable ctm by SoC. (gamma has > the same problem) Amend: enable ctm according to the crtc which as ctm function. Regards, CK > > > priv->num_pipes++; > > #ifdef CONFIG_MTK_CMDQ > > mtk_crtc->cmdq_client = > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > index 9cc12af..4bbbac7 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > @@ -38,7 +38,15 @@ > > #define CCORR_EN BIT(0) > > #define DISP_CCORR_CFG 0x0020 > > #define CCORR_RELAY_MODE BIT(0) > > +#define CCORR_ENGINE_EN BIT(1) > > +#define CCORR_GAMMA_OFF BIT(2) > > +#define CCORR_WGAMUT_SRC_CLIP BIT(3) > > #define DISP_CCORR_SIZE 0x0030 > > +#define DISP_CCORR_COEF_0 0x0080 > > +#define DISP_CCORR_COEF_1 0x0084 > > +#define DISP_CCORR_COEF_2 0x0088 > > +#define DISP_CCORR_COEF_3 0x008C > > +#define DISP_CCORR_COEF_4 0x0090 > > > > #define DISP_DITHER_EN 0x0000 > > #define DITHER_EN BIT(0) > > @@ -187,7 +195,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > > { > > mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE); > > - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG); > > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG); > > } > > > > static void mtk_ccorr_start(struct mtk_ddp_comp *comp) > > @@ -200,6 +208,54 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp) > > writel_relaxed(0x0, comp->regs + DISP_CCORR_EN); > > } > > > > +/* Converts a DRM S31.32 value to the HW S0.11 format. */ > > +static u16 mtk_ctm_s31_32_to_s0_11(u64 in) > > +{ > > + u16 r; > > + > > + /* Sign bit. */ > > + r = in & BIT_ULL(63) ? BIT(11) : 0; > > + > > + if ((in & GENMASK_ULL(62, 33)) > 0) { > > if ((in & GENMASK_ULL(62, 32)) > 0) { > > > + /* We have zero integer bits so we can only saturate here. */ > > + r |= GENMASK(10, 0); > > + } else { > > + /* Otherwise take the 9 most important fractional bits. */ > > + r |= (in >> 22) & GENMASK(10, 0); > > r |= (in >> 21) & GENMASK(10, 0); > > Regards, > CK > > > + } > > + > > + return r; > > +} > > + > > +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp, > > + struct drm_crtc_state *state) > > +{ > > + struct drm_property_blob *blob = state->ctm; > > + struct drm_color_ctm *ctm; > > + const u64 *input; > > + uint16_t coeffs[9] = { 0 }; > > + int i; > > + > > + if (!blob) > > + return; > > + > > + ctm = (struct drm_color_ctm *)blob->data; > > + input = ctm->matrix; > > + > > + for (i = 0; i < ARRAY_SIZE(coeffs); i++) > > + coeffs[i] = mtk_ctm_s31_32_to_s0_11(input[i]); > > + > > + writel_relaxed(coeffs[0] << 16 | coeffs[1], > > + comp->regs + DISP_CCORR_COEF_0); > > + writel_relaxed(coeffs[2] << 16 | coeffs[3], > > + comp->regs + DISP_CCORR_COEF_1); > > + writel_relaxed(coeffs[4] << 16 | coeffs[5], > > + comp->regs + DISP_CCORR_COEF_2); > > + writel_relaxed(coeffs[6] << 16 | coeffs[7], > > + comp->regs + DISP_CCORR_COEF_3); > > + writel_relaxed(coeffs[8] << 16, comp->regs + DISP_CCORR_COEF_4); > > +} > > + > > static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, > > unsigned int h, unsigned int vrefresh, > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > > @@ -269,6 +325,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp, > > .config = mtk_ccorr_config, > > .start = mtk_ccorr_start, > > .stop = mtk_ccorr_stop, > > + .ctm_set = mtk_ccorr_ctm_set, > > }; > > > > static const struct mtk_ddp_comp_funcs ddp_dither = { > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > index 5b0a3d4..5100c3d 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > @@ -95,6 +95,8 @@ struct mtk_ddp_comp_funcs { > > struct cmdq_pkt *cmdq_pkt); > > void (*bgclr_in_on)(struct mtk_ddp_comp *comp); > > void (*bgclr_in_off)(struct mtk_ddp_comp *comp); > > + void (*ctm_set)(struct mtk_ddp_comp *comp, > > + struct drm_crtc_state *state); > > }; > > > > struct mtk_ddp_comp { > > @@ -213,6 +215,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp) > > comp->funcs->bgclr_in_off(comp); > > } > > > > +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp, > > + struct drm_crtc_state *state) > > +{ > > + if (comp->funcs && comp->funcs->ctm_set) > > + comp->funcs->ctm_set(comp, state); > > +} > > + > > int mtk_ddp_comp_get_id(struct device_node *node, > > enum mtk_ddp_comp_type comp_type); > > int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node, > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek