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Mon, 02 Dec 2019 17:38:37 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 2 Dec 2019 17:38:47 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 Dec 2019 09:38:19 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 3 Dec 2019 09:38:14 +0800 Message-ID: <1575337114.1155.4.camel@mtksdaap41> Subject: Re: [PATCH v1 6/6] drm/mediatek: apply CMDQ control flow From: CK Hu To: Bibby Hsieh Date: Tue, 3 Dec 2019 09:38:34 +0800 In-Reply-To: <20191128024238.9399-7-bibby.hsieh@mediatek.com> References: <20191128024238.9399-1-bibby.hsieh@mediatek.com> <20191128024238.9399-7-bibby.hsieh@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191202_173842_413419_F9D554DF X-CRM114-Status: GOOD ( 20.42 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drinkcat@chromium.org, Yongqiang Niu , srv_heupstream@mediatek.com, David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, tfiga@chromium.org, Thierry Reding , linux-mediatek@lists.infradead.org, Philipp Zabel , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, Bibby: On Thu, 2019-11-28 at 10:42 +0800, Bibby Hsieh wrote: > Unlike other SoCs, MT8183 does not have "shadow" > registers for performaing an atomic video mode > set or page flip at vblank/vsync. > > The CMDQ (Commend Queue) in MT8183 is used to help > update all relevant display controller registers > with critical time limation. > > Signed-off-by: YT Shen > Signed-off-by: CK Hu > Signed-off-by: Philipp Zabel > Signed-off-by: Bibby Hsieh > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 86 ++++++++++++++++++++- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 31 ++++++++ > 2 files changed, 113 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index fcf4e755e0bd..1b4e537ac3c1 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -12,6 +12,8 @@ > #include > #include > #include > +#include > +#include > > #include "mtk_drm_drv.h" > #include "mtk_drm_crtc.h" > @@ -42,6 +44,9 @@ struct mtk_drm_crtc { > unsigned int layer_nr; > bool pending_planes; > > + struct cmdq_client *cmdq_client; > + u32 cmdq_event; > + > void __iomem *config_regs; > const struct mtk_mmsys_reg_data *mmsys_reg_data; > struct mtk_disp_mutex *mutex; > @@ -56,6 +61,11 @@ struct mtk_crtc_state { > unsigned int pending_width; > unsigned int pending_height; > unsigned int pending_vrefresh; > + struct cmdq_pkt *cmdq_handle; > +}; > + > +struct mtk_cmdq_cb_data { > + struct cmdq_pkt *cmdq_handle; > }; > > static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) > @@ -229,6 +239,46 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, > return NULL; > } > > +#ifdef CONFIG_MTK_CMDQ > +static void ddp_cmdq_cb(struct cmdq_cb_data data) > +{ > + struct mtk_cmdq_cb_data *cb_data = data.data; > + > + cmdq_pkt_destroy(cb_data->cmdq_handle); > + kfree(cb_data); > +} > + > +static void mtk_cmdq_acquire(struct drm_crtc *crtc) > +{ > + struct mtk_crtc_state *mtk_crtc_state = > + to_mtk_crtc_state(crtc->state); > + struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); > + > + mtk_crtc_state->cmdq_handle = > + cmdq_pkt_create(mtk_crtc->cmdq_client, > + PAGE_SIZE); I would like to remove atomic feature in cmdq driver and drm driver could reuse the pkt. Please refer to [1] for detail. [1] http://lists.infradead.org/pipermail/linux-mediatek/2019-January/016866.html > + cmdq_pkt_clear_event(mtk_crtc_state->cmdq_handle, > + mtk_crtc->cmdq_event); > + cmdq_pkt_wfe(mtk_crtc_state->cmdq_handle, mtk_crtc->cmdq_event); > +} > + > +static void mtk_cmdq_release(struct drm_crtc *crtc) > +{ > + struct mtk_crtc_state *mtk_crtc_state = > + to_mtk_crtc_state(crtc->state); > + struct mtk_cmdq_cb_data *cb_data; > + > + cb_data = kmalloc(sizeof(*cb_data), GFP_KERNEL); > + if (!cb_data) { > + DRM_DEV_ERROR(crtc->dev->dev, "Failed to alloc cb_data\n"); > + return; > + } > + > + cb_data->cmdq_handle = mtk_crtc_state->cmdq_handle; > + cmdq_pkt_flush_async(mtk_crtc_state->cmdq_handle, > + ddp_cmdq_cb, cb_data); > +} > +#endif > static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) > { > struct drm_crtc *crtc = &mtk_crtc->base; > @@ -383,7 +433,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) > if (state->pending_config) { > mtk_ddp_comp_config(comp, state->pending_width, > state->pending_height, > - state->pending_vrefresh, 0, NULL); > + state->pending_vrefresh, 0, > + state->cmdq_handle); > > state->pending_config = false; > } > @@ -403,7 +454,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) > > if (comp) > mtk_ddp_comp_layer_config(comp, local_layer, > - plane_state, NULL); > + plane_state, > + state->cmdq_handle); > plane_state->pending.config = false; > } > mtk_crtc->pending_planes = false; > @@ -454,6 +506,13 @@ void mtk_drm_crtc_cursor_update(struct drm_crtc *crtc, struct drm_plane *plane, > mtk_crtc_ddp_config(crtc); > mtk_disp_mutex_release(mtk_crtc->mutex); > } > +#ifdef CONFIG_MTK_CMDQ > + if (mtk_crtc->cmdq_client) { > + mtk_cmdq_acquire(crtc); > + mtk_crtc_ddp_config(crtc); > + mtk_cmdq_release(crtc); > + } > +#endif > mutex_unlock(&priv->hw_lock); > } > > @@ -570,6 +629,13 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, > mtk_crtc_ddp_config(crtc); > mtk_disp_mutex_release(mtk_crtc->mutex); > } > +#ifdef CONFIG_MTK_CMDQ > + if (mtk_crtc->cmdq_client) { > + mtk_cmdq_acquire(crtc); > + mtk_crtc_ddp_config(crtc); > + mtk_cmdq_release(crtc); > + } > +#endif This part is almost the same as the one in mtk_drm_crtc_cursor_update(), try to merge them. > } > > static const struct drm_crtc_funcs mtk_crtc_funcs = { > @@ -619,7 +685,7 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) > struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); > struct mtk_drm_private *priv = crtc->dev->dev_private; > > - if (!priv->data->shadow_register) > + if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) > mtk_crtc_ddp_config(crtc); > > mtk_drm_finish_page_flip(mtk_crtc); > @@ -761,6 +827,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); > drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE); > priv->num_pipes++; > - > +#ifdef CONFIG_MTK_CMDQ > + mtk_crtc->cmdq_client = > + cmdq_mbox_create(dev, drm_crtc_index(&mtk_crtc->base), > + 2000); > + of_property_read_u32_index(dev->of_node, "mediatek,gce-events", > + drm_crtc_index(&mtk_crtc->base), > + &mtk_crtc->cmdq_event); > + if (IS_ERR(mtk_crtc->cmdq_client)) { > + dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", > + drm_crtc_index(&mtk_crtc->base)); > + mtk_crtc->cmdq_client = NULL; > + } > +#endif > return 0; > } > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 6d0f349ddf82..9cc12af2bc06 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -370,6 +370,9 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, > const struct mtk_ddp_comp_funcs *funcs) > { > struct platform_device *comp_pdev; > + struct resource res; > + struct cmdq_client_reg *cmdq_reg; > + int ret = 0; > > if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX) > return -EINVAL; > @@ -404,6 +407,34 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, > } > comp->dev = &comp_pdev->dev; > > +#ifdef CONFIG_MTK_CMDQ > + if (of_address_to_resource(node, 0, &res) != 0) { > + dev_err(dev, "Missing reg in %s node\n", > + node->full_name); > + return -EINVAL; > + } > + comp->regs_pa = res.start; > + > + comp_pdev = of_find_device_by_node(node); > + if (!comp_pdev) { > + dev_warn(dev, "Waiting for component device %s\n", > + node->full_name); > + return -EPROBE_DEFER; > + } > + > + cmdq_reg = kzalloc(sizeof(*cmdq_reg), GFP_KERNEL); > + if (!cmdq_reg) > + return -EINVAL; > + > + ret = cmdq_dev_get_client_reg(&comp_pdev->dev, cmdq_reg, 0); > + if (ret != 0) > + dev_dbg(&comp_pdev->dev, > + "get mediatek,gce-client-reg fail!\n"); > + else > + comp->subsys = cmdq_reg->subsys; > + > + kfree(cmdq_reg); > +#endif I would like to move this part to the patch "drm/mediatek: support CMDQ interface in ddp component". Regards, CK > return 0; > } > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek