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From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Cc: James Liao <jamesjj.liao@mediatek.com>,
	Nicolas Boichat <drinkcat@chromium.org>,
	srv_heupstream@mediatek.com, Rob Herring <robh@kernel.org>,
	Enric Balletbo Serra <eballetbo@gmail.com>,
	linux-kernel@vger.kernel.org, Fan Chen <fan.chen@mediatek.com>,
	linux-mediatek@lists.infradead.org,
	Sascha Hauer <kernel@pengutronix.de>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v14 03/11] soc: mediatek: Add basic_clk_name to scp_power_data
Date: Fri, 15 May 2020 11:35:24 +0800	[thread overview]
Message-ID: <1589513724.16252.3.camel@mtksdaap41> (raw)
In-Reply-To: <1589176947.21832.9.camel@mtksdaap41>

On Mon, 2020-05-11 at 14:02 +0800, Weiyi Lu wrote:
> On Wed, 2020-05-06 at 23:01 +0200, Enric Balletbo i Serra wrote:
> > Hi Weiyi,
> > 
> > Thank you for your patch.
> > 
> > On 6/5/20 10:15, Weiyi Lu wrote:
> > > Try to stop extending the clk_id or clk_names if there are
> > > more and more new BASIC clocks. To get its own clocks by the
> > > basic_clk_name of each power domain.
> > > And then use basic_clk_name strings for all compatibles, instead of
> > > mixing clk_id and clk_name.
> > > 
> > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > > Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> > > ---
> > >  drivers/soc/mediatek/mtk-scpsys.c | 134 ++++++++++++--------------------------
> > >  1 file changed, 41 insertions(+), 93 deletions(-)
> > > 
> > > diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> > > index f669d37..c9c3cf7 100644
> > > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > > @@ -78,34 +78,6 @@
> > >  #define PWR_STATUS_HIF1			BIT(26)	/* MT7622 */
> > >  #define PWR_STATUS_WB			BIT(27)	/* MT7622 */
> > >  
> > > -enum clk_id {
> > > -	CLK_NONE,
> > > -	CLK_MM,
> > > -	CLK_MFG,
> > > -	CLK_VENC,
> > > -	CLK_VENC_LT,
> > > -	CLK_ETHIF,
> > > -	CLK_VDEC,
> > > -	CLK_HIFSEL,
> > > -	CLK_JPGDEC,
> > > -	CLK_AUDIO,
> > > -	CLK_MAX,
> > > -};
> > > -
> > > -static const char * const clk_names[] = {
> > > -	NULL,
> > > -	"mm",
> > > -	"mfg",
> > > -	"venc",
> > > -	"venc_lt",
> > > -	"ethif",
> > > -	"vdec",
> > > -	"hif_sel",
> > > -	"jpgdec",
> > > -	"audio",
> > > -	NULL,
> > > -};
> > > -
> > >  #define MAX_CLKS	3
> > >  
> > >  /**
> > > @@ -116,7 +88,7 @@ enum clk_id {
> > >   * @sram_pdn_bits: The mask for sram power control bits.
> > >   * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> > >   * @bus_prot_mask: The mask for single step bus protection.
> > > - * @clk_id: The basic clocks required by this power domain.
> > > + * @basic_clk_name: The basic clocks required by this power domain.
> > >   * @caps: The flag for active wake-up action.
> > >   */
> > >  struct scp_domain_data {
> > > @@ -126,7 +98,7 @@ struct scp_domain_data {
> > >  	u32 sram_pdn_bits;
> > >  	u32 sram_pdn_ack_bits;
> > >  	u32 bus_prot_mask;
> > > -	enum clk_id clk_id[MAX_CLKS];
> > > +	const char *basic_clk_name[MAX_CLKS];
> > 
> > I only reviewed v13, so sorry if this was already discussed. I am wondering if
> > would be better take advantage of the devm_clk_bulk_get() function instead of
> > kind of reimplementing the same, something like this
> > 
> > 	const struct clk_bulk_data *basic_clocks;
> > 
> 
> I thought it should be const struct clk_bulk_data
> basic_clocks[MAX_CLKS]; instead of const struct clk_bulk_data
> *basic_clocks; in struct scp_domain_data data type
> 
> > >  	u8 caps;
> > >  };
> > >  
> > > @@ -411,12 +383,19 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> > >  	return ret;
> > >  }
> > >  
> > > -static void init_clks(struct platform_device *pdev, struct clk **clk)
> > > +static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
> > > +			const char * const *name)
> > >  {
> > >  	int i;
> > >  
> > > -	for (i = CLK_NONE + 1; i < CLK_MAX; i++)
> > > -		clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
> > > +	for (i = 0; i < MAX_CLKS && name[i]; i++) {
> > > +		clk[i] = devm_clk_get(&pdev->dev, name[i]);
> > > +
> > > +		if (IS_ERR(clk[i]))
> > > +			return PTR_ERR(clk[i]);
> > > +	}
> > 
> > You will be able to remove this function, see below ...
> > 
> > > +
> > > +	return 0;
> > >  }
> > >  
> > >  static struct scp *init_scp(struct platform_device *pdev,
> > > @@ -426,9 +405,8 @@ static struct scp *init_scp(struct platform_device *pdev,
> > >  {
> > >  	struct genpd_onecell_data *pd_data;
> > >  	struct resource *res;
> > > -	int i, j;
> > > +	int i, ret;
> > >  	struct scp *scp;
> > > -	struct clk *clk[CLK_MAX];
> > >  
> > >  	scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
> > >  	if (!scp)
> > > @@ -481,8 +459,6 @@ static struct scp *init_scp(struct platform_device *pdev,
> > >  
> > >  	pd_data->num_domains = num;
> > >  
> > > -	init_clks(pdev, clk);
> > > -
> > >  	for (i = 0; i < num; i++) {
> > >  		struct scp_domain *scpd = &scp->domains[i];
> > >  		struct generic_pm_domain *genpd = &scpd->genpd;
> > > @@ -493,17 +469,9 @@ static struct scp *init_scp(struct platform_device *pdev,
> > >  
> > >  		scpd->data = data;
> > >  
> > > -		for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
> > > -			struct clk *c = clk[data->clk_id[j]];
> > > -
> > > -			if (IS_ERR(c)) {
> > > -				dev_err(&pdev->dev, "%s: clk unavailable\n",
> > > -					data->name);
> > > -				return ERR_CAST(c);
> > > -			}
> > > -
> > > -			scpd->clk[j] = c;
> > > -		}
> > > +		ret = init_basic_clks(pdev, scpd->clk, data->basic_clk_name);
> > > +		if (ret)
> > > +			return ERR_PTR(ret);
> > 
> > Just call:
> > 
> > 	ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(basic_clocks),
> > 				data->basic_clocks);
> > 	if (ret)
> > 		return ERR_PTR(ret);
> > 
> > >  
> > >  		genpd->name = data->name;
> > >  		genpd->power_off = scpsys_power_off;
> > > @@ -560,7 +528,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > >  		.ctl_offs = SPM_CONN_PWR_CON,
> > >  		.bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> > >  				 MT2701_TOP_AXI_PROT_EN_CONN_S,
> > > -		.clk_id = {CLK_NONE},
> > >  		.caps = MTK_SCPD_ACTIVE_WAKEUP,
> > >  	},
> > >  	[MT2701_POWER_DOMAIN_DISP] = {
> > > @@ -568,7 +535,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > >  		.sta_mask = PWR_STATUS_DISP,
> > >  		.ctl_offs = SPM_DIS_PWR_CON,
> > >  		.sram_pdn_bits = GENMASK(11, 8),
> > > -		.clk_id = {CLK_MM},
> > > +		.basic_clk_name = {"mm"},
> > 
> > 		.basic_clocks[] = {
> > 			{ .id = "mm" },
> > 		};
> > 
> 
> Those basic clocks without given a name (name: null) would get incorrect
> clock via clk_bulk_get(...) due to 
> 
> /**
>  * of_parse_clkspec() - Parse a DT clock specifier for a given device
> node
>  * @np: device node to parse clock specifier from
>  * @index: index of phandle to parse clock out of. If index < 0, @name
> is used
>  * @name: clock name to find and parse. If name is NULL, the index is
> used
> 
> And the index is 0 here in this callstack
> 
> I guess something need to be improved before we use the clk_bulk_ APIs.
> 

Hi Enric,

According to the result above, is it necessary to change the APIs or
maybe I should send the next version v15 first to fix other problems you
mentioned? Many thanks.

> 
> > >  		.bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
> > >  		.caps = MTK_SCPD_ACTIVE_WAKEUP,
> > >  	},
> > > @@ -578,7 +545,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > >  		.ctl_offs = SPM_MFG_PWR_CON,
> > >  		.sram_pdn_bits = GENMASK(11, 8),
> > >  		.sram_pdn_ack_bits = GENMASK(12, 12),
> > > -		.clk_id = {CLK_MFG},
> > > +		.basic_clk_name = {"mfg"},
> > 
> > 		.basic_clocks[] = {
> > 			{ .id = "mfg" },
> > 		};
> > 
> > >  		.caps = MTK_SCPD_ACTIVE_WAKEUP,
> > >  	},
> > >  	[MT2701_POWER_DOMAIN_VDEC] = {
> > > @@ -587,7 +554,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > >  		.ctl_offs = SPM_VDE_PWR_CON,
> > >  		.sram_pdn_bits = GENMASK(11, 8),
> > >  		.sram_pdn_ack_bits = GENMASK(12, 12),
> > > -		.clk_id = {CLK_MM},
> > > +		.basic_clk_name = {"mm"},
> > 
> > ...
> > 
> > [snip]
> 
> 

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  reply	other threads:[~2020-05-15  3:36 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-06  8:15 [PATCH v14 00/11] Mediatek MT8183 scpsys support Weiyi Lu
2020-05-06  8:15 ` [PATCH v14 01/11] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
2020-05-06 20:59   ` Enric Balletbo i Serra
2020-05-11  6:00     ` Weiyi Lu
2020-05-06  8:15 ` [PATCH v14 02/11] dt-bindings: soc: Add MT8183 power dt-bindings Weiyi Lu
2020-05-06 21:00   ` Enric Balletbo i Serra
2020-05-11  6:01     ` Weiyi Lu
2020-05-06  8:15 ` [PATCH v14 03/11] soc: mediatek: Add basic_clk_name to scp_power_data Weiyi Lu
2020-05-06 21:01   ` Enric Balletbo i Serra
2020-05-11  6:02     ` Weiyi Lu
2020-05-15  3:35       ` Weiyi Lu [this message]
2020-05-18 17:52         ` Enric Balletbo i Serra
2020-05-21  3:28           ` Weiyi Lu
2020-05-06  8:15 ` [PATCH v14 04/11] soc: mediatek: Remove infracfg misc driver support Weiyi Lu
2020-05-06 21:00   ` Enric Balletbo i Serra
2020-05-11  6:03     ` Weiyi Lu
2020-05-06  8:15 ` [PATCH v14 05/11] soc: mediatek: Add multiple step bus protection control Weiyi Lu
2020-05-06  8:15 ` [PATCH v14 06/11] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
2020-05-06  8:15 ` [PATCH v14 07/11] soc: mediatek: Add extra sram control Weiyi Lu
2020-05-06  8:16 ` [PATCH v14 08/11] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2020-05-06  8:16 ` [PATCH v14 09/11] soc: mediatek: Add a comma at the end Weiyi Lu
2020-05-06  8:16 ` [PATCH v14 10/11] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
2020-05-06  8:16 ` [PATCH v14 11/11] arm64: dts: Add power-domains property to mfgcfg Weiyi Lu

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