From: EastL <EastL.Lee@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
wsd_upstream@mediatek.com, Sean Wang <sean.wang@mediatek.com>,
linux-kernel@vger.kernel.org, vkoul@kernel.org,
robh+dt@kernel.org, linux-mediatek@lists.infradead.org,
dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
Date: Wed, 1 Jul 2020 16:38:36 +0800 [thread overview]
Message-ID: <1593592716.26931.1.camel@mtkswgap22> (raw)
In-Reply-To: <4fc5f4b9-8f03-74b4-8bc9-bf86a6246ff0@gmail.com>
On Fri, 2020-06-19 at 11:36 +0200, Matthias Brugger wrote:
>
> On 19/06/2020 10:04, EastL wrote:
> > Document the devicetree bindings for MediaTek Command-Queue DMA controller
> > which could be found on MT6779 SoC or other similar Mediatek SoCs.
> >
> > Signed-off-by: EastL <EastL.Lee@mediatek.com>
>
> Still missing the full name.
Sorry I thought it was only needed in the yaml file
I will fix in next version.
>
> > ---
> > .../devicetree/bindings/dma/mtk-cqdma.yaml | 114 +++++++++++++++++++++
> > 1 file changed, 114 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> > new file mode 100644
> > index 0000000..e6fdf05
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> > @@ -0,0 +1,114 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>
> You missed the brackets ().
OK
>
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek Command-Queue DMA controller Device Tree Binding
> > +
> > +maintainers:
> > + - EastL Lee <EastL.Lee@mediatek.com>
> > +
> > +description:
> > + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC
> > + is dedicated to memory-to-memory transfer through queue based
> > + descriptor management.
> > +
> > +allOf:
> > + - $ref: "dma-controller.yaml#"
> > +
> > +properties:
> > + "#dma-cells":
> > + minimum: 1
> > + maximum: 255
> > + description:
> > + Used to provide DMA controller specific information.
> > +
> > + compatible:
> > + oneOf:
> > + - const: mediatek,common-cqdma
>
> What is the common-cqdma for if we have only one compatible specifying the SoC.
> Actually I'm not a great fan of the common-cqdma thing. I'd prefer a fallback
> compatible that has the name of the first SoC implementing the same device.
>
> Regards,
> Matthias
>
OK, I'll remove common compatible.
> > + - const: mediatek,mt6765-cqdma
> > + - const: mediatek,mt6779-cqdma
> > +
> > + reg:
> > + minItems: 1
> > + maxItems: 5
> > + description:
> > + A base address of MediaTek Command-Queue DMA controller,
> > + a channel will have a set of base address.
> > +
> > + interrupts:
> > + minItems: 1
> > + maxItems: 5
> > + description:
> > + A interrupt number of MediaTek Command-Queue DMA controller,
> > + one interrupt number per dma-channels.
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + clock-names:
> > + const: cqdma
> > +
> > + dma-channel-mask:
> > + $ref: /schemas/types.yaml#definitions/uint32
> > + description:
> > + For DMA capability, We will know the addressing capability of
> > + MediaTek Command-Queue DMA controller through dma-channel-mask.
> > + items:
> > + minItems: 1
> > + maxItems: 63
> > +
> > + dma-channels:
> > + $ref: /schemas/types.yaml#definitions/uint32
> > + description:
> > + Number of DMA channels supported by MediaTek Command-Queue DMA
> > + controller, support up to five.
> > + items:
> > + minItems: 1
> > + maxItems: 5
> > +
> > + dma-requests:
> > + $ref: /schemas/types.yaml#definitions/uint32
> > + description:
> > + Number of DMA request (virtual channel) supported by MediaTek
> > + Command-Queue DMA controller, support up to 32.
> > + items:
> > + minItems: 1
> > + maxItems: 32
> > +
> > +required:
> > + - "#dma-cells"
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
> > + - dma-channel-mask
> > + - dma-channels
> > + - dma-requests
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/clock/mt6779-clk.h>
> > + cqdma: dma-controller@10212000 {
> > + compatible = "mediatek,mt6779-cqdma";
> > + reg = <0x10212000 0x80>,
> > + <0x10212080 0x80>,
> > + <0x10212100 0x80>;
> > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>;
> > + clock-names = "cqdma";
> > + dma-channel-mask = <63>;
> > + dma-channels = <3>;
> > + dma-requests = <32>;
> > + #dma-cells = <1>;
> > + };
> > +
> > +...
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
next prev parent reply other threads:[~2020-07-01 8:46 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-19 8:04 [PATCH v5] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue EastL
2020-06-19 8:04 ` [PATCH v5 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings EastL
2020-06-19 9:36 ` Matthias Brugger
2020-07-01 8:38 ` EastL [this message]
2020-07-01 15:06 ` Matthias Brugger
2020-06-19 8:05 ` [PATCH v5 2/4] dmaengine: mediatek-cqdma: remove redundant queue structure EastL
2020-06-19 8:05 ` [PATCH v5 3/4] dmaengine: mediatek-cqdma: add dma mask for capability EastL
2020-06-19 9:39 ` Matthias Brugger
2020-07-01 9:01 ` EastL
2020-06-19 8:05 ` [PATCH v5 4/4] dmaengine: mediatek-cqdma: fix compatible EastL
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1593592716.26931.1.camel@mtkswgap22 \
--to=eastl.lee@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=dmaengine@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=mark.rutland@arm.com \
--cc=matthias.bgg@gmail.com \
--cc=robh+dt@kernel.org \
--cc=sean.wang@mediatek.com \
--cc=vkoul@kernel.org \
--cc=wsd_upstream@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).