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Tue, 08 Sep 2020 05:38:54 -0800 Received: from MTKMBS31N1.mediatek.inc (172.27.4.69) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Sep 2020 06:28:51 -0700 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Sep 2020 21:28:48 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 8 Sep 2020 21:28:48 +0800 Message-ID: <1599571618.14806.7.camel@mhfsdcap03> Subject: Re: [v4,4/4] arm64: dts: mt8192: add infracfg_rst node From: Crystal Guo To: Suman Anna Date: Tue, 8 Sep 2020 21:26:58 +0800 In-Reply-To: <211bd78f-3b70-1e65-eea9-75cc73a3dfdd@ti.com> References: <20200817030324.5690-1-crystal.guo@mediatek.com> <20200817030324.5690-5-crystal.guo@mediatek.com> <211bd78f-3b70-1e65-eea9-75cc73a3dfdd@ti.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: E2B71D7CF58B128302A1F43348A6FECCA6782FE097627415268B005A7ADAC0792000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_093903_522081_BBBF4D89 X-CRM114-Status: GOOD ( 18.57 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , Yong Liang =?UTF-8?Q?=28=E6=A2=81=E5=8B=87=29?= , srv_heupstream , Seiya Wang =?UTF-8?Q?=28=E7=8E=8B=E8=BF=BA=E5=90=9B=29?= , "linux-kernel@vger.kernel.org" , Fan Chen =?UTF-8?Q?=28=E9=99=B3=E5=87=A1=29?= , "robh+dt@kernel.org" , "linux-mediatek@lists.infradead.org" , "p.zabel@pengutronix.de" , "matthias.bgg@gmail.com" , Yingjoe Chen =?UTF-8?Q?=28=E9=99=B3=E8=8B=B1=E6=B4=B2=29?= , Stanley Chu =?UTF-8?Q?=28=E6=9C=B1=E5=8E=9F=E9=99=9E=29?= , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, 2020-09-03 at 07:29 +0800, Suman Anna wrote: > Hi Crystal, > > On 8/16/20 10:03 PM, Crystal Guo wrote: > > add infracfg_rst node which is for MT8192 platform > > > > Signed-off-by: Crystal Guo > > I understand you are posting these together for complete reference, but driver > subsystem maintainers typically don't pick dts patches. In anycase, can you > clarify if your registers are self-clearing registers? > > regards > Suman > Hi Suman, Thanks for your reply. Our reset registers are not self-clearing, it needs to set the clear bit to 1 to clear the related bit. And should I separate this dts patch from the patch sets? regards Crystal > > --- > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 ++++++++++- > > 1 file changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index 931e1ca17220..a0cb9904706b 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -10,6 +10,7 @@ > > #include > > #include > > #include > > +#include > > > > / { > > compatible = "mediatek,mt8192"; > > @@ -219,9 +220,17 @@ > > }; > > > > infracfg: infracfg@10001000 { > > - compatible = "mediatek,mt8192-infracfg", "syscon"; > > + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; > > reg = <0 0x10001000 0 0x1000>; > > #clock-cells = <1>; > > + > > + infracfg_rst: reset-controller { > > + compatible = "mediatek,infra-reset", "ti,syscon-reset"; > > + #reset-cells = <1>; > > + ti,reset-bits = < > > + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: pcie */ > > + >; > > + }; > > }; > > > > pericfg: pericfg@10003000 { > > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek