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Sun, 25 Oct 2020 23:42:03 -0800 Received: from MTKMBS31DR.mediatek.inc (172.27.6.102) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Oct 2020 00:42:01 -0700 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Oct 2020 15:41:23 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Oct 2020 15:41:22 +0800 Message-ID: <1603698083.26323.87.camel@mhfsdcap03> Subject: Re: [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek From: Yong Wu To: Robin Murphy Date: Mon, 26 Oct 2020 15:41:23 +0800 In-Reply-To: References: <20200930070647.10188-1-yong.wu@mediatek.com> <20200930070647.10188-12-yong.wu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 020A65BDCF4EA27467567D031B54810B516A69E7C2B6BB71FC4C0F5EDD0582DF2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201026_034227_546086_9C295E00 X-CRM114-Status: GOOD ( 25.01 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, kernel-team@android.com, Joerg Roedel , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Krzysztof Kozlowski , Matthias Brugger , ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Fri, 2020-10-23 at 15:10 +0100, Robin Murphy wrote: > On 2020-09-30 08:06, Yong Wu wrote: > > The standard input iova bits is 32. MediaTek quad the lvl1 pagetable > > (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach > > 34bit. > > > > Signed-off-by: Yong Wu > > --- > > drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++--- > > drivers/iommu/mtk_iommu.c | 2 +- > > 2 files changed, 11 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c > > index 8362fdf76657..306bae2755ed 100644 > > --- a/drivers/iommu/io-pgtable-arm-v7s.c > > +++ b/drivers/iommu/io-pgtable-arm-v7s.c > > @@ -50,10 +50,17 @@ > > */ > > #define ARM_V7S_ADDR_BITS 32 > > #define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4) > > +/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */ > > +#define _ARM_V7S_LVL_BITS_MTK(lvl) (20 - (lvl) * 6) > > This should defined in terms of both lvl and cfg->ias. The formula here > is nothing more than a disgusting trick I made up since a linear > interpolation happened to fit the required numbers. That said, all of > these bits pretending that short-descriptor is a well-defined recursive > format only served to allow the rest of the code to look more like the > LPAE code - IIRC they've already diverged a fair bit since then, so > frankly a lot of this could stand to be unpicked and made considerably > clearer by simply accepting that level 1 and level 2 are different from > each other. If the formula is not good and make it clearer, How about this? /* * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2, -* and 12 bits in a page. With some carefully-chosen coefficients we can -* hide the ugly inconsistencies behind these macros and at least let the -* rest of the code pretend to be somewhat sane. +* and 12 bits in a page. +* +* MediaTek extend 2 bits to reach 34 bits, 14 bits at lvl1 and 8 bits at lvl2. */ -#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4) +#define _ARM_V7S_LVL1_BITS_NR(cfg) (((cfg)->ias == 32) ? 12 : 14) +#define _ARM_V7S_LVL2_BITS_NR 8 + +#define _ARM_V7S_LVL_BITS(lvl, cfg) \ + (((lvl) == 1) ? _ARM_V7S_LVL1_BITS_NR(cfg):_ARM_V7S_LVL2_BITS_NR) > Robin. > > > #define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl))) > > #define ARM_V7S_TABLE_SHIFT 10 > > > > -#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl)) > > +#define ARM_V7S_PTES_PER_LVL(lvl, cfg) ({ \ > > + int _lvl = lvl; \ > > + !arm_v7s_is_mtk_enabled(cfg) ? \ > > + (1 << _ARM_V7S_LVL_BITS(_lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(_lvl));\ > > +}) > > + > > #define ARM_V7S_TABLE_SIZE(lvl, cfg) \ > > (ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte)) > > > > @@ -63,7 +70,7 @@ > > #define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1) > > #define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \ > > int _l = lvl; \ > > - ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \ > > + ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \ > > }) > > > > /* > > @@ -755,7 +762,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > > { > > struct arm_v7s_io_pgtable *data; > > > > - if (cfg->ias > ARM_V7S_ADDR_BITS) > > + if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) > > return NULL; > > > > if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS)) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index f6a2e3eb59d2..6e85c9976a33 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) > > IO_PGTABLE_QUIRK_TLBI_ON_MAP | > > IO_PGTABLE_QUIRK_ARM_MTK_EXT, > > .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, > > - .ias = 32, > > + .ias = 34, > > .oas = 35, > > .tlb = &mtk_iommu_flush_ops, > > .iommu_dev = data->dev, > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek