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Wed, 11 Nov 2020 00:28:39 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 11 Nov 2020 00:28:37 -0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 11 Nov 2020 16:28:35 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 11 Nov 2020 16:28:36 +0800 Message-ID: <1605083317.32073.5.camel@mtkswgap22> Subject: Re: [v6,1/3] dt-binding: reset-controller: mediatek: add YAML schemas From: Stanley Chu To: Crystal Guo , "p.zabel@pengutronix.de" , "matthias.bgg@gmail.com" , Suman Anna Date: Wed, 11 Nov 2020 16:28:37 +0800 In-Reply-To: <1602682204.14806.53.camel@mhfsdcap03> References: <20200930022159.5559-1-crystal.guo@mediatek.com> <20200930022159.5559-2-crystal.guo@mediatek.com> <1602682204.14806.53.camel@mhfsdcap03> X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_032850_763435_C55EB179 X-CRM114-Status: GOOD ( 20.11 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , Yong Liang =?UTF-8?Q?=28=E6=A2=81=E5=8B=87=29?= , srv_heupstream , Seiya Wang =?UTF-8?Q?=28=E7=8E=8B=E8=BF=BA=E5=90=9B=29?= , "linux-kernel@vger.kernel.org" , Fan Chen =?UTF-8?Q?=28=E9=99=B3=E5=87=A1=29?= , "robh+dt@kernel.org" , "linux-mediatek@lists.infradead.org" , Yingjoe Chen =?UTF-8?Q?=28=E9=99=B3=E8=8B=B1=E6=B4=B2=29?= , "s-anna@ti.com" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi Matthias, Philipp, Suman, Since almost one month pending with this patch series, just a gentle ping that would you have further suggestions on this series? We are looking for this series being merged soon. Thanks On Wed, 2020-10-14 at 21:30 +0800, Crystal Guo wrote: > Hi Maintainers, > > Gentle ping for this patch set. > > Many thanks > Crystal > > On Wed, 2020-09-30 at 10:21 +0800, Crystal Guo wrote: > > Add a YAML documentation for Mediatek, which uses ti reset-controller > > driver directly. The TI reset controller provides a common reset > > management, and is suitable for Mediatek SoCs. > > > > Signed-off-by: Crystal Guo > > --- > > .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++ > > 1 file changed, 51 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml > > > > diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml > > new file mode 100644 > > index 000000000000..7871550c3c69 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml > > @@ -0,0 +1,51 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Mediatek Reset Controller > > + > > +maintainers: > > + - Crystal Guo > > + > > +description: > > + The bindings describe the reset-controller for Mediatek SoCs, > > + which is based on TI reset controller. For more detail, please > > + visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. > > + > > +properties: > > + compatible: > > + const: mediatek,syscon-reset > > + > > + '#reset-cells': > > + const: 1 > > + > > + mediatek,reset-bits: > > + description: > > > + Contains the reset control register information, please refer to > > + Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. > > + > > +required: > > + - compatible > > + - '#reset-cells' > > + - mediatek,reset-bits > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + infracfg: infracfg@10001000 { > > + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; > > + reg = <0 0x10001000>; > > + #clock-cells = <1>; > > + > > + infracfg_rst: reset-controller { > > + compatible = "mediatek,syscon-reset"; > > + #reset-cells = <1>; > > + mediatek,reset-bits = < > > + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) > > + >; > > + }; > > + }; > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek