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From: <chuanjia.liu@mediatek.com>
To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
	srv_heupstream@mediatek.com,
	"chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org,
	yong.wu@mediatek.com, bhelgaas@google.com,
	linux-arm-kernel@lists.infradead.org,
	amurray@thegoodpenguin.co.uk
Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node
Date: Thu, 28 May 2020 14:16:48 +0800	[thread overview]
Message-ID: <20200528061648.32078-5-chuanjia.liu@mediatek.com> (raw)
In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com>

From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>

Remove unused property and add pciecfg node.

Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
---
 arch/arm/boot/dts/mt7629-rfb.dts |  3 ++-
 arch/arm/boot/dts/mt7629.dtsi    | 23 +++++++++++++----------
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts
index 9980c10c6e29..eb536cbebd9b 100644
--- a/arch/arm/boot/dts/mt7629-rfb.dts
+++ b/arch/arm/boot/dts/mt7629-rfb.dts
@@ -140,9 +140,10 @@
 	};
 };
 
-&pcie {
+&pcie1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_pins>;
+	status = "okay";
 };
 
 &pciephy1 {
diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
index 5cbb3d244c75..94567307b842 100644
--- a/arch/arm/boot/dts/mt7629.dtsi
+++ b/arch/arm/boot/dts/mt7629.dtsi
@@ -360,16 +360,21 @@
 			#reset-cells = <1>;
 		};
 
-		pcie: pcie@1a140000 {
+		pciecfg: pciecfg@1a140000 {
+			compatible = "mediatek,mt7629-pciecfg", "syscon";
+			reg = <0x1a140000 0x1000>;
+		};
+
+		pcie1: pcie@1a145000 {
 			compatible = "mediatek,mt7629-pcie";
 			device_type = "pci";
-			reg = <0x1a140000 0x1000>,
-			      <0x1a145000 0x1000>;
-			reg-names = "subsys","port1";
+			reg = <0x1a145000 0x1000>;
+			reg-names = "port1";
+			mediatek,pcie-cfg = <&pciecfg>;
 			#address-cells = <3>;
 			#size-cells = <2>;
-			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
-				     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+			interrupt-names = "pcie_irq";
 			clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
 				 <&pciesys CLK_PCIE_P0_AHB_EN>,
 				 <&pciesys CLK_PCIE_P1_AUX_EN>,
@@ -390,21 +395,19 @@
 			power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 			bus-range = <0x00 0xff>;
 			ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
+			status = "disabled";
 
-			pcie1: pcie@1,0 {
-				device_type = "pci";
+			slot1: pcie@1,0 {
 				reg = <0x0800 0 0 0 0>;
 				#address-cells = <3>;
 				#size-cells = <2>;
 				#interrupt-cells = <1>;
 				ranges;
-				num-lanes = <1>;
 				interrupt-map-mask = <0 0 0 7>;
 				interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 						<0 0 0 2 &pcie_intc1 1>,
 						<0 0 0 3 &pcie_intc1 2>,
 						<0 0 0 4 &pcie_intc1 3>;
-
 				pcie_intc1: interrupt-controller {
 					interrupt-controller;
 					#address-cells = <0>;
-- 
2.18.0
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  parent reply	other threads:[~2020-05-28  6:29 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-28  6:16 [PATCH v2 0/4] Spilt PCIe node to comply with hardware design chuanjia.liu
2020-05-28  6:16 ` [PATCH v2 1/4] dt-bindings: PCI: Mediatek: Update PCIe binding chuanjia.liu
2020-05-28  6:16 ` [PATCH v2 2/4] PCI: mediatek: Use regmap to get shared pcie-cfg base chuanjia.liu
2020-05-28  6:16 ` [PATCH v2 3/4] arm64: dts: mediatek: Split PCIe node for MT2712/MT7622 chuanjia.liu
2020-05-28  6:16 ` chuanjia.liu [this message]
2020-05-29  3:05 ` [PATCH v2 0/4] Spilt PCIe node to comply with hardware design Ryder Lee

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