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From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	"Matthias Brugger" <matthias.bgg@gmail.com>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
	wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
	Evan Green <evgreen@chromium.org>,
	Chao Hao <chao.hao@mediatek.com>,
	iommu@lists.linux-foundation.org,
	linux-mediatek@lists.infradead.org,
	Yong Wu <yong.wu@mediatek.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data
Date: Mon, 29 Jun 2020 15:13:05 +0800
Message-ID: <20200629071310.1557-6-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200629071310.1557-1-chao.hao@mediatek.com>

For mt6779, MMU_INV_SEL register's offset is changed from
0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to
use it.
In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it
before mt6779.

Cc: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
---
 drivers/iommu/mtk_iommu.c | 9 ++++++---
 drivers/iommu/mtk_iommu.h | 1 +
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 67b46b5d83d9..116418cc1cf8 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -37,7 +37,7 @@
 #define REG_MMU_INVLD_START_A			0x024
 #define REG_MMU_INVLD_END_A			0x028
 
-#define REG_MMU_INV_SEL				0x038
+#define REG_MMU_INV_SEL_GEN1			0x038
 #define F_INVLD_EN0				BIT(0)
 #define F_INVLD_EN1				BIT(1)
 
@@ -168,7 +168,7 @@ static void mtk_iommu_tlb_flush_all(void *cookie)
 
 	for_each_m4u(data) {
 		writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
-			       data->base + REG_MMU_INV_SEL);
+			       data->base + data->plat_data->inv_sel_reg);
 		writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
 		wmb(); /* Make sure the tlb flush all done */
 	}
@@ -185,7 +185,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
 	for_each_m4u(data) {
 		spin_lock_irqsave(&data->tlb_lock, flags);
 		writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
-			       data->base + REG_MMU_INV_SEL);
+			       data->base + data->plat_data->inv_sel_reg);
 
 		writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
 		writel_relaxed(iova + size - 1,
@@ -777,6 +777,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
 	.flags        = HAS_4GB_MODE |
 			HAS_BCLK |
 			HAS_VLD_PA_RNG,
+	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
 	.larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
 };
 
@@ -785,12 +786,14 @@ static const struct mtk_iommu_plat_data mt8173_data = {
 	.flags	      = HAS_4GB_MODE |
 			HAS_BCLK |
 			RESET_AXI,
+	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
 	.larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
 };
 
 static const struct mtk_iommu_plat_data mt8183_data = {
 	.m4u_plat     = M4U_MT8183,
 	.flags        = RESET_AXI,
+	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
 	.larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
 };
 
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 4b780b651ef4..ae70296af2b4 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -47,6 +47,7 @@ enum mtk_iommu_plat {
 struct mtk_iommu_plat_data {
 	enum mtk_iommu_plat m4u_plat;
 	u32                 flags;
+	u32                 inv_sel_reg;
 	unsigned char       larbid_remap[MTK_LARB_NR_MAX];
 };
 
-- 
2.18.0
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  parent reply index

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-29  7:13 [PATCH v5 00/10] MT6779 IOMMU SUPPORT Chao Hao
2020-06-29  7:13 ` [PATCH v5 01/10] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-06-29  7:13 ` [PATCH v5 02/10] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL Chao Hao
2020-07-01  2:17   ` Yong Wu
2020-07-03  2:36     ` chao hao
2020-06-29  7:13 ` [PATCH v5 03/10] iommu/mediatek: Modify the usage of mtk_iommu_plat_data structure Chao Hao
2020-06-29  9:11   ` Matthias Brugger
2020-06-30 10:56   ` Yong Wu
2020-06-30 11:55     ` chao hao
2020-06-29  7:13 ` [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register Chao Hao
2020-06-29  9:28   ` Matthias Brugger
2020-06-30 10:53     ` chao hao
2020-07-01 14:58       ` Matthias Brugger
2020-07-03  2:38         ` chao hao
2020-06-29  7:13 ` Chao Hao [this message]
2020-06-29  7:13 ` [PATCH v5 06/10] iommu/mediatek: Add sub_comm id in translation fault Chao Hao
2020-06-30 10:55   ` Yong Wu
2020-06-30 11:07     ` chao hao
2020-06-29  7:13 ` [PATCH v5 07/10] iommu/mediatek: Add REG_MMU_WR_LEN register definition Chao Hao
2020-06-29 10:16   ` Matthias Brugger
2020-06-30 10:59     ` chao hao
2020-07-01 15:00       ` Matthias Brugger
2020-06-29  7:13 ` [PATCH v5 08/10] iommu/mediatek: Extend protect pa alignment value Chao Hao
2020-06-29 10:17   ` Matthias Brugger
2020-06-29  7:13 ` [PATCH v5 09/10] iommu/mediatek: Modify MMU_CTRL register setting Chao Hao
2020-06-29 10:28   ` Matthias Brugger
2020-06-30 11:02     ` chao hao
2020-06-29  7:13 ` [PATCH v5 10/10] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-06-29 10:29   ` Matthias Brugger

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