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From: Zhiyong Tao <zhiyong.tao@mediatek.com>
To: <robh+dt@kernel.org>, <linus.walleij@linaro.org>,
	<mark.rutland@arm.com>,  <matthias.bgg@gmail.com>,
	<sean.wang@kernel.org>
Cc: devicetree@vger.kernel.org, sean.wang@mediatek.com,
	srv_heupstream@mediatek.com, chuanjia.liu@mediatek.com,
	biao.huang@mediatek.com, zhiyong.tao@mediatek.com,
	erin.lo@mediatek.com, hui.liu@mediatek.com,
	seiya.wang@mediatek.com, linux-kernel@vger.kernel.org,
	hongzhou.yang@mediatek.com, sj.huang@mediatek.com,
	linux-mediatek@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
	eddie.huang@mediatek.com, jg_poxu@mediatek.com
Subject: [PATCH v2 2/3] dt-bindings: pinctrl: mt8192: add binding document
Date: Sat, 1 Aug 2020 12:33:02 +0800
Message-ID: <20200801043303.32149-3-zhiyong.tao@mediatek.com> (raw)
In-Reply-To: <20200801043303.32149-1-zhiyong.tao@mediatek.com>

The commit adds mt8192 compatible node in binding document.

Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
---
 .../bindings/pinctrl/pinctrl-mt8192.yaml      | 175 ++++++++++++++++++
 1 file changed, 175 insertions(+)
 create mode 100755 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml
new file mode 100755
index 000000000000..88e18e2e23a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml
@@ -0,0 +1,175 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT8192 Pin Controller
+
+maintainers:
+  - Sean Wang <sean.wang@mediatek.com>
+
+description: |
+  The Mediatek's Pin controller is used to control SoC pins.
+
+properties:
+  compatible:
+    const: mediatek,mt8192-pinctrl
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    description: |
+      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
+      the amount of cells must be specified as 2. See the below
+      mentioned gpio binding representation for description of particular cells.
+    const: 2
+
+  gpio-ranges:
+    description: gpio valid number range.
+    maxItems: 1
+
+  reg:
+    description: |
+      Physical address base for gpio base registers. There are 11 GPIO
+      physical address base in mt8192.
+    maxItems: 11
+
+  reg-names:
+    description: |
+      Gpio base register names.
+    maxItems: 11
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+  interrupts:
+    description: The interrupt outputs to sysirq.
+    maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+  '^pins':
+    type: object
+    description: |
+      A pinctrl node should contain at least one subnodes representing the
+      pinctrl groups available on the machine. Each subnode will list the
+      pins it needs, and how they should be configured, with regard to muxer
+      configuration, pullups, drive strength, input enable/disable and
+      input schmitt.
+      An example of using macro:
+      node {
+        pinmux = <PIN_NUMBER_PINMUX>;
+        GENERIC_PINCONFIG;
+      };
+    properties:
+      pinmux:
+        $ref: "/schemas/types.yaml#/definitions/uint32-array"
+        description: |
+          Integer array, represents gpio pin number and mux setting.
+          Supported pin number and mux varies for different SoCs, and are defined
+          as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
+
+      GENERIC_PINCONFIG:
+        description: |
+          It is the generic pinconfig options to use, bias-disable,
+          bias-pull-down, bias-pull-up, input-enable, input-disable, output-low,
+          output-high, input-schmitt-enable, input-schmitt-disable
+          and drive-strength are valid.
+
+          Some special pins have extra pull up strength, there are R0 and R1 pull-up
+          resistors available, but for user, it's only need to set R1R0 as 00, 01,
+          10 or 11. So It needs config "mediatek,pull-up-adv" or
+          "mediatek,pull-down-adv" to support arguments for those special pins.
+          Valid arguments are from 0 to 3.
+
+          We can use "mediatek,tdsel" which is an integer describing the steps for
+          output level shifter duty cycle when asserted (high pulse width adjustment).
+          Valid arguments  are from 0 to 15.
+          We can use "mediatek,rdsel" which is an integer describing the steps for
+          input level shifter duty cycle when asserted (high pulse width adjustment).
+          Valid arguments are from 0 to 63.
+
+          When config drive-strength, it can support some arguments, such as
+          MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
+          It can only support 2/4/6/8/10/12/14/16mA in mt8192.
+          For I2C pins, there are existing generic driving setup and the specific
+          driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving
+          adjustment in generic driving setup. But in specific driving setup,
+          they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
+          driving setup for I2C pins, the existing generic driving setup will be
+          disabled. For some special features, we need the I2C pins specific
+          driving setup. The specific driving setup is controlled by E1E0EN.
+          So we need add extra vendor driving preperty instead of
+          the generic driving property.
+          We can add "mediatek,drive-strength-adv = <XXX>;" to describe the specific
+          driving setup property. "XXX" means the value of E1E0EN. EN is 0 or 1.
+          It is used to enable or disable the specific driving setup.
+          E1E0 is used to describe the detail strength specification of the I2C pin.
+          When E1=0/E0=0, the strength is 0.125mA.
+          When E1=0/E0=1, the strength is 0.25mA.
+          When E1=1/E0=0, the strength is 0.5mA.
+          When E1=1/E0=1, the strength is 1mA.
+          So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7.
+
+      bias-pull-down: true
+
+      bias-pull-up: true
+
+      bias-disable: true
+
+      output-high: true
+
+      output-low: true
+
+      input-enable: true
+
+      input-disable: true
+
+      input-schmitt-enable: true
+
+      input-schmitt-disable: true
+
+    required:
+      - pinmux
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-controller
+  - '#interrupt-cells'
+  - gpio-controller
+  - '#gpio-cells'
+  - gpio-ranges
+
+examples:
+  - |
+            #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+            #include <dt-bindings/interrupt-controller/arm-gic.h>
+            pio: pinctrl@10005000 {
+                    compatible = "mediatek,mt8192-pinctrl";
+                    reg = <0 0x10005000 0 0x1000>,
+                          <0 0x11c20000 0 0x1000>,
+                          <0 0x11d10000 0 0x1000>,
+                          <0 0x11d30000 0 0x1000>,
+                          <0 0x11d40000 0 0x1000>,
+                          <0 0x11e20000 0 0x1000>,
+                          <0 0x11e70000 0 0x1000>,
+                          <0 0x11ea0000 0 0x1000>,
+                          <0 0x11f20000 0 0x1000>,
+                          <0 0x11f30000 0 0x1000>,
+                          <0 0x1000b000 0 0x1000>;
+                    reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
+                          "iocfg_bl", "iocfg_br", "iocfg_lm",
+                          "iocfg_lb", "iocfg_rt", "iocfg_lt",
+                          "iocfg_tl", "eint";
+                    gpio-controller;
+                    #gpio-cells = <2>;
+                    gpio-ranges = <&pio 0 0 220>;
+                    interrupt-controller;
+                    interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
+                    #interrupt-cells = <2>;
+            };
-- 
2.18.0
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  parent reply index

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-01  4:33 [PATCH v2 0/3] Mediatek pinctrl patch on mt8192 Zhiyong Tao
2020-08-01  4:33 ` [PATCH v2 1/3] dt-bindings: pinctrl: mt8192: add pinctrl file Zhiyong Tao
2020-08-01  4:33 ` Zhiyong Tao [this message]
2020-08-03 21:40   ` [PATCH v2 2/3] dt-bindings: pinctrl: mt8192: add binding document Rob Herring
2020-08-04  0:14     ` zhiyong tao
2020-08-03 21:46   ` Rob Herring
2020-08-04  2:09     ` zhiyong tao
2020-08-01  4:33 ` [PATCH v2 3/3] pinctrl: add pinctrl driver on mt8192 Zhiyong Tao

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