From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
To: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org, drinkcat@chromium.org,
weiyi.lu@mediatek.com, fparent@baylibre.com,
Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org, hsinyi@chromium.org,
matthias.bgg@gmail.com,
Collabora Kernel ML <kernel@collabora.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 03/12] arm64: dts: mediatek: Add mt8173 power domain controller
Date: Thu, 10 Sep 2020 19:28:17 +0200 [thread overview]
Message-ID: <20200910172826.3074357-4-enric.balletbo@collabora.com> (raw)
In-Reply-To: <20200910172826.3074357-1-enric.balletbo@collabora.com>
Add power domain controller node for SoC mt8173.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 78 +++++++++++++++++++++---
1 file changed, 69 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 5e046f9d48ce..3b08c5404d81 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -450,16 +450,76 @@ pins1 {
};
};
- scpsys: power-controller@10006000 {
- compatible = "mediatek,mt8173-scpsys";
- #power-domain-cells = <1>;
+ scpsys: syscon@10006000 {
+ compatible = "mediatek,mt8173-power-controller";
reg = <0 0x10006000 0 0x1000>;
- clocks = <&clk26m>,
- <&topckgen CLK_TOP_MM_SEL>,
- <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- clock-names = "mfg", "mm", "venc", "venc_lt";
- infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* power domains of the SoC */
+ vdec@MT8173_POWER_DOMAIN_VDEC {
+ reg = <MT8173_POWER_DOMAIN_VDEC>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ };
+
+ venc@MT8173_POWER_DOMAIN_VENC {
+ reg = <MT8173_POWER_DOMAIN_VENC>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_VENC_SEL>;
+ clock-names = "mm", "venc";
+ #power-domain-cells = <0>;
+ };
+ isp@MT8173_POWER_DOMAIN_ISP {
+ reg = <MT8173_POWER_DOMAIN_ISP>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ };
+ mm@MT8173_POWER_DOMAIN_MM {
+ reg = <MT8173_POWER_DOMAIN_MM>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+ venc_lt@MT8173_POWER_DOMAIN_VENC_LT {
+ reg = <MT8173_POWER_DOMAIN_VENC_LT>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "mm", "venclt";
+ #power-domain-cells = <0>;
+ };
+ audio@MT8173_POWER_DOMAIN_AUDIO {
+ reg = <MT8173_POWER_DOMAIN_AUDIO>;
+ #power-domain-cells = <0>;
+ };
+ usb@MT8173_POWER_DOMAIN_USB {
+ reg = <MT8173_POWER_DOMAIN_USB>;
+ #power-domain-cells = <0>;
+ };
+ mfg_async@MT8173_POWER_DOMAIN_MFG_ASYNC {
+ reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
+ clocks = <&clk26m>;
+ clock-names = "mfg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ mfg_2d@MT8173_POWER_DOMAIN_MFG_2D {
+ reg = <MT8173_POWER_DOMAIN_MFG_2D>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ mfg@MT8173_POWER_DOMAIN_MFG {
+ reg = <MT8173_POWER_DOMAIN_MFG>;
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+ };
+ };
};
watchdog: watchdog@10007000 {
--
2.28.0
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next prev parent reply other threads:[~2020-09-10 17:29 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-10 17:28 [PATCH 00/12] soc: mediatek: pm-domains: Add new driver for SCPSYS power domains controller Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 01/12] dt-bindings: power: Add bindings for the Mediatek " Enric Balletbo i Serra
2020-09-11 23:02 ` Rob Herring
2020-09-14 8:59 ` Matthias Brugger
2020-09-14 9:49 ` Enric Balletbo i Serra
2020-09-22 22:36 ` Rob Herring
2020-09-23 16:12 ` Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 02/12] soc: mediatek: Add MediaTek SCPSYS power domains Enric Balletbo i Serra
2020-09-25 10:25 ` Weiyi Lu
2020-09-25 10:43 ` Matthias Brugger
2020-09-10 17:28 ` Enric Balletbo i Serra [this message]
2020-09-18 20:20 ` [PATCH 03/12] arm64: dts: mediatek: Add mt8173 power domain controller Fabien Parent
2020-09-18 20:50 ` Enric Balletbo Serra
2020-09-10 17:28 ` [PATCH 04/12] soc: mediatek: pm-domains: Add bus protection protocol Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 05/12] soc: mediatek: pm_domains: Make bus protection generic Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 06/12] soc: mediatek: pm-domains: Add SMI block as bus protection block Enric Balletbo i Serra
2020-09-25 10:45 ` Weiyi Lu
2020-09-25 11:01 ` Matthias Brugger
2020-09-10 17:28 ` [PATCH 07/12] soc: mediatek: pm-domains: Add extra sram control Enric Balletbo i Serra
2020-09-10 18:27 ` Matthias Brugger
2020-10-26 15:16 ` Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 08/12] soc: mediatek: pm-domains: Add subsystem clocks Enric Balletbo i Serra
2020-09-25 10:55 ` Weiyi Lu
2020-09-25 12:20 ` Matthias Brugger
2020-09-10 17:28 ` [PATCH 09/12] soc: mediatek: pm-domains: Allow bus protection to ignore clear ack Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 10/12] dt-bindings: power: Add MT8183 power domains Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 11/12] soc: mediatek: pm-domains: Add support for mt8183 Enric Balletbo i Serra
2020-09-16 9:46 ` Matthias Brugger
2020-09-16 12:19 ` Matthias Brugger
2020-09-25 7:37 ` Hsin-Yi Wang
2020-09-25 8:21 ` Enric Balletbo i Serra
2020-09-25 9:07 ` Matthias Brugger
2020-09-10 17:28 ` [PATCH 12/12] arm64: dts: mediatek: Add mt8183 power domains controller Enric Balletbo i Serra
2020-09-25 10:06 ` [PATCH 00/12] soc: mediatek: pm-domains: Add new driver for SCPSYS " Weiyi Lu
2020-09-25 14:04 ` Matthias Brugger
2020-10-06 6:53 ` Weiyi Lu
2020-10-09 12:50 ` Matthias Brugger
2020-10-09 13:57 ` Enric Balletbo i Serra
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