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Fri, 11 Sep 2020 16:02:57 -0700 (PDT) Received: from xps15 ([64.188.179.251]) by smtp.gmail.com with ESMTPSA id q23sm1864341iob.19.2020.09.11.16.02.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2020 16:02:56 -0700 (PDT) Received: (nullmailer pid 2983166 invoked by uid 1000); Fri, 11 Sep 2020 23:02:55 -0000 Date: Fri, 11 Sep 2020 17:02:55 -0600 From: Rob Herring To: Enric Balletbo i Serra Subject: Re: [PATCH 01/12] dt-bindings: power: Add bindings for the Mediatek SCPSYS power domains controller Message-ID: <20200911230255.GA2972120@bogus> References: <20200910172826.3074357-1-enric.balletbo@collabora.com> <20200910172826.3074357-2-enric.balletbo@collabora.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200910172826.3074357-2-enric.balletbo@collabora.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200911_190259_193484_8B1701EB X-CRM114-Status: GOOD ( 30.89 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, drinkcat@chromium.org, weiyi.lu@mediatek.com, linux-kernel@vger.kernel.org, fparent@baylibre.com, Matthias Brugger , linux-mediatek@lists.infradead.org, hsinyi@chromium.org, matthias.bgg@gmail.com, Collabora Kernel ML , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, Sep 10, 2020 at 07:28:15PM +0200, Enric Balletbo i Serra wrote: > The System Control Processor System (SCPSYS) has several power management > related tasks in the system. Add the bindings to define the power > domains for the SCPSYS power controller. > > Co-developed-by: Matthias Brugger > Signed-off-by: Matthias Brugger > Signed-off-by: Enric Balletbo i Serra > --- > Dear Rob, > > I am awasre that this binding is not ready, but I prefered to send because I'm > kind of blocked. Compiling this binding triggers the following error: > > mediatek,power-controller.example.dt.yaml: syscon@10006000: mfg_async@7: > '#address-cells', '#size-cells', 'mfg_2d@8' > do not match any of the regexes: 'pinctrl-[0-9]+' > > This happens when a definition of a power-domain (parent) contains > another power-domain (child), like the example. I am not sure how to > specify this in the yaml and deal with this, so any clue is welcome. You just have to keep nesting schemas all the way down. Define a grandchild node under the child node and then all of its properties. > > Thanks, > Enric > > .../power/mediatek,power-controller.yaml | 171 ++++++++++++++++++ > 1 file changed, 171 insertions(+) > create mode 100644 Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > > diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > new file mode 100644 > index 000000000000..8be9244ad160 > --- /dev/null > +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > @@ -0,0 +1,171 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek Power Domains Controller > + > +maintainers: > + - Weiyi Lu > + - Matthias Brugger > + > +description: | > + Mediatek processors include support for multiple power domains which can be > + powered up/down by software based on different application scenes to save power. > + > + IP cores belonging to a power domain should contain a 'power-domains' > + property that is a phandle for SCPSYS node representing the domain. > + > +properties: > + $nodename: > + pattern: "^syscon@[0-9a-f]+$" > + > + compatible: > + items: > + - enum: > + - mediatek,mt8173-power-controller > + - const: syscon > + > + reg: > + maxItems: 1 > + > +patternProperties: > + "^.*@[0-9]$": Node names should be generic: power-domain@ > + type: object > + description: | > + Represents the power domains within the power controller node as documented > + in Documentation/devicetree/bindings/power/power-domain.yaml. > + > + properties: > + reg: > + description: | > + Power domain index. Valid values are defined in: > + "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. > + maxItems: 1 > + > + '#power-domain-cells': > + description: > + Documented by the generic PM Domain bindings in > + Documentation/devicetree/bindings/power/power-domain.yaml. No need to redefine a common property. This should define valid values for it. > + > + clocks: > + description: | > + A number of phandles to clocks that need to be enabled during domain > + power-up sequencing. No need to redefine 'clocks'. You need to define how many, what each one is, and the order. > + > + clock-names: > + description: | > + List of names of clocks, in order to match the power-up sequencing > + for each power domain we need to group the clocks by name. BASIC > + clocks need to be enabled before enabling the corresponding power > + domain, and should not have a '-' in their name (i.e mm, mfg, venc). > + SUSBYS clocks need to be enabled before releasing the bus protection, > + and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). > + > + In order to follow properly the power-up sequencing, the clocks must > + be specified by order, adding first the BASIC clocks followed by the > + SUSBSYS clocks. You need to define the names. > + > + mediatek,infracfg: > + $ref: /schemas/types.yaml#definitions/phandle > + description: phandle to the device containing the INFRACFG register range. > + > + mediatek,smi: > + $ref: /schemas/types.yaml#definitions/phandle > + description: phandle to the device containing the SMI register range. > + > + required: > + - reg > + - '#power-domain-cells' > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + scpsys: syscon@10006000 { > + compatible = "mediatek,mt8173-power-controller", "syscon"; > + reg = <0 0x10006000 0 0x1000>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* power domains of the SoC */ > + vdec@MT8173_POWER_DOMAIN_VDEC { > + reg = ; > + clocks = <&topckgen CLK_TOP_MM_SEL>; > + clock-names = "mm"; > + #power-domain-cells = <0>; > + }; > + > + venc@MT8173_POWER_DOMAIN_VENC { > + reg = ; > + clocks = <&topckgen CLK_TOP_MM_SEL>, > + <&topckgen CLK_TOP_VENC_SEL>; > + clock-names = "mm", "venc"; > + #power-domain-cells = <0>; > + }; > + isp@MT8173_POWER_DOMAIN_ISP { > + reg = ; > + clocks = <&topckgen CLK_TOP_MM_SEL>; > + clock-names = "mm"; > + #power-domain-cells = <0>; > + }; > + mm@MT8173_POWER_DOMAIN_MM { > + reg = ; > + clocks = <&topckgen CLK_TOP_MM_SEL>; > + clock-names = "mm"; > + #power-domain-cells = <0>; > + mediatek,infracfg = <&infracfg>; > + }; > + venc_lt@MT8173_POWER_DOMAIN_VENC_LT { > + reg = ; > + clocks = <&topckgen CLK_TOP_MM_SEL>, > + <&topckgen CLK_TOP_VENC_LT_SEL>; > + clock-names = "mm", "venclt"; > + #power-domain-cells = <0>; > + }; > + audio@MT8173_POWER_DOMAIN_AUDIO { > + reg = ; > + #power-domain-cells = <0>; > + }; > + usb@MT8173_POWER_DOMAIN_USB { > + reg = ; > + #power-domain-cells = <0>; > + }; > + mfg_async@MT8173_POWER_DOMAIN_MFG_ASYNC { > + reg = ; > + clocks = <&clk26m>; > + clock-names = "mfg"; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + mfg_2d@MT8173_POWER_DOMAIN_MFG_2D { > + reg = ; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + mfg@MT8173_POWER_DOMAIN_MFG { > + reg = ; > + #power-domain-cells = <0>; > + mediatek,infracfg = <&infracfg>; > + }; > + }; > + }; > + }; > + }; > -- > 2.28.0 > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek