From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
To: linux-kernel@vger.kernel.org
Cc: drinkcat@chromium.org, weiyi.lu@mediatek.com,
fparent@baylibre.com, Matthias Brugger <mbrugger@suse.com>,
linux-mediatek@lists.infradead.org, hsinyi@chromium.org,
matthias.bgg@gmail.com,
Collabora Kernel ML <kernel@collabora.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 07/12] soc: mediatek: pm-domains: Add extra sram control
Date: Thu, 1 Oct 2020 18:01:49 +0200 [thread overview]
Message-ID: <20201001160154.3587848-8-enric.balletbo@collabora.com> (raw)
In-Reply-To: <20201001160154.3587848-1-enric.balletbo@collabora.com>
From: Matthias Brugger <mbrugger@suse.com>
For some power domains like vpu_core on MT8183 whose sram need to do clock
and internal isolation while power on/off sram. We add a cap
"MTK_SCPD_SRAM_ISO" to judge if we need to do the extra sram isolation
control or not.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
Changes in v2:
- Nit, split readl(ctl_addr) | pd->data->sram_pdn_bits in two lines.
- Use regmap API
drivers/soc/mediatek/mtk-pm-domains.c | 30 +++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 38f2630bdd0a..e0a52d489fea 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -21,6 +21,7 @@
#define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
#define MTK_SCPD_FWAIT_SRAM BIT(1)
+#define MTK_SCPD_SRAM_ISO BIT(2)
#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
#define SPM_VDE_PWR_CON 0x0210
@@ -42,6 +43,8 @@
#define PWR_ON_BIT BIT(2)
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BIT BIT(4)
+#define PWR_SRAM_CLKISO_BIT BIT(5)
+#define PWR_SRAM_ISOINT_B_BIT BIT(6)
#define PWR_STATUS_DISP BIT(3)
#define PWR_STATUS_MFG BIT(4)
@@ -155,14 +158,28 @@ static int scpsys_sram_enable(struct scpsys_domain *pd)
struct scpsys *scpsys = pd->scpsys;
u32 val;
int tmp;
+ int ret;
regmap_read(scpsys->base, pd->data->ctl_offs, &val);
val &= ~pd->data->sram_pdn_bits;
regmap_write(scpsys->base, pd->data->ctl_offs, val);
/* Either wait until SRAM_PDN_ACK all 1 or 0 */
- return regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp,
- (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ ret = regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp,
+ (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ if (ret < 0)
+ return ret;
+
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) {
+ regmap_read(scpsys->base, pd->data->ctl_offs, &val);
+ val |= PWR_SRAM_ISOINT_B_BIT;
+ regmap_write(scpsys->base, pd->data->ctl_offs, val);
+ udelay(1);
+ val &= ~PWR_SRAM_CLKISO_BIT;
+ regmap_write(scpsys->base, pd->data->ctl_offs, val);
+ }
+
+ return 0;
}
static int scpsys_sram_disable(struct scpsys_domain *pd)
@@ -172,6 +189,15 @@ static int scpsys_sram_disable(struct scpsys_domain *pd)
u32 val;
int tmp;
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) {
+ regmap_read(scpsys->base, pd->data->ctl_offs, &val);
+ val |= PWR_SRAM_CLKISO_BIT;
+ regmap_write(scpsys->base, pd->data->ctl_offs, val);
+ val &= ~PWR_SRAM_ISOINT_B_BIT;
+ regmap_write(scpsys->base, pd->data->ctl_offs, val);
+ udelay(1);
+ }
+
regmap_read(scpsys->base, pd->data->ctl_offs, &val);
val |= pd->data->sram_pdn_bits;
regmap_write(scpsys->base, pd->data->ctl_offs, val);
--
2.28.0
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next prev parent reply other threads:[~2020-10-01 16:03 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-01 16:01 [PATCH v2 00/12] soc: mediatek: pm-domains: Add new driver for SCPSYS power domains controller Enric Balletbo i Serra
2020-10-01 16:01 ` [PATCH v2 01/12] dt-bindings: power: Add bindings for the Mediatek " Enric Balletbo i Serra
2020-10-01 16:01 ` [PATCH v2 02/12] soc: mediatek: Add MediaTek SCPSYS power domains Enric Balletbo i Serra
2020-10-05 1:39 ` Nicolas Boichat
2020-10-26 15:17 ` Enric Balletbo i Serra
2020-10-27 0:19 ` Nicolas Boichat
2020-10-27 16:25 ` Enric Balletbo i Serra
2020-10-28 1:13 ` Nicolas Boichat
2020-10-30 10:29 ` Enric Balletbo i Serra
2020-10-30 12:44 ` Nicolas Boichat
2020-10-01 16:01 ` [PATCH v2 03/12] arm64: dts: mediatek: Add mt8173 power domain controller Enric Balletbo i Serra
2020-10-01 16:01 ` [PATCH v2 04/12] soc: mediatek: pm-domains: Add bus protection protocol Enric Balletbo i Serra
2020-10-01 16:01 ` [PATCH v2 05/12] soc: mediatek: pm_domains: Make bus protection generic Enric Balletbo i Serra
2020-10-01 16:01 ` [PATCH v2 06/12] soc: mediatek: pm-domains: Add SMI block as bus protection block Enric Balletbo i Serra
2020-10-02 8:56 ` Matthias Brugger
2020-10-05 1:48 ` Nicolas Boichat
2020-10-05 10:28 ` Matthias Brugger
2020-10-26 15:18 ` Enric Balletbo i Serra
2020-10-26 15:18 ` Enric Balletbo i Serra
2020-10-01 16:01 ` Enric Balletbo i Serra [this message]
2020-10-02 9:24 ` [PATCH v2 07/12] soc: mediatek: pm-domains: Add extra sram control Matthias Brugger
2020-10-01 16:01 ` [PATCH v2 08/12] soc: mediatek: pm-domains: Add subsystem clocks Enric Balletbo i Serra
2020-10-02 9:04 ` Matthias Brugger
2020-10-26 15:17 ` Enric Balletbo i Serra
2020-10-01 16:01 ` [PATCH v2 09/12] soc: mediatek: pm-domains: Allow bus protection to ignore clear ack Enric Balletbo i Serra
2020-10-01 16:01 ` [PATCH v2 10/12] dt-bindings: power: Add MT8183 power domains Enric Balletbo i Serra
2020-10-01 16:01 ` [PATCH v2 11/12] soc: mediatek: pm-domains: Add support for mt8183 Enric Balletbo i Serra
2020-10-01 16:01 ` [PATCH v2 12/12] arm64: dts: mediatek: Add mt8183 power domains controller Enric Balletbo i Serra
2020-10-02 9:11 ` Matthias Brugger
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