* [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema
@ 2020-10-14 1:44 Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 2/8] dt-bindings: phy: convert phy-mtk-tphy.txt " Chunfeng Yun
` (6 more replies)
0 siblings, 7 replies; 10+ messages in thread
From: Chunfeng Yun @ 2020-10-14 1:44 UTC (permalink / raw)
To: linux-mediatek; +Cc: Chunfeng Yun, srv_heupstream
Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: modify description and compatible definition suggested by Rob
---
.../bindings/phy/mediatek,xsphy.yaml | 200 ++++++++++++++++++
.../devicetree/bindings/phy/phy-mtk-xsphy.txt | 109 ----------
2 files changed, 200 insertions(+), 109 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
new file mode 100644
index 000000000000..86511f19277a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
@@ -0,0 +1,200 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek XS-PHY Controller Device Tree Bindings
+
+maintainers:
+ - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+description: |
+ The XS-PHY controller supports physical layer functionality for USB3.1
+ GEN2 controller on MediaTek SoCs.
+
+ Banks layout of xsphy
+ ----------------------------------
+ port offset bank
+ u2 port0 0x0000 MISC
+ 0x0100 FMREG
+ 0x0300 U2PHY_COM
+ u2 port1 0x1000 MISC
+ 0x1100 FMREG
+ 0x1300 U2PHY_COM
+ u2 port2 0x2000 MISC
+ ...
+ u31 common 0x3000 DIG_GLB
+ 0x3100 PHYA_GLB
+ u31 port0 0x3400 DIG_LN_TOP
+ 0x3500 DIG_LN_TX0
+ 0x3600 DIG_LN_RX0
+ 0x3700 DIG_LN_DAIF
+ 0x3800 PHYA_LN
+ u31 port1 0x3a00 DIG_LN_TOP
+ 0x3b00 DIG_LN_TX0
+ 0x3c00 DIG_LN_RX0
+ 0x3d00 DIG_LN_DAIF
+ 0x3e00 PHYA_LN
+ ...
+ DIG_GLB & PHYA_GLB are shared by U31 ports.
+
+properties:
+ $nodename:
+ pattern: "^xs-phy@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt3611-xsphy
+ - mediatek,mt3612-xsphy
+ - const: mediatek,xsphy
+
+ reg:
+ description: |
+ Register shared by multiple U3 ports, exclude port's private register,
+ if only U2 ports provided, shouldn't use the property.
+ maxItems: 1
+
+ "#address-cells":
+ enum: [1, 2]
+
+ "#size-cells":
+ enum: [1, 2]
+
+ ranges: true
+
+ mediatek,src-ref-clk-mhz:
+ description:
+ Frequency of reference clock for slew rate calibrate
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 26
+
+ mediatek,src-coef:
+ description:
+ Coefficient for slew rate calibrate, depends on SoC process
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 17
+
+# Required child node:
+patternProperties:
+ "^usb-phy@[0-9a-f]+$":
+ type: object
+ description: |
+ A sub-node is required for each port the controller provides.
+ Address range information including the usual 'reg' property
+ is used inside these nodes to describe the controller's topology.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
+
+ clock-names:
+ items:
+ - const: ref
+
+ "#phy-cells":
+ const: 1
+ description: |
+ The cells contain the following arguments.
+
+ - description: The PHY type
+ enum:
+ - PHY_TYPE_USB2
+ - PHY_TYPE_USB3
+
+ #The following optional vendor properties are only for debug or HQA test
+ mediatek,eye-src:
+ description:
+ The value of slew rate calibrate (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,eye-vrt:
+ description:
+ The selection of VRT reference voltage (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,eye-term:
+ description:
+ The selection of HS_TX TERM reference voltage (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,efuse-intr:
+ description:
+ The selection of Internal Resistor (U2/U3 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 63
+
+ mediatek,efuse-tx-imp:
+ description:
+ The selection of TX Impedance (U3 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 31
+
+ mediatek,efuse-rx-imp:
+ description:
+ The selection of RX Impedance (U3 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 31
+
+ required:
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+
+ u3phy: xs-phy@11c40000 {
+ compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
+ reg = <0x11c43000 0x0200>;
+ mediatek,src-ref-clk-mhz = <26>;
+ mediatek,src-coef = <17>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ u2port0: usb-phy@11c40000 {
+ reg = <0x11c40000 0x0400>;
+ clocks = <&clk48m>;
+ clock-names = "ref";
+ mediatek,eye-src = <4>;
+ #phy-cells = <1>;
+ };
+
+ u3port0: usb-phy@11c43000 {
+ reg = <0x11c43400 0x0500>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ mediatek,efuse-intr = <28>;
+ #phy-cells = <1>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
deleted file mode 100644
index e7caefa0b9c2..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
+++ /dev/null
@@ -1,109 +0,0 @@
-MediaTek XS-PHY binding
---------------------------
-
-The XS-PHY controller supports physical layer functionality for USB3.1
-GEN2 controller on MediaTek SoCs.
-
-Required properties (controller (parent) node):
- - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
- soc-model is the name of SoC, such as mt3611 etc;
- when using "mediatek,xsphy" compatible string, you need SoC specific
- ones in addition, one of:
- - "mediatek,mt3611-xsphy"
-
- - #address-cells, #size-cells : should use the same values as the root node
- - ranges: must be present
-
-Optional properties (controller (parent) node):
- - reg : offset and length of register shared by multiple U3 ports,
- exclude port's private register, if only U2 ports provided,
- shouldn't use the property.
- - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
- calibrate
- - mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on
- SoC process
-
-Required nodes : a sub-node is required for each port the controller
- provides. Address range information including the usual
- 'reg' property is used inside these nodes to describe
- the controller's topology.
-
-Required properties (port (child) node):
-- reg : address and length of the register set for the port.
-- clocks : a list of phandle + clock-specifier pairs, one for each
- entry in clock-names
-- clock-names : must contain
- "ref": 48M reference clock for HighSpeed analog phy; and 26M
- reference clock for SuperSpeedPlus analog phy, sometimes is
- 24M, 25M or 27M, depended on platform.
-- #phy-cells : should be 1
- cell after port phandle is phy type from:
- - PHY_TYPE_USB2
- - PHY_TYPE_USB3
-
-The following optional properties are only for debug or HQA test
-Optional properties (PHY_TYPE_USB2 port (child) node):
-- mediatek,eye-src : u32, the value of slew rate calibrate
-- mediatek,eye-vrt : u32, the selection of VRT reference voltage
-- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
-- mediatek,efuse-intr : u32, the selection of Internal Resistor
-
-Optional properties (PHY_TYPE_USB3 port (child) node):
-- mediatek,efuse-intr : u32, the selection of Internal Resistor
-- mediatek,efuse-tx-imp : u32, the selection of TX Impedance
-- mediatek,efuse-rx-imp : u32, the selection of RX Impedance
-
-Banks layout of xsphy
--------------------------------------------------------------
-port offset bank
-u2 port0 0x0000 MISC
- 0x0100 FMREG
- 0x0300 U2PHY_COM
-u2 port1 0x1000 MISC
- 0x1100 FMREG
- 0x1300 U2PHY_COM
-u2 port2 0x2000 MISC
- ...
-u31 common 0x3000 DIG_GLB
- 0x3100 PHYA_GLB
-u31 port0 0x3400 DIG_LN_TOP
- 0x3500 DIG_LN_TX0
- 0x3600 DIG_LN_RX0
- 0x3700 DIG_LN_DAIF
- 0x3800 PHYA_LN
-u31 port1 0x3a00 DIG_LN_TOP
- 0x3b00 DIG_LN_TX0
- 0x3c00 DIG_LN_RX0
- 0x3d00 DIG_LN_DAIF
- 0x3e00 PHYA_LN
- ...
-
-DIG_GLB & PHYA_GLB are shared by U31 ports.
-
-Example:
-
-u3phy: usb-phy@11c40000 {
- compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
- reg = <0 0x11c43000 0 0x0200>;
- mediatek,src-ref-clk-mhz = <26>;
- mediatek,src-coef = <17>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- u2port0: usb-phy@11c40000 {
- reg = <0 0x11c40000 0 0x0400>;
- clocks = <&clk48m>;
- clock-names = "ref";
- mediatek,eye-src = <4>;
- #phy-cells = <1>;
- };
-
- u3port0: usb-phy@11c43000 {
- reg = <0 0x11c43400 0 0x0500>;
- clocks = <&clk26m>;
- clock-names = "ref";
- mediatek,efuse-intr = <28>;
- #phy-cells = <1>;
- };
-};
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 2/8] dt-bindings: phy: convert phy-mtk-tphy.txt to YAML schema
2020-10-14 1:44 [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Chunfeng Yun
@ 2020-10-14 1:44 ` Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 3/8] dt-bindings: phy: convert phy-mtk-ufs.txt " Chunfeng Yun
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Chunfeng Yun @ 2020-10-14 1:44 UTC (permalink / raw)
To: linux-mediatek; +Cc: Chunfeng Yun, srv_heupstream
Convert phy-mtk-tphy.txt to YAML schema mediatek,tphy.yaml
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: modify description and compatible
---
.../bindings/phy/mediatek,tphy.yaml | 263 ++++++++++++++++++
.../devicetree/bindings/phy/phy-mtk-tphy.txt | 162 -----------
2 files changed, 263 insertions(+), 162 deletions(-)
create mode 100755 Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
new file mode 100755
index 000000000000..56ad8be69095
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
@@ -0,0 +1,263 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek T-PHY Controller Device Tree Bindings
+
+maintainers:
+ - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+description: |
+ The T-PHY controller supports physical layer functionality for a number of
+ controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
+
+ Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
+ T-PHY V2 (mt2712) when works on USB mode:
+ -----------------------------------
+ Version 1:
+ port offset bank
+ shared 0x0000 SPLLC
+ 0x0100 FMREG
+ u2 port0 0x0800 U2PHY_COM
+ u3 port0 0x0900 U3PHYD
+ 0x0a00 U3PHYD_BANK2
+ 0x0b00 U3PHYA
+ 0x0c00 U3PHYA_DA
+ u2 port1 0x1000 U2PHY_COM
+ u3 port1 0x1100 U3PHYD
+ 0x1200 U3PHYD_BANK2
+ 0x1300 U3PHYA
+ 0x1400 U3PHYA_DA
+ u2 port2 0x1800 U2PHY_COM
+ ...
+
+ Version 2:
+ port offset bank
+ u2 port0 0x0000 MISC
+ 0x0100 FMREG
+ 0x0300 U2PHY_COM
+ u3 port0 0x0700 SPLLC
+ 0x0800 CHIP
+ 0x0900 U3PHYD
+ 0x0a00 U3PHYD_BANK2
+ 0x0b00 U3PHYA
+ 0x0c00 U3PHYA_DA
+ u2 port1 0x1000 MISC
+ 0x1100 FMREG
+ 0x1300 U2PHY_COM
+ u3 port1 0x1700 SPLLC
+ 0x1800 CHIP
+ 0x1900 U3PHYD
+ 0x1a00 U3PHYD_BANK2
+ 0x1b00 U3PHYA
+ 0x1c00 U3PHYA_DA
+ u2 port2 0x2000 MISC
+ ...
+
+ SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
+ into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
+ added on V2.
+
+properties:
+ $nodename:
+ pattern: "^t-phy@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt2701-tphy
+ - mediatek,mt7623-tphy
+ - mediatek,mt7622-tphy
+ - mediatek,mt8516-tphy
+ - const: mediatek,generic-tphy-v1
+ - items:
+ - enum:
+ - mediatek,mt2712-tphy
+ - mediatek,mt7629-tphy
+ - mediatek,mt8183-tphy
+ - const: mediatek,generic-tphy-v2
+ - const: mediatek,mt2701-u3phy
+ deprecated: true
+ - const: mediatek,mt2712-u3phy
+ deprecated: true
+ - const: mediatek,mt8173-u3phy
+
+ reg:
+ description: |
+ Register shared by multiple ports, exclude port's private register.
+ It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
+ T-PHY V2, such as mt2712.
+ maxItems: 1
+
+ "#address-cells":
+ enum: [1, 2]
+
+ "#size-cells":
+ enum: [1, 2]
+
+ # Used with non-empty value if optional 'reg' is not provided.
+ # The format of the value is an arbitrary number of triplets of
+ # (child-bus-address, parent-bus-address, length).
+ ranges: true
+
+ mediatek,src-ref-clk-mhz:
+ description:
+ Frequency of reference clock for slew rate calibrate
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 26
+
+ mediatek,src-coef:
+ description:
+ Coefficient for slew rate calibrate, depends on SoC process
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 28
+
+# Required child node:
+patternProperties:
+ "^usb-phy@[0-9a-f]+$":
+ type: object
+ description: |
+ A sub-node is required for each port the controller provides.
+ Address range information including the usual 'reg' property
+ is used inside these nodes to describe the controller's topology.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
+ - description: Reference clock of analog phy
+ description: |
+ Uses both clocks if the clock of analog and digital phys are
+ separated, otherwise uses "ref" clock only if needed.
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: ref
+ - const: da_ref
+
+ "#phy-cells":
+ const: 1
+ description: |
+ The cells contain the following arguments.
+
+ - description: The PHY type
+ enum:
+ - PHY_TYPE_USB2
+ - PHY_TYPE_USB3
+ - PHY_TYPE_PCIE
+ - PHY_TYPE_SATA
+
+ #The following optional vendor properties are only for debug or HQA test
+ mediatek,eye-src:
+ description:
+ The value of slew rate calibrate (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,eye-vrt:
+ description:
+ The selection of VRT reference voltage (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,eye-term:
+ description:
+ The selection of HS_TX TERM reference voltage (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+
+ mediatek,intr:
+ description:
+ The selection of internal resistor (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 31
+
+ mediatek,discth:
+ description:
+ The selection of disconnect threshold (U2 phy)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 15
+
+ mediatek,bc12:
+ description:
+ Specify the flag to enable BC1.2 if support it
+ type: boolean
+
+ required:
+ - reg
+ - "#phy-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/phy/phy.h>
+ susb: usb@11271000 {
+ compatible = "mediatek,mt8173-mtu3";
+ reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
+ reg-names = "mac", "ippc";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ u3phy: t-phy@11290000 {
+ compatible = "mediatek,mt8173-u3phy";
+ reg = <0x11290000 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "okay";
+
+ u2port0: usb-phy@11290800 {
+ reg = <0x11290800 0x100>;
+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@11290900 {
+ reg = <0x11290900 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u2port1: usb-phy@11291000 {
+ reg = <0x11291000 0x100>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
deleted file mode 100644
index dd75b676b71d..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
+++ /dev/null
@@ -1,162 +0,0 @@
-MediaTek T-PHY binding
---------------------------
-
-T-phy controller supports physical layer functionality for a number of
-controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
-
-Required properties (controller (parent) node):
- - compatible : should be one of
- "mediatek,generic-tphy-v1"
- "mediatek,generic-tphy-v2"
- "mediatek,mt2701-u3phy" (deprecated)
- "mediatek,mt2712-u3phy" (deprecated)
- "mediatek,mt8173-u3phy";
- make use of "mediatek,generic-tphy-v1" on mt2701 instead and
- "mediatek,generic-tphy-v2" on mt2712 instead.
-
-- #address-cells: the number of cells used to represent physical
- base addresses.
-- #size-cells: the number of cells used to represent the size of an address.
-- ranges: the address mapping relationship to the parent, defined with
- - empty value: if optional 'reg' is used.
- - non-empty value: if optional 'reg' is not used. should set
- the child's base address to 0, the physical address
- within parent's address space, and the length of
- the address map.
-
-Required nodes : a sub-node is required for each port the controller
- provides. Address range information including the usual
- 'reg' property is used inside these nodes to describe
- the controller's topology.
-
-Optional properties (controller (parent) node):
- - reg : offset and length of register shared by multiple ports,
- exclude port's private register. It is needed on mt2701
- and mt8173, but not on mt2712.
- - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
- calibrate
- - mediatek,src-coef : coefficient for slew rate calibrate, depends on
- SoC process
-
-Required properties (port (child) node):
-- reg : address and length of the register set for the port.
-- #phy-cells : should be 1 (See second example)
- cell after port phandle is phy type from:
- - PHY_TYPE_USB2
- - PHY_TYPE_USB3
- - PHY_TYPE_PCIE
- - PHY_TYPE_SATA
-
-Optional properties (PHY_TYPE_USB2 port (child) node):
-- clocks : a list of phandle + clock-specifier pairs, one for each
- entry in clock-names
-- clock-names : may contain
- "ref": 48M reference clock for HighSpeed (digital) phy; and 26M
- reference clock for SuperSpeed (digital) phy, sometimes is
- 24M, 25M or 27M, depended on platform.
- "da_ref": the reference clock of analog phy, used if the clocks
- of analog and digital phys are separated, otherwise uses
- "ref" clock only if needed.
-
-- mediatek,eye-src : u32, the value of slew rate calibrate
-- mediatek,eye-vrt : u32, the selection of VRT reference voltage
-- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
-- mediatek,bc12 : bool, enable BC12 of u2phy if support it
-- mediatek,discth : u32, the selection of disconnect threshold
-- mediatek,intr : u32, the selection of internal R (resistance)
-
-Example:
-
-u3phy: usb-phy@11290000 {
- compatible = "mediatek,mt8173-u3phy";
- reg = <0 0x11290000 0 0x800>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- u2port0: usb-phy@11290800 {
- reg = <0 0x11290800 0 0x100>;
- clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
- clock-names = "ref";
- #phy-cells = <1>;
- };
-
- u3port0: usb-phy@11290900 {
- reg = <0 0x11290800 0 0x700>;
- clocks = <&clk26m>;
- clock-names = "ref";
- #phy-cells = <1>;
- };
-
- u2port1: usb-phy@11291000 {
- reg = <0 0x11291000 0 0x100>;
- clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
- clock-names = "ref";
- #phy-cells = <1>;
- };
-};
-
-Specifying phy control of devices
----------------------------------
-
-Device nodes should specify the configuration required in their "phys"
-property, containing a phandle to the phy port node and a device type;
-phy-names for each port are optional.
-
-Example:
-
-#include <dt-bindings/phy/phy.h>
-
-usb30: usb@11270000 {
- ...
- phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
- phy-names = "usb2-0", "usb3-0";
- ...
-};
-
-
-Layout differences of banks between mt8173/mt2701 and mt2712
--------------------------------------------------------------
-mt8173 and mt2701:
-port offset bank
-shared 0x0000 SPLLC
- 0x0100 FMREG
-u2 port0 0x0800 U2PHY_COM
-u3 port0 0x0900 U3PHYD
- 0x0a00 U3PHYD_BANK2
- 0x0b00 U3PHYA
- 0x0c00 U3PHYA_DA
-u2 port1 0x1000 U2PHY_COM
-u3 port1 0x1100 U3PHYD
- 0x1200 U3PHYD_BANK2
- 0x1300 U3PHYA
- 0x1400 U3PHYA_DA
-u2 port2 0x1800 U2PHY_COM
- ...
-
-mt2712:
-port offset bank
-u2 port0 0x0000 MISC
- 0x0100 FMREG
- 0x0300 U2PHY_COM
-u3 port0 0x0700 SPLLC
- 0x0800 CHIP
- 0x0900 U3PHYD
- 0x0a00 U3PHYD_BANK2
- 0x0b00 U3PHYA
- 0x0c00 U3PHYA_DA
-u2 port1 0x1000 MISC
- 0x1100 FMREG
- 0x1300 U2PHY_COM
-u3 port1 0x1700 SPLLC
- 0x1800 CHIP
- 0x1900 U3PHYD
- 0x1a00 U3PHYD_BANK2
- 0x1b00 U3PHYA
- 0x1c00 U3PHYA_DA
-u2 port2 0x2000 MISC
- ...
-
- SPLLC shared by u3 ports and FMREG shared by u2 ports on
-mt8173/mt2701 are put back into each port; a new bank MISC for
-u2 ports and CHIP for u3 ports are added on mt2712.
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 3/8] dt-bindings: phy: convert phy-mtk-ufs.txt to YAML schema
2020-10-14 1:44 [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 2/8] dt-bindings: phy: convert phy-mtk-tphy.txt " Chunfeng Yun
@ 2020-10-14 1:44 ` Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding " Chunfeng Yun
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Chunfeng Yun @ 2020-10-14 1:44 UTC (permalink / raw)
To: linux-mediatek; +Cc: Chunfeng Yun, srv_heupstream
Convert phy-mtk-ufs.txt to YAML schema mediatek,ufs-phy.yaml
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: fix binding check warning of reg in example
---
.../bindings/phy/mediatek,ufs-phy.yaml | 64 +++++++++++++++++++
.../devicetree/bindings/phy/phy-mtk-ufs.txt | 38 -----------
2 files changed, 64 insertions(+), 38 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
diff --git a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
new file mode 100644
index 000000000000..3a9be82e7f13
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Universal Flash Storage (UFS) M-PHY binding
+
+maintainers:
+ - Stanley Chu <stanley.chu@mediatek.com>
+ - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+description: |
+ UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
+ Each UFS M-PHY node should have its own node.
+ To bind UFS M-PHY with UFS host controller, the controller node should
+ contain a phandle reference to UFS M-PHY node.
+
+properties:
+ $nodename:
+ pattern: "^ufs-phy@[0-9a-f]+$"
+
+ compatible:
+ const: mediatek,mt8183-ufsphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Unipro core control clock.
+ - description: M-PHY core control clock.
+
+ clock-names:
+ items:
+ - const: unipro
+ - const: mp
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ ufsphy: ufs-phy@11fa0000 {
+ compatible = "mediatek,mt8183-ufsphy";
+ reg = <0x11fa0000 0xc000>;
+ clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
+ <&infracfg CLK_INFRA_UFS_MP_SAP_BCLK>;
+ clock-names = "unipro", "mp";
+ #phy-cells = <0>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt b/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
deleted file mode 100644
index 5789029a1d42..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-MediaTek Universal Flash Storage (UFS) M-PHY binding
---------------------------------------------------------
-
-UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
-Each UFS M-PHY node should have its own node.
-
-To bind UFS M-PHY with UFS host controller, the controller node should
-contain a phandle reference to UFS M-PHY node.
-
-Required properties for UFS M-PHY nodes:
-- compatible : Compatible list, contains the following controller:
- "mediatek,mt8183-ufsphy" for ufs phy
- persent on MT81xx chipsets.
-- reg : Address and length of the UFS M-PHY register set.
-- #phy-cells : This property shall be set to 0.
-- clocks : List of phandle and clock specifier pairs.
-- clock-names : List of clock input name strings sorted in the same
- order as the clocks property. Following clocks are
- mandatory.
- "unipro": Unipro core control clock.
- "mp": M-PHY core control clock.
-
-Example:
-
- ufsphy: phy@11fa0000 {
- compatible = "mediatek,mt8183-ufsphy";
- reg = <0 0x11fa0000 0 0xc000>;
- #phy-cells = <0>;
-
- clocks = <&infracfg_ao INFRACFG_AO_UNIPRO_SCK_CG>,
- <&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>;
- clock-names = "unipro", "mp";
- };
-
- ufshci@11270000 {
- ...
- phys = <&ufsphy>;
- };
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding to YAML schema
2020-10-14 1:44 [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 2/8] dt-bindings: phy: convert phy-mtk-tphy.txt " Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 3/8] dt-bindings: phy: convert phy-mtk-ufs.txt " Chunfeng Yun
@ 2020-10-14 1:44 ` Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 5/8] dt-bindings: usb: convert mediatek, musb.txt " Chunfeng Yun
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Chunfeng Yun @ 2020-10-14 1:44 UTC (permalink / raw)
To: linux-mediatek; +Cc: Chunfeng Yun, srv_heupstream
Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: fix binding check warning of reg in example
---
.../display/mediatek/mediatek,hdmi.txt | 17 +---
.../bindings/phy/mediatek,hdmi-phy.yaml | 90 +++++++++++++++++++
2 files changed, 91 insertions(+), 16 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
index 7b124242b0c5..edac18951a75 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
@@ -50,22 +50,7 @@ Required properties:
HDMI PHY
========
-
-The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
-output and drives the HDMI pads.
-
-Required properties:
-- compatible: "mediatek,<chip>-hdmi-phy"
-- reg: Physical base address and length of the module's registers
-- clocks: PLL reference clock
-- clock-names: must contain "pll_ref"
-- clock-output-names: must be "hdmitx_dig_cts" on mt8173
-- #phy-cells: must be <0>
-- #clock-cells: must be <0>
-
-Optional properties:
-- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
-- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
+See phy/mediatek,hdmi-phy.yaml
Example:
diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
new file mode 100644
index 000000000000..77df50204606
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+description: |
+ The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
+ output and drives the HDMI pads.
+
+properties:
+ $nodename:
+ pattern: "^hdmi-phy@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - mediatek,mt2701-hdmi-phy
+ - mediatek,mt8173-hdmi-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PLL reference clock
+
+ clock-names:
+ items:
+ - const: pll_ref
+
+ clock-output-names:
+ items:
+ - const: hdmitx_dig_cts
+
+ "#phy-cells":
+ const: 0
+
+ "#clock-cells":
+ const: 0
+
+ mediatek,ibias:
+ description:
+ TX DRV bias current for < 1.65Gbps
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 63
+ default: 0xa
+
+ mediatek,ibias_up:
+ description:
+ TX DRV bias current for >= 1.65Gbps
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 63
+ default: 0x1c
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - clock-output-names
+ - "#phy-cells"
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ hdmi_phy: hdmi-phy@10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0x10209100 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ clock-output-names = "hdmitx_dig_cts";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
+...
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 5/8] dt-bindings: usb: convert mediatek, musb.txt to YAML schema
2020-10-14 1:44 [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Chunfeng Yun
` (2 preceding siblings ...)
2020-10-14 1:44 ` [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding " Chunfeng Yun
@ 2020-10-14 1:44 ` Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 6/8] dt-bindings: usb: convert mediatek, mtk-xhci.txt " Chunfeng Yun
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Chunfeng Yun @ 2020-10-14 1:44 UTC (permalink / raw)
To: linux-mediatek; +Cc: Chunfeng Yun, Min Guo, srv_heupstream
Convert mediatek,musb.txt to YAML schema mediatek,musb.yaml
Cc: Min Guo <min.guo@mediatek.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: new patch
---
.../devicetree/bindings/usb/mediatek,musb.txt | 57 ---------
.../bindings/usb/mediatek,musb.yaml | 113 ++++++++++++++++++
2 files changed, 113 insertions(+), 57 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.txt
create mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.yaml
diff --git a/Documentation/devicetree/bindings/usb/mediatek,musb.txt b/Documentation/devicetree/bindings/usb/mediatek,musb.txt
deleted file mode 100644
index 5eedb0296562..000000000000
--- a/Documentation/devicetree/bindings/usb/mediatek,musb.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-MediaTek musb DRD/OTG controller
--------------------------------------------
-
-Required properties:
- - compatible : should be one of:
- "mediatek,mt2701-musb"
- ...
- followed by "mediatek,mtk-musb"
- - reg : specifies physical base address and size of
- the registers
- - interrupts : interrupt used by musb controller
- - interrupt-names : must be "mc"
- - phys : PHY specifier for the OTG phy
- - dr_mode : should be one of "host", "peripheral" or "otg",
- refer to usb/generic.txt
- - clocks : a list of phandle + clock-specifier pairs, one for
- each entry in clock-names
- - clock-names : must contain "main", "mcu", "univpll"
- for clocks of controller
-
-Optional properties:
- - power-domains : a phandle to USB power domain node to control USB's
- MTCMOS
-
-Required child nodes:
- usb connector node as defined in bindings/connector/usb-connector.yaml
-Optional properties:
- - id-gpios : input GPIO for USB ID pin.
- - vbus-gpios : input GPIO for USB VBUS pin.
- - vbus-supply : reference to the VBUS regulator, needed when supports
- dual-role mode
- - usb-role-switch : use USB Role Switch to support dual-role switch, see
- usb/generic.txt.
-
-Example:
-
-usb2: usb@11200000 {
- compatible = "mediatek,mt2701-musb",
- "mediatek,mtk-musb";
- reg = <0 0x11200000 0 0x1000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "mc";
- phys = <&u2port2 PHY_TYPE_USB2>;
- dr_mode = "otg";
- clocks = <&pericfg CLK_PERI_USB0>,
- <&pericfg CLK_PERI_USB0_MCU>,
- <&pericfg CLK_PERI_USB_SLV>;
- clock-names = "main","mcu","univpll";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
- usb-role-switch;
- connector{
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- type = "micro";
- id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
- vbus-supply = <&usb_vbus>;
- };
-};
diff --git a/Documentation/devicetree/bindings/usb/mediatek,musb.yaml b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml
new file mode 100644
index 000000000000..f2b3dcb3d52c
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/mediatek,musb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MUSB DRD/OTG Controller Device Tree Bindings
+
+maintainers:
+ - Min Guo <min.guo@mediatek.com>
+
+properties:
+ $nodename:
+ pattern: '^usb@[0-9a-f]+$'
+
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt2701-musb
+ - const: mediatek,mtk-musb
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ items:
+ - const: mc
+
+ clocks:
+ items:
+ - description: The main/core clock
+ - description: The system bus clock
+ - description: The 48Mhz clock
+
+ clock-names:
+ items:
+ - const: main
+ - const: mcu
+ - const: univpll
+
+ phys:
+ maxItems: 1
+
+ usb-role-switch:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Support role switch. See usb/generic.txt
+ type: boolean
+
+ dr_mode:
+ enum:
+ - host
+ - otg
+ - peripheral
+
+ power-domains:
+ description: A phandle to USB power domain node to control USB's MTCMOS
+ maxItems: 1
+
+ connector:
+ $ref: /connector/usb-connector.yaml#
+ description: Connector for dual role switch
+ type: object
+
+dependencies:
+ usb-role-switch: [ 'connector' ]
+ connector: [ 'usb-role-switch' ]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - phys
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt2701-clk.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/power/mt2701-power.h>
+
+ usb2: usb@11200000 {
+ compatible = "mediatek,mt2701-musb", "mediatek,mtk-musb";
+ reg = <0x11200000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "mc";
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ dr_mode = "otg";
+ clocks = <&pericfg CLK_PERI_USB0>,
+ <&pericfg CLK_PERI_USB0_MCU>,
+ <&pericfg CLK_PERI_USB_SLV>;
+ clock-names = "main","mcu","univpll";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+ usb-role-switch;
+
+ connector{
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ type = "micro";
+ id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
+ vbus-supply = <&usb_vbus>;
+ };
+ };
+...
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 6/8] dt-bindings: usb: convert mediatek, mtk-xhci.txt to YAML schema
2020-10-14 1:44 [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Chunfeng Yun
` (3 preceding siblings ...)
2020-10-14 1:44 ` [PATCH v2 5/8] dt-bindings: usb: convert mediatek, musb.txt " Chunfeng Yun
@ 2020-10-14 1:44 ` Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 7/8] dt-bindings: usb: convert mediatek, mtu3.txt " Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 8/8] MAINTAINERS: update MediaTek PHY/USB entry Chunfeng Yun
6 siblings, 0 replies; 10+ messages in thread
From: Chunfeng Yun @ 2020-10-14 1:44 UTC (permalink / raw)
To: linux-mediatek; +Cc: Chunfeng Yun, srv_heupstream
Convert mediatek,mtk-xhci.txt to YAML schema mediatek,mtk-xhci.yaml
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: new patch
---
.../bindings/usb/mediatek,mtk-xhci.txt | 121 ------------
.../bindings/usb/mediatek,mtk-xhci.yaml | 180 ++++++++++++++++++
2 files changed, 180 insertions(+), 121 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
create mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
deleted file mode 100644
index 42d8814f903a..000000000000
--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
+++ /dev/null
@@ -1,121 +0,0 @@
-MT8173 xHCI
-
-The device node for Mediatek SOC USB3.0 host controller
-
-There are two scenarios: the first one only supports xHCI driver;
-the second one supports dual-role mode, and the host is based on xHCI
-driver. Take account of backward compatibility, we divide bindings
-into two parts.
-
-1st: only supports xHCI driver
-------------------------------------------------------------------------
-
-Required properties:
- - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci",
- soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
- "mediatek,mtk-xhci" compatible string, you need SoC specific ones in
- addition, one of:
- - "mediatek,mt8173-xhci"
- - reg : specifies physical base address and size of the registers
- - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
- - interrupts : interrupt used by the controller
- - power-domains : a phandle to USB power domain node to control USB's
- mtcmos
- - vusb33-supply : regulator of USB avdd3.3v
-
- - clocks : a list of phandle + clock-specifier pairs, one for each
- entry in clock-names
- - clock-names : must contain
- "sys_ck": controller clock used by normal mode,
- the following ones are optional:
- "ref_ck": reference clock used by low power mode etc,
- "mcu_ck": mcu_bus clock for register access,
- "dma_ck": dma_bus clock for data transfer by DMA,
- "xhci_ck": controller clock
-
- - phys : see usb-hcd.yaml in the current directory
-
-Optional properties:
- - wakeup-source : enable USB remote wakeup;
- - mediatek,syscon-wakeup : phandle to syscon used to access the register
- of the USB wakeup glue layer between xHCI and SPM; it depends on
- "wakeup-source", and has two arguments:
- - the first one : register base address of the glue layer in syscon;
- - the second one : hardware version of the glue layer
- - 1 : used by mt8173 etc
- - 2 : used by mt2712 etc
- - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
- bit1 for u3port1, ... etc;
- - vbus-supply : reference to the VBUS regulator;
- - usb3-lpm-capable : supports USB3.0 LPM
- - pinctrl-names : a pinctrl state named "default" must be defined
- - pinctrl-0 : pin control group
- See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
- - imod-interval-ns: default interrupt moderation interval is 5000ns
-
-additionally the properties from usb-hcd.yaml (in the current directory) are
-supported.
-
-Example:
-usb30: usb@11270000 {
- compatible = "mediatek,mt8173-xhci";
- reg = <0 0x11270000 0 0x1000>,
- <0 0x11280700 0 0x0100>;
- reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
- <&pericfg CLK_PERI_USB0>,
- <&pericfg CLK_PERI_USB1>;
- clock-names = "sys_ck", "ref_ck";
- phys = <&phy_port0 PHY_TYPE_USB3>,
- <&phy_port1 PHY_TYPE_USB2>;
- vusb33-supply = <&mt6397_vusb_reg>;
- vbus-supply = <&usb_p1_vbus>;
- usb3-lpm-capable;
- mediatek,syscon-wakeup = <&pericfg 0x400 1>;
- wakeup-source;
- imod-interval-ns = <10000>;
-};
-
-2nd: dual-role mode with xHCI driver
-------------------------------------------------------------------------
-
-In the case, xhci is added as subnode to mtu3. An example and the DT binding
-details of mtu3 can be found in:
-Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
-
-Required properties:
- - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci",
- soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
- "mediatek,mtk-xhci" compatible string, you need SoC specific ones in
- addition, one of:
- - "mediatek,mt8173-xhci"
- - reg : specifies physical base address and size of the registers
- - reg-names: should be "mac" for xHCI MAC
- - interrupts : interrupt used by the host controller
- - power-domains : a phandle to USB power domain node to control USB's
- mtcmos
- - vusb33-supply : regulator of USB avdd3.3v
-
- - clocks : a list of phandle + clock-specifier pairs, one for each
- entry in clock-names
- - clock-names : must contain "sys_ck", and the following ones are optional:
- "ref_ck", "mcu_ck" and "dma_ck", "xhci_ck"
-
-Optional properties:
- - vbus-supply : reference to the VBUS regulator;
- - usb3-lpm-capable : supports USB3.0 LPM
-
-Example:
-usb30: usb@11270000 {
- compatible = "mediatek,mt8173-xhci";
- reg = <0 0x11270000 0 0x1000>;
- reg-names = "mac";
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
- clock-names = "sys_ck", "ref_ck";
- vusb33-supply = <&mt6397_vusb_reg>;
- usb3-lpm-capable;
-};
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
new file mode 100644
index 000000000000..ea696c8f1269
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
@@ -0,0 +1,180 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek USB3 xHCI Device Tree Bindings
+
+maintainers:
+ - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+allOf:
+ - $ref: "usb-hcd.yaml"
+
+description: |
+ There are two scenarios:
+ case 1: only supports xHCI driver;
+ case 2: supports dual-role mode, and the host is based on xHCI driver.
+
+properties:
+ #common properties for both case 1 and case 2
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt2712-xhci
+ - mediatek,mt7622-xhci
+ - mediatek,mt7629-xhci
+ - mediatek,mt8173-xhci
+ - mediatek,mt8183-xhci
+ - const: mediatek,mtk-xhci
+
+ reg:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: the registers of xHCI MAC
+ - description: the registers of IP Port Control
+
+ reg-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: mac
+ - const: ippc #optional, only needed for case 1.
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle to USB power domain node to control USB's MTCMOS
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 5
+ items:
+ - description: Controller clock used by normal mode
+ - description: Reference clock used by low power mode etc
+ - description: Mcu bus clock for register access
+ - description: DMA bus clock for data transfer
+ - description: controller clock
+
+ clock-names:
+ minItems: 1
+ maxItems: 5
+ items:
+ - const: sys_ck #required, the following ones are optional
+ - const: ref_ck
+ - const: mcu_ck
+ - const: dma_ck
+ - const: xhci_ck
+
+ phys:
+ $ref: /usb/usb-hcd.yaml#
+
+ vusb33-supply:
+ description: Regulator of USB AVDD3.3v
+
+ vbus-supply:
+ description: Regulator of USB VBUS5v
+
+ usb3-lpm-capable:
+ description: supports USB3.0 LPM
+ type: boolean
+
+ imod-interval-ns:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Interrupt moderation interval value, it is 8 times as much as that
+ defined in the xHCI spec on MTK's controller.
+ default: 5000
+
+ #the following properties are only used for case 1
+ pinctrl-0:
+ description: A phandle to the default pinctrl state.
+
+ pinctrl-names:
+ description: A pinctrl state named "default" must be defined.
+ See pinctrl/pinctrl-bindings.txt
+ const: default
+
+ wakeup-source:
+ description: enable USB remote wakeup, see power/wakeup-source.txt
+ type: boolean
+
+ mediatek,syscon-wakeup:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+ description: |
+ A phandle to syscon used to access the register of the USB wakeup glue
+ layer between xHCI and SPM, the field should always be a multiple of
+ 3 cells long.
+
+ items:
+ - description:
+ The first cell represents a phandle to syscon
+ - description:
+ The second cell represents the register base address of the glue
+ layer in syscon
+ - description:
+ The third cell represents the hardware version of the glue layer,
+ 1 is used by mt8173 etc, 2 is used by mt2712 etc
+ enum: [1, 2]
+
+ mediatek,u3p-dis-msk:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The mask to disable u3ports, bit0 for u3port0,
+ bit1 for u3port1, ... etc
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^[a-f]+@[0-9a-f]+$":
+ $ref: /usb/usb-hcd.yaml#
+ type: object
+ description: The hard wired USB devices.
+
+dependencies:
+ wakeup-source: [ 'mediatek,syscon-wakeup' ]
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/power/mt8173-power.h>
+
+ usb3: usb@11270000 {
+ compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
+ reg = <0x11270000 0x1000>, <0x11280700 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+ clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
+ clock-names = "sys_ck", "ref_ck";
+ phys = <&u3port0 PHY_TYPE_USB3>, <&u2port1 PHY_TYPE_USB2>;
+ vusb33-supply = <&mt6397_vusb_reg>;
+ vbus-supply = <&usb_p1_vbus>;
+ imod-interval-ns = <10000>;
+ mediatek,syscon-wakeup = <&pericfg 0x400 1>;
+ wakeup-source;
+ usb3-lpm-capable;
+ };
+...
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 7/8] dt-bindings: usb: convert mediatek, mtu3.txt to YAML schema
2020-10-14 1:44 [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Chunfeng Yun
` (4 preceding siblings ...)
2020-10-14 1:44 ` [PATCH v2 6/8] dt-bindings: usb: convert mediatek, mtk-xhci.txt " Chunfeng Yun
@ 2020-10-14 1:44 ` Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 8/8] MAINTAINERS: update MediaTek PHY/USB entry Chunfeng Yun
6 siblings, 0 replies; 10+ messages in thread
From: Chunfeng Yun @ 2020-10-14 1:44 UTC (permalink / raw)
To: linux-mediatek; +Cc: Chunfeng Yun, srv_heupstream
Convert mediatek,mtu3.txt to YAML schema mediatek,mtu3.yaml
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: new patch
---
.../devicetree/bindings/usb/mediatek,mtu3.txt | 108 ---------
.../bindings/usb/mediatek,mtu3.yaml | 227 ++++++++++++++++++
2 files changed, 227 insertions(+), 108 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
create mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
deleted file mode 100644
index a82ca438aec1..000000000000
--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
+++ /dev/null
@@ -1,108 +0,0 @@
-The device node for Mediatek USB3.0 DRD controller
-
-Required properties:
- - compatible : should be "mediatek,<soc-model>-mtu3", "mediatek,mtu3",
- soc-model is the name of SoC, such as mt8173, mt2712 etc,
- when using "mediatek,mtu3" compatible string, you need SoC specific
- ones in addition, one of:
- - "mediatek,mt8173-mtu3"
- - reg : specifies physical base address and size of the registers
- - reg-names: should be "mac" for device IP and "ippc" for IP port control
- - interrupts : interrupt used by the device IP
- - power-domains : a phandle to USB power domain node to control USB's
- mtcmos
- - vusb33-supply : regulator of USB avdd3.3v
- - clocks : a list of phandle + clock-specifier pairs, one for each
- entry in clock-names
- - clock-names : must contain "sys_ck" for clock of controller,
- the following clocks are optional:
- "ref_ck", "mcu_ck" and "dma_ck";
- - phys : see usb-hcd.yaml in the current directory
- - dr_mode : should be one of "host", "peripheral" or "otg",
- refer to usb/generic.txt
-
-Optional properties:
- - #address-cells, #size-cells : should be '2' if the device has sub-nodes
- with 'reg' property
- - ranges : allows valid 1:1 translation between child's address space and
- parent's address space
- - extcon : external connector for vbus and idpin changes detection, needed
- when supports dual-role mode.
- it's considered valid for compatibility reasons, not allowed for
- new bindings, and use "usb-role-switch" property instead.
- - vbus-supply : reference to the VBUS regulator, needed when supports
- dual-role mode.
- it's considered valid for compatibility reasons, not allowed for
- new bindings, and put into a usb-connector node.
- see connector/usb-connector.yaml.
- - pinctrl-names : a pinctrl state named "default" is optional, and need be
- defined if auto drd switch is enabled, that means the property dr_mode
- is set as "otg", and meanwhile the property "mediatek,enable-manual-drd"
- is not set.
- - pinctrl-0 : pin control group
- See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
-
- - maximum-speed : valid arguments are "super-speed", "high-speed" and
- "full-speed"; refer to usb/generic.txt
- - usb-role-switch : use USB Role Switch to support dual-role switch, but
- not extcon; see usb/generic.txt.
- - enable-manual-drd : supports manual dual-role switch via debugfs; usually
- used when receptacle is TYPE-A and also wants to support dual-role
- mode.
- - wakeup-source: enable USB remote wakeup of host mode.
- - mediatek,syscon-wakeup : phandle to syscon used to access the register
- of the USB wakeup glue layer between SSUSB and SPM; it depends on
- "wakeup-source", and has two arguments:
- - the first one : register base address of the glue layer in syscon;
- - the second one : hardware version of the glue layer
- - 1 : used by mt8173 etc
- - 2 : used by mt2712 etc
- - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
- bit1 for u3port1, ... etc;
-
-additionally the properties from usb-hcd.yaml (in the current directory) are
-supported.
-
-Sub-nodes:
-The xhci should be added as subnode to mtu3 as shown in the following example
-if host mode is enabled. The DT binding details of xhci can be found in:
-Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
-
-The port would be added as subnode if use "usb-role-switch" property.
- see graph.txt
-
-Example:
-ssusb: usb@11271000 {
- compatible = "mediatek,mt8173-mtu3";
- reg = <0 0x11271000 0 0x3000>,
- <0 0x11280700 0 0x0100>;
- reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
- phys = <&phy_port0 PHY_TYPE_USB3>,
- <&phy_port1 PHY_TYPE_USB2>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
- <&pericfg CLK_PERI_USB0>,
- <&pericfg CLK_PERI_USB1>;
- clock-names = "sys_ck", "ref_ck";
- vusb33-supply = <&mt6397_vusb_reg>;
- vbus-supply = <&usb_p0_vbus>;
- extcon = <&extcon_usb>;
- dr_mode = "otg";
- wakeup-source;
- mediatek,syscon-wakeup = <&pericfg 0x400 1>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- usb_host: xhci@11270000 {
- compatible = "mediatek,mt8173-xhci";
- reg = <0 0x11270000 0 0x1000>;
- reg-names = "mac";
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
- clock-names = "sys_ck", "ref_ck";
- vusb33-supply = <&mt6397_vusb_reg>;
- };
-};
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
new file mode 100644
index 000000000000..57ef2ced9f31
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
@@ -0,0 +1,227 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/mediatek,mtu3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek USB3 DRD Controller Device Tree Bindings
+
+maintainers:
+ - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+description: |
+ The DRD controller has a glue layer IPPC (IP Port Control), and its host is
+ based on xHCI.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt2712-mtu3
+ - mediatek,mt8173-mtu3
+ - mediatek,mt8183-mtu3
+ - const: mediatek,mtu3
+
+ reg:
+ items:
+ - description: the registers of device MAC
+ - description: the registers of IP Port Control
+
+ reg-names:
+ items:
+ - const: mac
+ - const: ippc
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle to USB power domain node to control USB's MTCMOS
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+ items:
+ - description: Controller clock used by normal mode
+ - description: Reference clock used by low power mode etc
+ - description: Mcu bus clock for register access
+ - description: DMA bus clock for data transfer
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+ items:
+ - const: sys_ck #required, the following ones are optional
+ - const: ref_ck
+ - const: mcu_ck
+ - const: dma_ck
+
+ phys:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: List of all the USB PHYs used
+
+ vusb33-supply:
+ description: Regulator of USB AVDD3.3v
+
+ vbus-supply:
+ $ref: /connector/usb-connector.yaml#
+ deprecated: true
+ description: |
+ Regulator of USB VBUS5v, needed when supports dual-role mode.
+ Particularly, if use an output GPIO to control a VBUS regulator, should
+ model it as a regulator. See bindings/regulator/fixed-regulator.yaml
+ It's considered valid for compatibility reasons, not allowed for
+ new bindings, and put into a usb-connector node.
+
+ dr_mode:
+ description: See usb/generic.txt
+ enum: [host, peripheral, otg]
+ default: otg
+
+ maximum-speed:
+ description: See usb/generic.txt
+ enum: [super-speed-plus, super-speed, high-speed, full-speed]
+
+ "#address-cells":
+ enum: [1, 2]
+
+ "#size-cells":
+ enum: [1, 2]
+
+ ranges: true
+
+ pinctrl-0:
+ description: A phandle to the default pinctrl state
+
+ pinctrl-names:
+ description: Usually it's needed when use IDDIG/VBUS pin.
+ See pinctrl/pinctrl-bindings.txt
+ const: default
+
+ extcon:
+ deprecated: true
+ description: |
+ Phandle to the extcon device detecting the IDDIG/VBUS state, neede
+ when supports dual-role mode.
+ It's considered valid for compatibility reasons, not allowed for
+ new bindings, and use "usb-role-switch" property instead.
+
+ usb-role-switch:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Support role switch. See usb/generic.txt
+ type: boolean
+
+ connector:
+ $ref: /connector/usb-connector.yaml#
+ description:
+ Connector for dual role switch, especially for "gpio-usb-b-connector"
+ type: object
+
+ port:
+ description: |
+ Any connector to the data bus of this controller should be modelled
+ using the OF graph bindings specified, if the "usb-role-switch"
+ property is used. See graph.txt
+ type: object
+
+ enable-manual-drd:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ supports manual dual-role switch via debugfs; usually used when
+ receptacle is TYPE-A and also wants to support dual-role mode.
+ type: boolean
+
+ wakeup-source:
+ description: enable USB remote wakeup, see power/wakeup-source.txt
+ type: boolean
+
+ mediatek,syscon-wakeup:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+ description: |
+ A phandle to syscon used to access the register of the USB wakeup glue
+ layer between xHCI and SPM, the field should always be a multiple of
+ 3 cells long.
+
+ items:
+ - description:
+ The first cell represents a phandle to syscon
+ - description:
+ The second cell represents the register base address of the glue
+ layer in syscon
+ - description:
+ The third cell represents the hardware version of the glue layer,
+ 1 is used by mt8173 etc, 2 is used by mt2712 etc
+ enum: [1, 2]
+
+ mediatek,u3p-dis-msk:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The mask to disable u3ports, bit0 for u3port0,
+ bit1 for u3port1, ... etc
+
+# Required child node when support dual-role
+patternProperties:
+ "^usb@[0-9a-f]+$":
+ type: object
+ $ref: /usb/mediatek,mtk-xhci.yaml#
+ description: |
+ The xhci should be added as subnode to mtu3 as shown in the following
+ example if the host mode is enabled.
+
+dependencies:
+ connector: [ 'usb-role-switch' ]
+ port: [ 'usb-role-switch' ]
+ wakeup-source: [ 'mediatek,syscon-wakeup' ]
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+ - phys
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/power/mt8173-power.h>
+
+ ssusb: usb@11271000 {
+ compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
+ reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&phy_port0 PHY_TYPE_USB3>, <&phy_port1 PHY_TYPE_USB2>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+ clocks = <&topckgen CLK_TOP_USB30_SEL>;
+ clock-names = "sys_ck";
+ vusb33-supply = <&mt6397_vusb_reg>;
+ vbus-supply = <&usb_p0_vbus>;
+ extcon = <&extcon_usb>;
+ dr_mode = "otg";
+ wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x400 1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ xhci: usb@11270000 {
+ compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
+ reg = <0x11270000 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+ clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
+ clock-names = "sys_ck", "ref_ck";
+ vusb33-supply = <&mt6397_vusb_reg>;
+ };
+ };
+...
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 8/8] MAINTAINERS: update MediaTek PHY/USB entry
2020-10-14 1:44 [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Chunfeng Yun
` (5 preceding siblings ...)
2020-10-14 1:44 ` [PATCH v2 7/8] dt-bindings: usb: convert mediatek, mtu3.txt " Chunfeng Yun
@ 2020-10-14 1:44 ` Chunfeng Yun
6 siblings, 0 replies; 10+ messages in thread
From: Chunfeng Yun @ 2020-10-14 1:44 UTC (permalink / raw)
To: linux-mediatek; +Cc: Chunfeng Yun, srv_heupstream
Due to the phy/usb bindings are converted into YAML schema and
also renamed, update entries.
Meanwhile add drivers/usb/host/mtk-xhci* files.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: new patch
---
MAINTAINERS | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..d68725d87e44 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2105,7 +2105,7 @@ M: Chunfeng Yun <chunfeng.yun@mediatek.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Maintained
-F: Documentation/devicetree/bindings/phy/phy-mtk-*
+F: Documentation/devicetree/bindings/phy/mediatek,*
F: drivers/phy/mediatek/
ARM/Microchip (AT91) SoC support
@@ -11028,6 +11028,8 @@ L: linux-usb@vger.kernel.org (moderated for non-subscribers)
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Maintained
+F: Documentation/devicetree/bindings/usb/mediatek,*
+F: drivers/usb/host/xhci-mtk*
F: drivers/usb/mtu3/
MEGACHIPS STDPXXXX-GE-B850V3-FW LVDS/DP++ BRIDGES
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema
2020-10-16 17:00 ` [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Rob Herring
@ 2020-10-20 2:30 ` Chunfeng Yun
0 siblings, 0 replies; 10+ messages in thread
From: Chunfeng Yun @ 2020-10-20 2:30 UTC (permalink / raw)
To: Rob Herring
Cc: Chun-Kuang Hu, Min Guo, Philipp Zabel, devicetree, David Airlie,
Greg Kroah-Hartman, linux-usb, linux-kernel, dri-devel,
Kishon Vijay Abraham I, Mauro Carvalho Chehab, Vinod Koul, CK Hu,
linux-mediatek, Daniel Vetter, Matthias Brugger, Stanley Chu,
David S . Miller, linux-arm-kernel
On Fri, 2020-10-16 at 12:00 -0500, Rob Herring wrote:
> On Tue, Oct 13, 2020 at 04:52:00PM +0800, Chunfeng Yun wrote:
> > Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml
> >
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > v2: modify description and compatible definition suggested by Rob
> > ---
> > .../bindings/phy/mediatek,xsphy.yaml | 200 ++++++++++++++++++
> > .../devicetree/bindings/phy/phy-mtk-xsphy.txt | 109 ----------
> > 2 files changed, 200 insertions(+), 109 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> > delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
> >
> > diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> > new file mode 100644
> > index 000000000000..86511f19277a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> > @@ -0,0 +1,200 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2020 MediaTek
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek XS-PHY Controller Device Tree Bindings
> > +
> > +maintainers:
> > + - Chunfeng Yun <chunfeng.yun@mediatek.com>
> > +
> > +description: |
> > + The XS-PHY controller supports physical layer functionality for USB3.1
> > + GEN2 controller on MediaTek SoCs.
[...]
> > +
> > + ranges: true
> > +
> > + mediatek,src-ref-clk-mhz:
> > + description:
> > + Frequency of reference clock for slew rate calibrate
> > + $ref: /schemas/types.yaml#/definitions/uint32
>
> Properties with a standard unit suffix don't need a type.
Ok, will remove it, and also do it for other patches, thanks
> > --
[...]
> > 2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema
[not found] <20201013085207.17749-1-chunfeng.yun@mediatek.com>
@ 2020-10-16 17:00 ` Rob Herring
2020-10-20 2:30 ` Chunfeng Yun
0 siblings, 1 reply; 10+ messages in thread
From: Rob Herring @ 2020-10-16 17:00 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Chun-Kuang Hu, Min Guo, Philipp Zabel, devicetree, David Airlie,
Greg Kroah-Hartman, linux-usb, linux-kernel, dri-devel,
Kishon Vijay Abraham I, Mauro Carvalho Chehab, Vinod Koul, CK Hu,
linux-mediatek, Daniel Vetter, Matthias Brugger, Stanley Chu,
David S . Miller, linux-arm-kernel
On Tue, Oct 13, 2020 at 04:52:00PM +0800, Chunfeng Yun wrote:
> Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: modify description and compatible definition suggested by Rob
> ---
> .../bindings/phy/mediatek,xsphy.yaml | 200 ++++++++++++++++++
> .../devicetree/bindings/phy/phy-mtk-xsphy.txt | 109 ----------
> 2 files changed, 200 insertions(+), 109 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> new file mode 100644
> index 000000000000..86511f19277a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> @@ -0,0 +1,200 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek XS-PHY Controller Device Tree Bindings
> +
> +maintainers:
> + - Chunfeng Yun <chunfeng.yun@mediatek.com>
> +
> +description: |
> + The XS-PHY controller supports physical layer functionality for USB3.1
> + GEN2 controller on MediaTek SoCs.
> +
> + Banks layout of xsphy
> + ----------------------------------
> + port offset bank
> + u2 port0 0x0000 MISC
> + 0x0100 FMREG
> + 0x0300 U2PHY_COM
> + u2 port1 0x1000 MISC
> + 0x1100 FMREG
> + 0x1300 U2PHY_COM
> + u2 port2 0x2000 MISC
> + ...
> + u31 common 0x3000 DIG_GLB
> + 0x3100 PHYA_GLB
> + u31 port0 0x3400 DIG_LN_TOP
> + 0x3500 DIG_LN_TX0
> + 0x3600 DIG_LN_RX0
> + 0x3700 DIG_LN_DAIF
> + 0x3800 PHYA_LN
> + u31 port1 0x3a00 DIG_LN_TOP
> + 0x3b00 DIG_LN_TX0
> + 0x3c00 DIG_LN_RX0
> + 0x3d00 DIG_LN_DAIF
> + 0x3e00 PHYA_LN
> + ...
> + DIG_GLB & PHYA_GLB are shared by U31 ports.
> +
> +properties:
> + $nodename:
> + pattern: "^xs-phy@[0-9a-f]+$"
> +
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt3611-xsphy
> + - mediatek,mt3612-xsphy
> + - const: mediatek,xsphy
> +
> + reg:
> + description: |
> + Register shared by multiple U3 ports, exclude port's private register,
> + if only U2 ports provided, shouldn't use the property.
> + maxItems: 1
> +
> + "#address-cells":
> + enum: [1, 2]
> +
> + "#size-cells":
> + enum: [1, 2]
> +
> + ranges: true
> +
> + mediatek,src-ref-clk-mhz:
> + description:
> + Frequency of reference clock for slew rate calibrate
> + $ref: /schemas/types.yaml#/definitions/uint32
Properties with a standard unit suffix don't need a type.
> + default: 26
> +
> + mediatek,src-coef:
> + description:
> + Coefficient for slew rate calibrate, depends on SoC process
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 17
> +
> +# Required child node:
> +patternProperties:
> + "^usb-phy@[0-9a-f]+$":
> + type: object
> + description: |
> + A sub-node is required for each port the controller provides.
> + Address range information including the usual 'reg' property
> + is used inside these nodes to describe the controller's topology.
> +
> + properties:
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
> +
> + clock-names:
> + items:
> + - const: ref
> +
> + "#phy-cells":
> + const: 1
> + description: |
> + The cells contain the following arguments.
> +
> + - description: The PHY type
> + enum:
> + - PHY_TYPE_USB2
> + - PHY_TYPE_USB3
> +
> + #The following optional vendor properties are only for debug or HQA test
> + mediatek,eye-src:
> + description:
> + The value of slew rate calibrate (U2 phy)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 7
> +
> + mediatek,eye-vrt:
> + description:
> + The selection of VRT reference voltage (U2 phy)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 7
> +
> + mediatek,eye-term:
> + description:
> + The selection of HS_TX TERM reference voltage (U2 phy)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 7
> +
> + mediatek,efuse-intr:
> + description:
> + The selection of Internal Resistor (U2/U3 phy)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 63
> +
> + mediatek,efuse-tx-imp:
> + description:
> + The selection of TX Impedance (U3 phy)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 31
> +
> + mediatek,efuse-rx-imp:
> + description:
> + The selection of RX Impedance (U3 phy)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 31
> +
> + required:
> + - reg
> + - clocks
> + - clock-names
> + - "#phy-cells"
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - "#address-cells"
> + - "#size-cells"
> + - ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/phy/phy.h>
> +
> + u3phy: xs-phy@11c40000 {
> + compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
> + reg = <0x11c43000 0x0200>;
> + mediatek,src-ref-clk-mhz = <26>;
> + mediatek,src-coef = <17>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + u2port0: usb-phy@11c40000 {
> + reg = <0x11c40000 0x0400>;
> + clocks = <&clk48m>;
> + clock-names = "ref";
> + mediatek,eye-src = <4>;
> + #phy-cells = <1>;
> + };
> +
> + u3port0: usb-phy@11c43000 {
> + reg = <0x11c43400 0x0500>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + mediatek,efuse-intr = <28>;
> + #phy-cells = <1>;
> + };
> + };
> +
> +...
> diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
> deleted file mode 100644
> index e7caefa0b9c2..000000000000
> --- a/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
> +++ /dev/null
> @@ -1,109 +0,0 @@
> -MediaTek XS-PHY binding
> ---------------------------
> -
> -The XS-PHY controller supports physical layer functionality for USB3.1
> -GEN2 controller on MediaTek SoCs.
> -
> -Required properties (controller (parent) node):
> - - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
> - soc-model is the name of SoC, such as mt3611 etc;
> - when using "mediatek,xsphy" compatible string, you need SoC specific
> - ones in addition, one of:
> - - "mediatek,mt3611-xsphy"
> -
> - - #address-cells, #size-cells : should use the same values as the root node
> - - ranges: must be present
> -
> -Optional properties (controller (parent) node):
> - - reg : offset and length of register shared by multiple U3 ports,
> - exclude port's private register, if only U2 ports provided,
> - shouldn't use the property.
> - - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
> - calibrate
> - - mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on
> - SoC process
> -
> -Required nodes : a sub-node is required for each port the controller
> - provides. Address range information including the usual
> - 'reg' property is used inside these nodes to describe
> - the controller's topology.
> -
> -Required properties (port (child) node):
> -- reg : address and length of the register set for the port.
> -- clocks : a list of phandle + clock-specifier pairs, one for each
> - entry in clock-names
> -- clock-names : must contain
> - "ref": 48M reference clock for HighSpeed analog phy; and 26M
> - reference clock for SuperSpeedPlus analog phy, sometimes is
> - 24M, 25M or 27M, depended on platform.
> -- #phy-cells : should be 1
> - cell after port phandle is phy type from:
> - - PHY_TYPE_USB2
> - - PHY_TYPE_USB3
> -
> -The following optional properties are only for debug or HQA test
> -Optional properties (PHY_TYPE_USB2 port (child) node):
> -- mediatek,eye-src : u32, the value of slew rate calibrate
> -- mediatek,eye-vrt : u32, the selection of VRT reference voltage
> -- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
> -- mediatek,efuse-intr : u32, the selection of Internal Resistor
> -
> -Optional properties (PHY_TYPE_USB3 port (child) node):
> -- mediatek,efuse-intr : u32, the selection of Internal Resistor
> -- mediatek,efuse-tx-imp : u32, the selection of TX Impedance
> -- mediatek,efuse-rx-imp : u32, the selection of RX Impedance
> -
> -Banks layout of xsphy
> --------------------------------------------------------------
> -port offset bank
> -u2 port0 0x0000 MISC
> - 0x0100 FMREG
> - 0x0300 U2PHY_COM
> -u2 port1 0x1000 MISC
> - 0x1100 FMREG
> - 0x1300 U2PHY_COM
> -u2 port2 0x2000 MISC
> - ...
> -u31 common 0x3000 DIG_GLB
> - 0x3100 PHYA_GLB
> -u31 port0 0x3400 DIG_LN_TOP
> - 0x3500 DIG_LN_TX0
> - 0x3600 DIG_LN_RX0
> - 0x3700 DIG_LN_DAIF
> - 0x3800 PHYA_LN
> -u31 port1 0x3a00 DIG_LN_TOP
> - 0x3b00 DIG_LN_TX0
> - 0x3c00 DIG_LN_RX0
> - 0x3d00 DIG_LN_DAIF
> - 0x3e00 PHYA_LN
> - ...
> -
> -DIG_GLB & PHYA_GLB are shared by U31 ports.
> -
> -Example:
> -
> -u3phy: usb-phy@11c40000 {
> - compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
> - reg = <0 0x11c43000 0 0x0200>;
> - mediatek,src-ref-clk-mhz = <26>;
> - mediatek,src-coef = <17>;
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> -
> - u2port0: usb-phy@11c40000 {
> - reg = <0 0x11c40000 0 0x0400>;
> - clocks = <&clk48m>;
> - clock-names = "ref";
> - mediatek,eye-src = <4>;
> - #phy-cells = <1>;
> - };
> -
> - u3port0: usb-phy@11c43000 {
> - reg = <0 0x11c43400 0 0x0500>;
> - clocks = <&clk26m>;
> - clock-names = "ref";
> - mediatek,efuse-intr = <28>;
> - #phy-cells = <1>;
> - };
> -};
> --
> 2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-10-20 2:30 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-14 1:44 [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 2/8] dt-bindings: phy: convert phy-mtk-tphy.txt " Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 3/8] dt-bindings: phy: convert phy-mtk-ufs.txt " Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding " Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 5/8] dt-bindings: usb: convert mediatek, musb.txt " Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 6/8] dt-bindings: usb: convert mediatek, mtk-xhci.txt " Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 7/8] dt-bindings: usb: convert mediatek, mtu3.txt " Chunfeng Yun
2020-10-14 1:44 ` [PATCH v2 8/8] MAINTAINERS: update MediaTek PHY/USB entry Chunfeng Yun
[not found] <20201013085207.17749-1-chunfeng.yun@mediatek.com>
2020-10-16 17:00 ` [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema Rob Herring
2020-10-20 2:30 ` Chunfeng Yun
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