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From: Nancy.Lin <nancy.lin@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	"jason-jh . lin" <jason-jh.lin@mediatek.com>,
	"Nancy . Lin" <nancy.lin@mediatek.com>,
	Yongqiang Niu <yongqiang.niu@mediatek.com>,
	<dri-devel@lists.freedesktop.org>,
	<linux-mediatek@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<singo.chang@mediatek.com>, <srv_heupstream@mediatek.com>
Subject: [PATCH v4 03/17] dt-bindings: mediatek: add ethdr definition for mt8195
Date: Wed, 25 Aug 2021 18:05:17 +0800	[thread overview]
Message-ID: <20210825100531.5653-4-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20210825100531.5653-1-nancy.lin@mediatek.com>

Add vdosys1 ETHDR definition.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
 .../display/mediatek/mediatek,ethdr.yaml      | 144 ++++++++++++++++++
 1 file changed, 144 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..64d5349cdf8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek ethdr Device Tree Bindings
+
+maintainers:
+  - CK Hu <ck.hu@mediatek.com>
+  - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+  ETHDR is designed for HDR video and graphics conversion in the external display path.
+  It handles multiple HDR input types and performs tone mapping, color space/color
+  format conversion, and then combine different layers, output the required HDR or
+  SDR signal to the subsequent display path. This engine is composed of two video
+  frontends, two graphic frontends, one video backend and a mixer.
+
+properties:
+  compatible:
+    items:
+      - const: mediatek,mt8195-disp-ethdr
+  reg:
+    maxItems: 7
+  reg-names:
+    items:
+      - const: mixer
+      - const: vdo_fe0
+      - const: vdo_fe1
+      - const: gfx_fe0
+      - const: gfx_fe1
+      - const: vdo_be
+      - const: adl_ds
+  interrupts:
+    minItems: 1
+  iommus:
+    description: The compatible property is DMA function blocks.
+      Should point to the respective IOMMU block with master port as argument,
+      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+      details.
+    minItems: 1
+    maxItems: 2
+  clocks:
+    items:
+      - description: mixer clock
+      - description: video frontend 0 clock
+      - description: video frontend 1 clock
+      - description: graphic frontend 0 clock
+      - description: graphic frontend 1 clock
+      - description: video backend clock
+      - description: autodownload and menuload clock
+      - description: video frontend 0 async clock
+      - description: video frontend 1 async clock
+      - description: graphic frontend 0 async clock
+      - description: graphic frontend 1 async clock
+      - description: video backend async clock
+      - description: ethdr top clock
+  clock-names:
+    items:
+      - const: mixer
+      - const: vdo_fe0
+      - const: vdo_fe1
+      - const: gfx_fe0
+      - const: gfx_fe1
+      - const: vdo_be
+      - const: adl_ds
+      - const: vdo_fe0_async
+      - const: vdo_fe1_async
+      - const: gfx_fe0_async
+      - const: gfx_fe1_async
+      - const: vdo_be_async
+      - const: ethdr_top
+  power-domains:
+    maxItems: 1
+  resets:
+    maxItems: 5
+  mediatek,gce-client-reg:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: The register of display function block to be set by gce.
+      There are 4 arguments in this property, gce node, subsys id, offset and
+      register size. The subsys id is defined in the gce header of each chips
+      include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+      display function block.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+
+    disp_ethdr@1c114000 {
+            compatible = "mediatek,mt8195-disp-ethdr";
+            reg = <0 0x1c114000 0 0x1000>,
+                  <0 0x1c115000 0 0x1000>,
+                  <0 0x1c117000 0 0x1000>,
+                  <0 0x1c119000 0 0x1000>,
+                  <0 0x1c11A000 0 0x1000>,
+                  <0 0x1c11B000 0 0x1000>,
+                  <0 0x1c11C000 0 0x1000>;
+            reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+                        "vdo_be", "adl_ds";
+            mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+                                      <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+                                      <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+                                      <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+                                      <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+                                      <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+                                      <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+            clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+                     <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+                     <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+                     <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+                     <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+                     <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+                     <&vdosys1 CLK_VDO1_26M_SLOW>,
+                     <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+                     <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+                     <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+                     <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+                     <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+                     <&topckgen CLK_TOP_ETHDR_SEL>;
+            clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+                          "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+                          "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+                          "ethdr_top";
+            power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+            iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+                     <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+            interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+            resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+                     <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+                     <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+                     <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+                     <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
+    };
+
+...
-- 
2.18.0
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  parent reply	other threads:[~2021-08-25 10:22 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-25 10:05 [PATCH v4 00/17] Add MediaTek SoC DRM (vdosys1) support " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 01/17] dt-bindings: mediatek: add vdosys1 RDMA definition " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 02/17] dt-bindings: mediatek: add vdosys1 MERGE property " Nancy.Lin
2021-08-25 10:05 ` Nancy.Lin [this message]
2021-08-25 10:05 ` [PATCH v4 04/17] dt-bindings: mediatek: Add #reset-cells to mmsys system controller Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 05/17] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 06/17] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 07/17] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 08/17] soc: mediatek: add mtk-mmsys config API " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 09/17] soc: mediatek: add cmdq support of " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 10/17] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1 Nancy.Lin
2021-08-25 10:46   ` Philipp Zabel
2021-09-06  2:07     ` Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 11/17] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 12/17] drm/mediatek: add display MDP RDMA support for MT8195 Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 13/17] drm/mediatek: add display merge api " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 14/17] drm/mediatek: add ETHDR " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 15/17] drm/mediatek: add ovl_adaptor " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 16/17] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 17/17] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 Nancy.Lin

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