* [PATCH v1 0/6] drm/mediatek: Add mt8195 DisplayPort driver
@ 2021-09-06 19:35 Markus Schneider-Pargmann
2021-09-06 19:35 ` [PATCH v1 1/6] dt-bindings: mediatek,dpi: Add mt8195 dpintf Markus Schneider-Pargmann
` (5 more replies)
0 siblings, 6 replies; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-06 19:35 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel
Cc: Sam Ravnborg, dri-devel, linux-mediatek, linux-arm-kernel,
Markus Schneider-Pargmann
Hi everyone,
this series is built around the DisplayPort driver. The dpi/dpintf driver and
the added helper functions are required for the DisplayPort driver to work.
It is version 1 of the patch series following the RFC version:
https://lore.kernel.org/linux-mediatek/20210816192523.1739365-1-msp@baylibre.com/
Note: This patch series is currently tested on v5.10 and I am currently working
on testing it on v5.14.
The series is now based on these patch series and its dependencies:
- Add Mediatek Soc DRM (vdosys0) support for mt8195
https://lore.kernel.org/linux-mediatek/20210825144833.7757-1-jason-jh.lin@mediatek.com/
- Add MediaTek SoC DRM (vdosys1) support for mt8195
https://lore.kernel.org/linux-mediatek/20210825100531.5653-1-nancy.lin@mediatek.com/
Changes in v1:
- Added DP binding documentation.
- Addressed feedback from the RFC.
- General cleanups in DPI and DP drivers.
- See individual patches for details on the changes done.
Thanks in advance for any feedback and comments.
Best,
Markus
Markus Schneider-Pargmann (6):
dt-bindings: mediatek,dpi: Add mt8195 dpintf
dt-bindings: mediatek,dp: Add Display Port binding
drm/edid: Add cea_sad helpers for freq/length
video/hdmi: Add audio_infoframe packing for DP
drm/mediatek: dpi: Add dpintf support
drm/mediatek: Add mt8195 DisplayPort driver
.../display/mediatek/mediatek,dp.yaml | 89 +
.../display/mediatek/mediatek,dpi.yaml | 43 +-
drivers/gpu/drm/drm_edid.c | 57 +
drivers/gpu/drm/mediatek/Kconfig | 6 +
drivers/gpu/drm/mediatek/Makefile | 2 +
drivers/gpu/drm/mediatek/mtk_dp.c | 2881 +++++++++++++++++
drivers/gpu/drm/mediatek/mtk_dp_reg.h | 580 ++++
drivers/gpu/drm/mediatek/mtk_dpi.c | 248 +-
drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 12 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
drivers/video/hdmi.c | 87 +-
include/drm/drm_edid.h | 18 +-
include/linux/hdmi.h | 4 +
15 files changed, 3958 insertions(+), 77 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h
--
2.33.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v1 1/6] dt-bindings: mediatek,dpi: Add mt8195 dpintf
2021-09-06 19:35 [PATCH v1 0/6] drm/mediatek: Add mt8195 DisplayPort driver Markus Schneider-Pargmann
@ 2021-09-06 19:35 ` Markus Schneider-Pargmann
2021-09-06 20:14 ` Sam Ravnborg
2021-09-06 19:35 ` [PATCH v1 2/6] dt-bindings: mediatek,dp: Add Display Port binding Markus Schneider-Pargmann
` (4 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-06 19:35 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel
Cc: Sam Ravnborg, dri-devel, linux-mediatek, linux-arm-kernel,
Markus Schneider-Pargmann
DP_INTF is similar to the actual dpi. They differ in some points
regarding registers and what needs to be set but the function blocks
itself are similar in design.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
.../display/mediatek/mediatek,dpi.yaml | 43 ++++++++++++++++---
1 file changed, 37 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index dd2896a40ff0..1a158b719ce6 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: mediatek DPI Controller Device Tree Bindings
+title: mediatek DPI/DP_INTF Controller Device Tree Bindings
maintainers:
- CK Hu <ck.hu@mediatek.com>
@@ -13,7 +13,8 @@ maintainers:
description: |
The Mediatek DPI function block is a sink of the display subsystem and
provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
- output bus.
+ output bus. The Mediatek DP_INTF is a similar function block that is
+ connected to the (embedded) display port function block.
properties:
compatible:
@@ -23,6 +24,7 @@ properties:
- mediatek,mt8173-dpi
- mediatek,mt8183-dpi
- mediatek,mt8192-dpi
+ - mediatek,mt8195-dpintf
reg:
maxItems: 1
@@ -37,10 +39,11 @@ properties:
- description: DPI PLL
clock-names:
- items:
- - const: pixel
- - const: engine
- - const: pll
+ description:
+ For dpi clocks pixel, engine and pll are required. For dpintf pixel,
+ hf_fmm and hf_fdp are required.
+ minItems: 3
+ maxItems: 3
pinctrl-0: true
pinctrl-1: true
@@ -64,6 +67,34 @@ required:
- clock-names
- port
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8195-dpintf
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: pixel
+ - const: hf_fmm
+ - const: hf_fdp
+ else:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: pixel
+ - const: engine
+ - const: pll
+
additionalProperties: false
examples:
--
2.33.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v1 2/6] dt-bindings: mediatek,dp: Add Display Port binding
2021-09-06 19:35 [PATCH v1 0/6] drm/mediatek: Add mt8195 DisplayPort driver Markus Schneider-Pargmann
2021-09-06 19:35 ` [PATCH v1 1/6] dt-bindings: mediatek,dpi: Add mt8195 dpintf Markus Schneider-Pargmann
@ 2021-09-06 19:35 ` Markus Schneider-Pargmann
2021-09-06 19:35 ` [PATCH v1 3/6] drm/edid: Add cea_sad helpers for freq/length Markus Schneider-Pargmann
` (3 subsequent siblings)
5 siblings, 0 replies; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-06 19:35 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel
Cc: Sam Ravnborg, dri-devel, linux-mediatek, linux-arm-kernel,
Markus Schneider-Pargmann
This controller is present on different mediatek hardware. Currently
mt8195 and mt8395 have this controller without a functional difference,
so only one compatible is added.
The controller can be in two forms, for a normal display port and for
embedded display port.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
Notes:
I added the mediatek maintainers in the list of maintainers as I wasn't sure
whom I should put there. Please let me know if I am supposed to add my mail
there.
.../display/mediatek/mediatek,dp.yaml | 89 +++++++++++++++++++
1 file changed, 89 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
new file mode 100644
index 000000000000..f7a35962c23b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Display Port Controller
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Jitao shi <jitao.shi@mediatek.com>
+
+description: |
+ Device tree bindings for the Mediatek (embedded) Display Port controller
+ present on some Mediatek SoCs.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-edp_tx
+ - mediatek,mt8195-dp_tx
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: faxi clock
+
+ clock-names:
+ items:
+ - const: faxi
+
+ power-domains:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Input endpoint of the controller, usually dp_intf
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output endpoint of the controller
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/mt8195-power.h>
+ dp_tx: edp_tx@1c500000 {
+ compatible = "mediatek,mt8195-edp_tx";
+ reg = <0 0x1c500000 0 0x8000>;
+ interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_pin>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ edp_in: endpoint {
+ remote-endpoint = <&dp_intf0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ edp_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
--
2.33.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v1 3/6] drm/edid: Add cea_sad helpers for freq/length
2021-09-06 19:35 [PATCH v1 0/6] drm/mediatek: Add mt8195 DisplayPort driver Markus Schneider-Pargmann
2021-09-06 19:35 ` [PATCH v1 1/6] dt-bindings: mediatek,dpi: Add mt8195 dpintf Markus Schneider-Pargmann
2021-09-06 19:35 ` [PATCH v1 2/6] dt-bindings: mediatek,dp: Add Display Port binding Markus Schneider-Pargmann
@ 2021-09-06 19:35 ` Markus Schneider-Pargmann
2021-09-06 20:19 ` Sam Ravnborg
2021-09-06 19:35 ` [PATCH v1 4/6] video/hdmi: Add audio_infoframe packing for DP Markus Schneider-Pargmann
` (2 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-06 19:35 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel
Cc: Sam Ravnborg, dri-devel, linux-mediatek, linux-arm-kernel,
Markus Schneider-Pargmann
This patch adds two helper functions that extract the frequency and word
length from a struct cea_sad.
For these helper functions new defines are added that help translate the
'freq' and 'byte2' fields into real numbers.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/gpu/drm/drm_edid.c | 57 ++++++++++++++++++++++++++++++++++++++
include/drm/drm_edid.h | 18 ++++++++++--
2 files changed, 73 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 81d5f2524246..2389d34ce10e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4666,6 +4666,63 @@ int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
}
EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
+/**
+ * drm_cea_sad_get_sample_rate - Extract the sample rate from cea_sad
+ * @sad: Pointer to the cea_sad struct
+ *
+ * Extracts the cea_sad frequency field and returns the sample rate in Hz.
+ *
+ * Return: Sample rate in Hz or a negative errno if parsing failed.
+ */
+int drm_cea_sad_get_sample_rate(struct cea_sad *sad)
+{
+ switch (sad->freq) {
+ case CEA_SAD_FREQ_32KHZ:
+ return 32000;
+ case CEA_SAD_FREQ_44KHZ:
+ return 44100;
+ case CEA_SAD_FREQ_48KHZ:
+ return 48000;
+ case CEA_SAD_FREQ_88KHZ:
+ return 88200;
+ case CEA_SAD_FREQ_96KHZ:
+ return 96000;
+ case CEA_SAD_FREQ_176KHZ:
+ return 176400;
+ case CEA_SAD_FREQ_192KHZ:
+ return 192000;
+ default:
+ return -EINVAL;
+ }
+}
+EXPORT_SYMBOL(drm_cea_sad_get_sample_rate);
+
+/**
+ * drm_cea_sad_get_uncompressed_word_length - Extract word length
+ * @sad: Pointer to the cea_sad struct
+ *
+ * Extracts the cea_sad byte2 field and returns the word length for an
+ * uncompressed stream.
+ *
+ * Note: This function may only be called for uncompressed audio.
+ *
+ * Return: Word length in bits or a negative errno if parsing failed.
+ */
+int drm_cea_sad_get_uncompressed_word_length(struct cea_sad *sad)
+{
+ switch (sad->byte2) {
+ case CEA_SAD_UNCOMPRESSED_WORD_16BIT:
+ return 16;
+ case CEA_SAD_UNCOMPRESSED_WORD_20BIT:
+ return 20;
+ case CEA_SAD_UNCOMPRESSED_WORD_24BIT:
+ return 24;
+ default:
+ return -EINVAL;
+ }
+}
+EXPORT_SYMBOL(drm_cea_sad_get_uncompressed_word_length);
+
/**
* drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
* @connector: connector associated with the HDMI/DP sink
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 759328a5eeb2..bed091a749ef 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -361,12 +361,24 @@ struct edid {
/* Short Audio Descriptor */
struct cea_sad {
- u8 format;
+ u8 format; /* See HDMI_AUDIO_CODING_TYPE_* */
u8 channels; /* max number of channels - 1 */
- u8 freq;
+ u8 freq; /* See CEA_SAD_FREQ_* */
u8 byte2; /* meaning depends on format */
};
+#define CEA_SAD_FREQ_32KHZ BIT(0)
+#define CEA_SAD_FREQ_44KHZ BIT(1)
+#define CEA_SAD_FREQ_48KHZ BIT(2)
+#define CEA_SAD_FREQ_88KHZ BIT(3)
+#define CEA_SAD_FREQ_96KHZ BIT(4)
+#define CEA_SAD_FREQ_176KHZ BIT(5)
+#define CEA_SAD_FREQ_192KHZ BIT(6)
+
+#define CEA_SAD_UNCOMPRESSED_WORD_16BIT BIT(0)
+#define CEA_SAD_UNCOMPRESSED_WORD_20BIT BIT(1)
+#define CEA_SAD_UNCOMPRESSED_WORD_24BIT BIT(2)
+
struct drm_encoder;
struct drm_connector;
struct drm_connector_state;
@@ -374,6 +386,8 @@ struct drm_display_mode;
int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);
+int drm_cea_sad_get_sample_rate(struct cea_sad *sad);
+int drm_cea_sad_get_uncompressed_word_length(struct cea_sad *sad);
int drm_av_sync_delay(struct drm_connector *connector,
const struct drm_display_mode *mode);
--
2.33.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v1 4/6] video/hdmi: Add audio_infoframe packing for DP
2021-09-06 19:35 [PATCH v1 0/6] drm/mediatek: Add mt8195 DisplayPort driver Markus Schneider-Pargmann
` (2 preceding siblings ...)
2021-09-06 19:35 ` [PATCH v1 3/6] drm/edid: Add cea_sad helpers for freq/length Markus Schneider-Pargmann
@ 2021-09-06 19:35 ` Markus Schneider-Pargmann
2021-09-06 20:30 ` Sam Ravnborg
2021-09-06 19:35 ` [PATCH v1 5/6] drm/mediatek: dpi: Add dpintf support Markus Schneider-Pargmann
2021-09-06 19:35 ` [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver Markus Schneider-Pargmann
5 siblings, 1 reply; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-06 19:35 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel
Cc: Sam Ravnborg, dri-devel, linux-mediatek, linux-arm-kernel,
Markus Schneider-Pargmann
Similar to HDMI, DP uses audio infoframes as well which are structured
very similar to the HDMI ones.
This patch adds a helper function to pack the HDMI audio infoframe for
DP, called hdmi_audio_infoframe_pack_for_dp().
hdmi_audio_infoframe_pack_only() is split into two parts. One of them
packs the payload only and can be used for HDMI and DP.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
drivers/video/hdmi.c | 87 +++++++++++++++++++++++++++++++++++---------
include/linux/hdmi.h | 4 ++
2 files changed, 73 insertions(+), 18 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 947be761dfa4..59c4341549e4 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -387,6 +387,28 @@ int hdmi_audio_infoframe_check(struct hdmi_audio_infoframe *frame)
}
EXPORT_SYMBOL(hdmi_audio_infoframe_check);
+static void
+hdmi_audio_infoframe_pack_payload(const struct hdmi_audio_infoframe *frame,
+ u8 *buffer)
+{
+ u8 channels;
+
+ if (frame->channels >= 2)
+ channels = frame->channels - 1;
+ else
+ channels = 0;
+
+ buffer[0] = ((frame->coding_type & 0xf) << 4) | (channels & 0x7);
+ buffer[1] = ((frame->sample_frequency & 0x7) << 2) |
+ (frame->sample_size & 0x3);
+ buffer[2] = frame->coding_type_ext & 0x1f;
+ buffer[3] = frame->channel_allocation;
+ buffer[4] = (frame->level_shift_value & 0xf) << 3;
+
+ if (frame->downmix_inhibit)
+ buffer[4] |= BIT(7);
+}
+
/**
* hdmi_audio_infoframe_pack_only() - write HDMI audio infoframe to binary buffer
* @frame: HDMI audio infoframe
@@ -404,7 +426,6 @@ EXPORT_SYMBOL(hdmi_audio_infoframe_check);
ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *frame,
void *buffer, size_t size)
{
- unsigned char channels;
u8 *ptr = buffer;
size_t length;
int ret;
@@ -420,28 +441,13 @@ ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *frame,
memset(buffer, 0, size);
- if (frame->channels >= 2)
- channels = frame->channels - 1;
- else
- channels = 0;
-
ptr[0] = frame->type;
ptr[1] = frame->version;
ptr[2] = frame->length;
ptr[3] = 0; /* checksum */
- /* start infoframe payload */
- ptr += HDMI_INFOFRAME_HEADER_SIZE;
-
- ptr[0] = ((frame->coding_type & 0xf) << 4) | (channels & 0x7);
- ptr[1] = ((frame->sample_frequency & 0x7) << 2) |
- (frame->sample_size & 0x3);
- ptr[2] = frame->coding_type_ext & 0x1f;
- ptr[3] = frame->channel_allocation;
- ptr[4] = (frame->level_shift_value & 0xf) << 3;
-
- if (frame->downmix_inhibit)
- ptr[4] |= BIT(7);
+ hdmi_audio_infoframe_pack_payload(frame,
+ ptr + HDMI_INFOFRAME_HEADER_SIZE);
hdmi_infoframe_set_checksum(buffer, length);
@@ -479,6 +485,51 @@ ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_infoframe *frame,
}
EXPORT_SYMBOL(hdmi_audio_infoframe_pack);
+/**
+ * hdmi_audio_infoframe_pack_for_dp - Pack a HDMI Audio infoframe for
+ * displayport
+ *
+ * @frame HDMI Audio infoframe
+ * @header Header buffer to be used
+ * @header_size Size of header buffer
+ * @data Data buffer to be used
+ * @data_size Size of data buffer
+ * @dp_version Display Port version to be encoded in the header
+ *
+ * Packs a HDMI Audio Infoframe to be sent over Display Port. This function
+ * fills both header and data buffer with the required data.
+ *
+ * Return: Number of total written bytes or a negative errno on failure.
+ */
+ssize_t hdmi_audio_infoframe_pack_for_dp(struct hdmi_audio_infoframe *frame,
+ void *header, size_t header_size,
+ void *data, size_t data_size,
+ u8 dp_version)
+{
+ int ret;
+ u8 *hdr_ptr = header;
+
+ ret = hdmi_audio_infoframe_check(frame);
+ if (ret)
+ return ret;
+
+ if (header_size < 4 || data_size < frame->length)
+ return -ENOSPC;
+
+ memset(header, 0, header_size);
+ memset(data, 0, data_size);
+
+ // Secondary-data packet header
+ hdr_ptr[1] = frame->type;
+ hdr_ptr[2] = 0x1B; // As documented by DP spec for Secondary-data Packets
+ hdr_ptr[3] = (dp_version & 0x3f) << 2;
+
+ hdmi_audio_infoframe_pack_payload(frame, data);
+
+ return frame->length + 4;
+}
+EXPORT_SYMBOL(hdmi_audio_infoframe_pack_for_dp);
+
/**
* hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe
* @frame: HDMI vendor infoframe
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index c8ec982ff498..f576a0b08c85 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -334,6 +334,10 @@ struct hdmi_audio_infoframe {
int hdmi_audio_infoframe_init(struct hdmi_audio_infoframe *frame);
ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_infoframe *frame,
void *buffer, size_t size);
+ssize_t hdmi_audio_infoframe_pack_for_dp(struct hdmi_audio_infoframe *frame,
+ void *header, size_t header_size,
+ void *data, size_t data_size,
+ u8 dp_version);
ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *frame,
void *buffer, size_t size);
int hdmi_audio_infoframe_check(struct hdmi_audio_infoframe *frame);
--
2.33.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v1 5/6] drm/mediatek: dpi: Add dpintf support
2021-09-06 19:35 [PATCH v1 0/6] drm/mediatek: Add mt8195 DisplayPort driver Markus Schneider-Pargmann
` (3 preceding siblings ...)
2021-09-06 19:35 ` [PATCH v1 4/6] video/hdmi: Add audio_infoframe packing for DP Markus Schneider-Pargmann
@ 2021-09-06 19:35 ` Markus Schneider-Pargmann
2021-09-06 19:35 ` [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver Markus Schneider-Pargmann
5 siblings, 0 replies; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-06 19:35 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel
Cc: Sam Ravnborg, dri-devel, linux-mediatek, linux-arm-kernel,
Markus Schneider-Pargmann
dpintf is the displayport interface hardware unit. This unit is similar
to dpi and can reuse most of the code.
This patch adds support for mt8195-dpintf to this dpi driver. Main
differences are:
- Some features/functional components are not available for dpintf
which are now excluded from code execution once is_dpintf is set
- dpintf can and needs to choose between different clockdividers based
on the clockspeed. This is done by choosing a different clock parent.
- There are two additional clocks that need to be managed. These are
only set for dpintf and will be set to NULL if not supplied. The
clk_* calls handle these as normal clocks then.
- Some register contents differ slightly between the two components. To
work around this I added register bits/masks with a DPINTF_ prefix
and use them where different.
Based on a separate driver for dpintf created by
Jason-JH.Lin <jason-jh.lin@mediatek.com>.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
Notes:
Changes RFC -> v1:
- Remove setting parents and fully rely on the clock tree instead which already
models a mux at the important place.
- Integrated mtk_dpi dpintf changes into the mediatek drm driver.
drivers/gpu/drm/mediatek/mtk_dpi.c | 248 ++++++++++++++++----
drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 12 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
5 files changed, 217 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index e94738fe4db8..986c7f72483f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -71,6 +71,8 @@ struct mtk_dpi {
void __iomem *regs;
struct device *dev;
struct clk *engine_clk;
+ struct clk *hf_fmm_clk;
+ struct clk *hf_fdp_clk;
struct clk *pixel_clk;
struct clk *tvd_clk;
int irq;
@@ -125,6 +127,7 @@ struct mtk_dpi_conf {
bool edge_sel_en;
const u32 *output_fmts;
u32 num_output_fmts;
+ bool is_dpintf;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -153,30 +156,52 @@ static void mtk_dpi_disable(struct mtk_dpi *dpi)
static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
struct mtk_dpi_sync_param *sync)
{
- mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH,
- sync->sync_width << HPW, HPW_MASK);
- mtk_dpi_mask(dpi, DPI_TGEN_HPORCH,
- sync->back_porch << HBP, HBP_MASK);
- mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
- HFP_MASK);
+ if (dpi->conf->is_dpintf) {
+ mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH,
+ sync->sync_width << HPW, DPINTF_HPW_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH,
+ sync->back_porch << HBP, DPINTF_HBP_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
+ DPINTF_HFP_MASK);
+ } else {
+ mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH,
+ sync->sync_width << HPW, HPW_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH,
+ sync->back_porch << HBP, HBP_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
+ HFP_MASK);
+ }
}
static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
struct mtk_dpi_sync_param *sync,
u32 width_addr, u32 porch_addr)
{
- mtk_dpi_mask(dpi, width_addr,
- sync->sync_width << VSYNC_WIDTH_SHIFT,
- VSYNC_WIDTH_MASK);
mtk_dpi_mask(dpi, width_addr,
sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
VSYNC_HALF_LINE_MASK);
- mtk_dpi_mask(dpi, porch_addr,
- sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
- VSYNC_BACK_PORCH_MASK);
- mtk_dpi_mask(dpi, porch_addr,
- sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
- VSYNC_FRONT_PORCH_MASK);
+
+ if (dpi->conf->is_dpintf) {
+ mtk_dpi_mask(dpi, width_addr,
+ sync->sync_width << VSYNC_WIDTH_SHIFT,
+ DPINTF_VSYNC_WIDTH_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+ sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
+ DPINTF_VSYNC_BACK_PORCH_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+ sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
+ DPINTF_VSYNC_FRONT_PORCH_MASK);
+ } else {
+ mtk_dpi_mask(dpi, width_addr,
+ sync->sync_width << VSYNC_WIDTH_SHIFT,
+ VSYNC_WIDTH_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+ sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
+ VSYNC_BACK_PORCH_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+ sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
+ VSYNC_FRONT_PORCH_MASK);
+ }
}
static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi,
@@ -210,13 +235,20 @@ static void mtk_dpi_config_pol(struct mtk_dpi *dpi,
struct mtk_dpi_polarities *dpi_pol)
{
unsigned int pol;
+ unsigned int mask;
- pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL) |
- (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL) |
- (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) |
+ mask = HSYNC_POL | VSYNC_POL;
+ pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) |
(dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL);
- mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol,
- CK_POL | DE_POL | HSYNC_POL | VSYNC_POL);
+ if (!dpi->conf->is_dpintf) {
+ mask |= CK_POL | DE_POL;
+ pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ?
+ 0 : CK_POL) |
+ (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ?
+ 0 : DE_POL);
+ }
+
+ mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask);
}
static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d)
@@ -231,8 +263,13 @@ static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter)
static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height)
{
- mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK);
- mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK);
+ if (dpi->conf->is_dpintf) {
+ mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, DPINTF_HSIZE_MASK);
+ mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, DPINTF_VSIZE_MASK);
+ } else {
+ mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK);
+ mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK);
+ }
}
static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi,
@@ -332,12 +369,21 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi,
break;
}
- mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK);
+ if (dpi->conf->is_dpintf)
+ mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << DPINTF_CH_SWAP,
+ DPINTF_CH_SWAP_MASK);
+ else
+ mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP,
+ CH_SWAP_MASK);
}
static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable)
{
- mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN);
+ if (dpi->conf->is_dpintf)
+ mtk_dpi_mask(dpi, DPI_CON, enable ? DPINTF_YUV422_EN : 0,
+ DPINTF_YUV422_EN);
+ else
+ mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN);
}
static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable)
@@ -367,19 +413,25 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_444) ||
(format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) {
mtk_dpi_config_yuv422_enable(dpi, false);
- mtk_dpi_config_csc_enable(dpi, true);
- mtk_dpi_config_swap_input(dpi, false);
+ if (!dpi->conf->is_dpintf) {
+ mtk_dpi_config_csc_enable(dpi, true);
+ mtk_dpi_config_swap_input(dpi, false);
+ }
mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR);
} else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) ||
(format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) {
mtk_dpi_config_yuv422_enable(dpi, true);
- mtk_dpi_config_csc_enable(dpi, true);
- mtk_dpi_config_swap_input(dpi, true);
+ if (!dpi->conf->is_dpintf) {
+ mtk_dpi_config_csc_enable(dpi, true);
+ mtk_dpi_config_swap_input(dpi, true);
+ }
mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
} else {
mtk_dpi_config_yuv422_enable(dpi, false);
- mtk_dpi_config_csc_enable(dpi, false);
- mtk_dpi_config_swap_input(dpi, false);
+ if (!dpi->conf->is_dpintf) {
+ mtk_dpi_config_csc_enable(dpi, false);
+ mtk_dpi_config_swap_input(dpi, false);
+ }
mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
}
}
@@ -410,6 +462,8 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)
pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
mtk_dpi_disable(dpi);
+ clk_disable_unprepare(dpi->hf_fdp_clk);
+ clk_disable_unprepare(dpi->hf_fmm_clk);
clk_disable_unprepare(dpi->pixel_clk);
clk_disable_unprepare(dpi->engine_clk);
}
@@ -433,12 +487,28 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
goto err_pixel;
}
+ ret = clk_prepare_enable(dpi->hf_fmm_clk);
+ if (ret) {
+ dev_err(dpi->dev, "Failed to enable hf_fmm clock: %d\n", ret);
+ goto err_hf_fmm;
+ }
+
+ ret = clk_prepare_enable(dpi->hf_fdp_clk);
+ if (ret) {
+ dev_err(dpi->dev, "Failed to enable hf_fdp clock: %d\n", ret);
+ goto err_hf_fdp;
+ }
+
if (dpi->pinctrl && dpi->pins_dpi)
pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
mtk_dpi_enable(dpi);
return 0;
+err_hf_fdp:
+ clk_disable_unprepare(dpi->hf_fmm_clk);
+err_hf_fmm:
+ clk_disable_unprepare(dpi->pixel_clk);
err_pixel:
clk_disable_unprepare(dpi->engine_clk);
err_refcount:
@@ -472,22 +542,30 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
pll_rate = clk_get_rate(dpi->tvd_clk);
vm.pixelclock = pll_rate / factor;
- if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
- (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
+ if (dpi->conf->is_dpintf)
+ clk_set_rate(dpi->pixel_clk, vm.pixelclock / 4);
+ else if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
+ (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
else
clk_set_rate(dpi->pixel_clk, vm.pixelclock);
-
vm.pixelclock = clk_get_rate(dpi->pixel_clk);
dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
pll_rate, vm.pixelclock);
- limit.c_bottom = 0x0010;
- limit.c_top = 0x0FE0;
- limit.y_bottom = 0x0010;
- limit.y_top = 0x0FE0;
+ if (dpi->conf->is_dpintf) {
+ limit.c_bottom = 0x0000;
+ limit.c_top = 0xFFF;
+ limit.y_bottom = 0x0000;
+ limit.y_top = 0xFFF;
+ } else {
+ limit.c_bottom = 0x0010;
+ limit.c_top = 0x0FE0;
+ limit.y_bottom = 0x0010;
+ limit.y_top = 0x0FE0;
+ }
dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
@@ -495,9 +573,15 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ?
MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
- hsync.sync_width = vm.hsync_len;
- hsync.back_porch = vm.hback_porch;
- hsync.front_porch = vm.hfront_porch;
+ if (dpi->conf->is_dpintf) {
+ hsync.sync_width = vm.hsync_len / 4;
+ hsync.back_porch = vm.hback_porch / 4;
+ hsync.front_porch = vm.hfront_porch / 4;
+ } else {
+ hsync.sync_width = vm.hsync_len;
+ hsync.back_porch = vm.hback_porch;
+ hsync.front_porch = vm.hfront_porch;
+ }
hsync.shift_half_line = false;
vsync_lodd.sync_width = vm.vsync_len;
vsync_lodd.back_porch = vm.vback_porch;
@@ -539,11 +623,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
mtk_dpi_config_channel_limit(dpi, &limit);
mtk_dpi_config_bit_num(dpi, dpi->bit_num);
mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
- mtk_dpi_config_yc_map(dpi, dpi->yc_map);
mtk_dpi_config_color_format(dpi, dpi->color_format);
- mtk_dpi_config_2n_h_fre(dpi);
- mtk_dpi_dual_edge(dpi);
- mtk_dpi_config_disable_edge(dpi);
+ if (dpi->conf->is_dpintf) {
+ mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,
+ DPINTF_INPUT_2P_EN);
+ } else {
+ mtk_dpi_config_yc_map(dpi, dpi->yc_map);
+ mtk_dpi_config_2n_h_fre(dpi);
+ mtk_dpi_dual_edge(dpi);
+ mtk_dpi_config_disable_edge(dpi);
+ }
mtk_dpi_sw_reset(dpi, false);
return 0;
@@ -687,6 +776,17 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
.atomic_reset = drm_atomic_helper_bridge_reset,
};
+static const struct drm_bridge_funcs mtk_dpintf_bridge_funcs = {
+ .attach = mtk_dpi_bridge_attach,
+ .mode_set = mtk_dpi_bridge_mode_set,
+ .disable = mtk_dpi_bridge_disable,
+ .enable = mtk_dpi_bridge_enable,
+ .atomic_check = mtk_dpi_bridge_atomic_check,
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+};
+
void mtk_dpi_start(struct device *dev)
{
struct mtk_dpi *dpi = dev_get_drvdata(dev);
@@ -783,6 +883,16 @@ static unsigned int mt8183_calculate_factor(int clock)
return 2;
}
+static unsigned int mt8195_dpintf_calculate_factor(int clock)
+{
+ if (clock < 70000)
+ return 4;
+ else if (clock < 200000)
+ return 2;
+ else
+ return 1;
+}
+
static const u32 mt8173_output_fmts[] = {
MEDIA_BUS_FMT_RGB888_1X24,
};
@@ -798,6 +908,7 @@ static const struct mtk_dpi_conf mt8173_conf = {
.max_clock_khz = 300000,
.output_fmts = mt8173_output_fmts,
.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
+ .is_dpintf = false,
};
static const struct mtk_dpi_conf mt2701_conf = {
@@ -807,6 +918,7 @@ static const struct mtk_dpi_conf mt2701_conf = {
.max_clock_khz = 150000,
.output_fmts = mt8173_output_fmts,
.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
+ .is_dpintf = false,
};
static const struct mtk_dpi_conf mt8183_conf = {
@@ -815,6 +927,7 @@ static const struct mtk_dpi_conf mt8183_conf = {
.max_clock_khz = 100000,
.output_fmts = mt8183_output_fmts,
.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
+ .is_dpintf = false,
};
static const struct mtk_dpi_conf mt8192_conf = {
@@ -823,6 +936,12 @@ static const struct mtk_dpi_conf mt8192_conf = {
.max_clock_khz = 150000,
.output_fmts = mt8173_output_fmts,
.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
+ .is_dpintf = false,
+};
+
+static const struct mtk_dpi_conf mt8195_dpintf_conf = {
+ .cal_factor = mt8195_dpintf_calculate_factor,
+ .is_dpintf = true,
};
static int mtk_dpi_probe(struct platform_device *pdev)
@@ -868,13 +987,16 @@ static int mtk_dpi_probe(struct platform_device *pdev)
return ret;
}
- dpi->engine_clk = devm_clk_get(dev, "engine");
- if (IS_ERR(dpi->engine_clk)) {
- ret = PTR_ERR(dpi->engine_clk);
- if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get engine clock: %d\n", ret);
+ if (!dpi->conf->is_dpintf) {
+ dpi->engine_clk = devm_clk_get(dev, "engine");
+ if (IS_ERR(dpi->engine_clk)) {
+ ret = PTR_ERR(dpi->engine_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to get engine clock: %d\n",
+ ret);
- return ret;
+ return ret;
+ }
}
dpi->pixel_clk = devm_clk_get(dev, "pixel");
@@ -895,6 +1017,24 @@ static int mtk_dpi_probe(struct platform_device *pdev)
return ret;
}
+ dpi->hf_fmm_clk = devm_clk_get_optional(dev, "hf_fmm");
+ if (IS_ERR(dpi->hf_fmm_clk)) {
+ ret = PTR_ERR(dpi->hf_fmm_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to get hf_fmm clock: %d\n", ret);
+
+ return ret;
+ }
+
+ dpi->hf_fdp_clk = devm_clk_get_optional(dev, "hf_fdp");
+ if (IS_ERR(dpi->hf_fdp_clk)) {
+ ret = PTR_ERR(dpi->hf_fdp_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to get hf_fdp clock: %d\n", ret);
+
+ return ret;
+ }
+
dpi->irq = platform_get_irq(pdev, 0);
if (dpi->irq <= 0)
return -EINVAL;
@@ -908,7 +1048,10 @@ static int mtk_dpi_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, dpi);
- dpi->bridge.funcs = &mtk_dpi_bridge_funcs;
+ if (dpi->conf->is_dpintf)
+ dpi->bridge.funcs = &mtk_dpintf_bridge_funcs;
+ else
+ dpi->bridge.funcs = &mtk_dpi_bridge_funcs;
dpi->bridge.of_node = dev->of_node;
dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
@@ -947,6 +1090,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8192-dpi",
.data = &mt8192_conf,
},
+ { .compatible = "mediatek,mt8195-dpintf",
+ .data = &mt8195_dpintf_conf,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 3a02fabe1662..72efe6ee2584 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -40,10 +40,14 @@
#define FAKE_DE_LEVEN BIT(21)
#define FAKE_DE_RODD BIT(22)
#define FAKE_DE_REVEN BIT(23)
+#define DPINTF_YUV422_EN BIT(24)
+#define DPINTF_INPUT_2P_EN BIT(29)
#define DPI_OUTPUT_SETTING 0x14
#define CH_SWAP 0
+#define DPINTF_CH_SWAP BIT(1)
#define CH_SWAP_MASK (0x7 << 0)
+#define DPINTF_CH_SWAP_MASK (0x7 << 1)
#define SWAP_RGB 0x00
#define SWAP_GBR 0x01
#define SWAP_BRG 0x02
@@ -80,8 +84,10 @@
#define DPI_SIZE 0x18
#define HSIZE 0
#define HSIZE_MASK (0x1FFF << 0)
+#define DPINTF_HSIZE_MASK (0xFFFF << 0)
#define VSIZE 16
#define VSIZE_MASK (0x1FFF << 16)
+#define DPINTF_VSIZE_MASK (0xFFFF << 16)
#define DPI_DDR_SETTING 0x1C
#define DDR_EN BIT(0)
@@ -93,24 +99,30 @@
#define DPI_TGEN_HWIDTH 0x20
#define HPW 0
#define HPW_MASK (0xFFF << 0)
+#define DPINTF_HPW_MASK (0xFFFF << 0)
#define DPI_TGEN_HPORCH 0x24
#define HBP 0
#define HBP_MASK (0xFFF << 0)
+#define DPINTF_HBP_MASK (0xFFFF << 0)
#define HFP 16
#define HFP_MASK (0xFFF << 16)
+#define DPINTF_HFP_MASK (0xFFFF << 16)
#define DPI_TGEN_VWIDTH 0x28
#define DPI_TGEN_VPORCH 0x2C
#define VSYNC_WIDTH_SHIFT 0
#define VSYNC_WIDTH_MASK (0xFFF << 0)
+#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0)
#define VSYNC_HALF_LINE_SHIFT 16
#define VSYNC_HALF_LINE_MASK BIT(16)
#define VSYNC_BACK_PORCH_SHIFT 0
#define VSYNC_BACK_PORCH_MASK (0xFFF << 0)
+#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0)
#define VSYNC_FRONT_PORCH_SHIFT 16
#define VSYNC_FRONT_PORCH_MASK (0xFFF << 16)
+#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16)
#define DPI_BG_HCNTL 0x30
#define BG_RIGHT (0x1FFF << 0)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 900f9c9f61f3..871800b4b6ca 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -376,6 +376,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_UFOE] = "ufoe",
[MTK_DISP_WDMA] = "wdma",
[MTK_DPI] = "dpi",
+ [MTK_DP_INTF] = "dp-intf",
[MTK_DSI] = "dsi",
};
@@ -395,6 +396,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
+ [DDP_COMPONENT_DP_INTF0]= { MTK_DP_INTF, 0, &ddp_dpi },
+ [DDP_COMPONENT_DP_INTF1]= { MTK_DP_INTF, 1, &ddp_dpi },
[DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
[DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
@@ -547,6 +550,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
+ type == MTK_DP_INTF ||
type == MTK_DSI)
return 0;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index a8e5e770ce2f..9f47e883cc91 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_UFOE,
MTK_DISP_WDMA,
MTK_DPI,
+ MTK_DP_INTF,
MTK_DSI,
MTK_DDP_COMP_TYPE_MAX,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index e831175a66f3..a8c6b9708e34 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -728,6 +728,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt8183-dpi",
.data = (void *)MTK_DPI },
+ { .compatible = "mediatek,mt8195-dpintf",
+ .data = (void *)MTK_DP_INTF },
{ .compatible = "mediatek,mt2701-dsi",
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8173-dsi",
@@ -827,6 +829,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_OVL_ADAPTOR ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
+ comp_type == MTK_DP_INTF ||
comp_type == MTK_DSI) {
dev_info(dev, "Adding component match for %pOF\n",
node);
--
2.33.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver
2021-09-06 19:35 [PATCH v1 0/6] drm/mediatek: Add mt8195 DisplayPort driver Markus Schneider-Pargmann
` (4 preceding siblings ...)
2021-09-06 19:35 ` [PATCH v1 5/6] drm/mediatek: dpi: Add dpintf support Markus Schneider-Pargmann
@ 2021-09-06 19:35 ` Markus Schneider-Pargmann
2021-09-06 20:39 ` Sam Ravnborg
` (2 more replies)
5 siblings, 3 replies; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-06 19:35 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel
Cc: Sam Ravnborg, dri-devel, linux-mediatek, linux-arm-kernel,
Markus Schneider-Pargmann
This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
It supports both functional units on the mt8195, the embedded
DisplayPort as well as the external DisplayPort units. It offers
hot-plug-detection, audio up to 8 channels, and DisplayPort 1.4 with up
to 4 lanes.
This driver is based on an initial version by
Jason-JH.Lin <jason-jh.lin@mediatek.com>.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
Notes:
Changes RFC -> v1:
- Removed unused register definitions.
- Replaced workqueue with threaded irq.
- Removed connector code.
- Move to atomic_* drm functions.
- General cleanups of the code.
- Remove unused select GENERIC_PHY.
drivers/gpu/drm/mediatek/Kconfig | 6 +
drivers/gpu/drm/mediatek/Makefile | 2 +
drivers/gpu/drm/mediatek/mtk_dp.c | 2881 +++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_dp_reg.h | 580 +++++
4 files changed, 3469 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h
diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
index 2976d21e9a34..6d6a5b5872f2 100644
--- a/drivers/gpu/drm/mediatek/Kconfig
+++ b/drivers/gpu/drm/mediatek/Kconfig
@@ -28,3 +28,9 @@ config DRM_MEDIATEK_HDMI
select PHY_MTK_HDMI
help
DRM/KMS HDMI driver for Mediatek SoCs
+
+config MTK_DPTX_SUPPORT
+ tristate "DRM DPTX Support for Mediatek SoCs"
+ depends on DRM_MEDIATEK
+ help
+ DRM/KMS Display Port driver for Mediatek SoCs.
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 3abd27d7c91d..ba6e2228bbf8 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -25,3 +25,5 @@ mediatek-drm-hdmi-objs := mtk_cec.o \
mtk_hdmi_ddc.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
+
+obj-$(CONFIG_MTK_DPTX_SUPPORT) += mtk_dp.o
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
new file mode 100644
index 000000000000..1bd07c8d2f69
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -0,0 +1,2881 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Copyright (c) 2021 BayLibre
+ */
+
+#include <linux/arm-smccc.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/extcon.h>
+#include <linux/extcon-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/kthread.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/of_graph.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+#include <sound/hdmi-codec.h>
+#include <video/videomode.h>
+
+#include "mtk_dp_reg.h"
+
+#define MTK_DP_AUX_WAIT_REPLY_COUNT 20000
+#define MTK_DP_CHECK_SINK_CAP_TIMEOUT_COUNT 3
+
+#define MTK_DP_MAX_LANES 4
+#define MTK_DP_MAX_LINK_RATE MTK_DP_LINKRATE_HBR3
+
+#define MTK_DP_TBC_BUF_READ_START_ADDR 0x08
+
+#define MTK_DP_TRAIN_RETRY_LIMIT 8
+#define MTK_DP_TRAIN_MAX_ITERATIONS 5
+
+#define MTK_DP_AUX_WRITE_READ_WAIT_TIME_US 20
+
+#define MTK_DP_DP_VERSION_11 0x11
+
+enum mtk_dp_state {
+ MTK_DP_STATE_INITIAL,
+ MTK_DP_STATE_IDLE,
+ MTK_DP_STATE_PREPARE,
+ MTK_DP_STATE_NORMAL,
+};
+
+enum mtk_dp_train_state {
+ MTK_DP_TRAIN_STATE_STARTUP = 0,
+ MTK_DP_TRAIN_STATE_CHECKCAP,
+ MTK_DP_TRAIN_STATE_CHECKEDID,
+ MTK_DP_TRAIN_STATE_TRAINING_PRE,
+ MTK_DP_TRAIN_STATE_TRAINING,
+ MTK_DP_TRAIN_STATE_CHECKTIMING,
+ MTK_DP_TRAIN_STATE_NORMAL,
+ MTK_DP_TRAIN_STATE_POWERSAVE,
+ MTK_DP_TRAIN_STATE_DPIDLE,
+};
+
+struct mtk_dp_timings {
+ struct videomode vm;
+
+ u16 htotal;
+ u16 vtotal;
+ u8 frame_rate;
+ u32 pix_rate_khz;
+};
+
+struct mtk_dp_train_info {
+ bool tps3;
+ bool tps4;
+ bool sink_ssc;
+ bool cable_plugged_in;
+ bool cable_state_change;
+ bool cr_done;
+ bool eq_done;
+
+ // link_rate is in multiple of 0.27Gbps
+ int link_rate;
+ int lane_count;
+
+ int irq_status;
+ int check_cap_count;
+};
+
+// Same values as used by the DP Spec for MISC0 bits 1 and 2
+enum mtk_dp_color_format {
+ MTK_DP_COLOR_FORMAT_RGB_444 = 0,
+ MTK_DP_COLOR_FORMAT_YUV_422 = 1,
+ MTK_DP_COLOR_FORMAT_YUV_444 = 2,
+ MTK_DP_COLOR_FORMAT_YUV_420 = 3,
+ MTK_DP_COLOR_FORMAT_YONLY = 4,
+ MTK_DP_COLOR_FORMAT_RAW = 5,
+ MTK_DP_COLOR_FORMAT_RESERVED = 6,
+ MTK_DP_COLOR_FORMAT_DEFAULT = MTK_DP_COLOR_FORMAT_RGB_444,
+ MTK_DP_COLOR_FORMAT_UNKNOWN = 15,
+};
+
+// Multiple of 0.27Gbps
+enum mtk_dp_linkrate {
+ MTK_DP_LINKRATE_RBR = 0x6,
+ MTK_DP_LINKRATE_HBR = 0xA,
+ MTK_DP_LINKRATE_HBR2 = 0x14,
+ MTK_DP_LINKRATE_HBR25 = 0x19,
+ MTK_DP_LINKRATE_HBR3 = 0x1E,
+};
+
+// Same values as used for DP Spec MISC0 bits 5,6,7
+enum mtk_dp_color_depth {
+ MTK_DP_COLOR_DEPTH_6BIT = 0,
+ MTK_DP_COLOR_DEPTH_8BIT = 1,
+ MTK_DP_COLOR_DEPTH_10BIT = 2,
+ MTK_DP_COLOR_DEPTH_12BIT = 3,
+ MTK_DP_COLOR_DEPTH_16BIT = 4,
+ MTK_DP_COLOR_DEPTH_UNKNOWN = 5,
+};
+
+struct mtk_dp_audio_cfg {
+ int sample_rate;
+ int word_length_bits;
+ int channels;
+};
+
+struct mtk_dp_info {
+ enum mtk_dp_color_depth depth;
+ enum mtk_dp_color_format format;
+ struct mtk_dp_audio_cfg audio_caps;
+ struct mtk_dp_timings timings;
+};
+
+struct mtk_dp_driver_data {
+ bool is_edp;
+};
+
+struct mtk_dp {
+ const struct mtk_dp_driver_data *driver_data;
+ struct device *dev;
+
+ struct drm_device *drm_dev;
+ struct drm_bridge bridge;
+ struct drm_bridge *next_bridge;
+ struct drm_dp_aux aux;
+ struct edid *edid;
+
+ u8 rx_cap[DP_RECEIVER_CAP_SIZE];
+
+ struct mtk_dp_info info;
+ enum mtk_dp_state state;
+
+ struct mtk_dp_train_info train_info;
+ enum mtk_dp_train_state train_state;
+
+ struct regmap *regs;
+ struct clk *dp_tx_clk;
+
+ bool pre_enabled;
+ bool enabled;
+ bool audio_enable;
+
+ bool has_fec;
+ struct mutex dp_lock;
+
+ struct mutex update_plugged_status_lock;
+
+ hdmi_codec_plugged_cb plugged_cb;
+ struct device *codec_dev;
+ u8 connector_eld[MAX_ELD_BYTES];
+};
+
+enum mtk_dp_sdp_type {
+ MTK_DP_SDP_NONE = 0x00,
+ MTK_DP_SDP_ACM = 0x01,
+ MTK_DP_SDP_ISRC = 0x02,
+ MTK_DP_SDP_AVI = 0x03,
+ MTK_DP_SDP_AUI = 0x04,
+ MTK_DP_SDP_SPD = 0x05,
+ MTK_DP_SDP_MPEG = 0x06,
+ MTK_DP_SDP_NTSC = 0x07,
+ MTK_DP_SDP_VSP = 0x08,
+ MTK_DP_SDP_VSC = 0x09,
+ MTK_DP_SDP_EXT = 0x0A,
+ MTK_DP_SDP_PPS0 = 0x0B,
+ MTK_DP_SDP_PPS1 = 0x0C,
+ MTK_DP_SDP_PPS2 = 0x0D,
+ MTK_DP_SDP_PPS3 = 0x0E,
+ MTK_DP_SDP_DRM = 0x10,
+ MTK_DP_SDP_MAX_NUM
+};
+
+struct mtk_dp_sdp_packet {
+ enum mtk_dp_sdp_type type;
+ u8 header[4];
+ u8 data[32];
+};
+
+#define MTK_DP_IEC_CHANNEL_STATUS_LEN 5
+union mtk_dp_audio_channel_status {
+ struct {
+ u8 rev : 1;
+ u8 is_lpcm : 1;
+ u8 copy_right : 1;
+ u8 additional_format_info : 3;
+ u8 channel_status_mode : 2;
+ u8 category_code;
+ u8 src_num : 4;
+ u8 channel_num : 4;
+ u8 sampling_freq : 4;
+ u8 clk_accuracy : 2;
+ u8 rev2 : 2;
+ u8 word_len : 4;
+ u8 original_sampling_freq : 4;
+ } iec;
+
+ u8 buf[MTK_DP_IEC_CHANNEL_STATUS_LEN];
+};
+
+static struct regmap_config mtk_dp_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = SEC_OFFSET + 0x90,
+ .name = "mtk-dp-registers",
+};
+
+static inline struct mtk_dp *mtk_dp_from_bridge(struct drm_bridge *b)
+{
+ return container_of(b, struct mtk_dp, bridge);
+}
+
+static u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset)
+{
+ u32 read_val;
+ int ret;
+
+ ret = regmap_read(mtk_dp->regs, offset, &read_val);
+ if (ret) {
+ dev_err(mtk_dp->dev, "Failed to read register 0x%x: %d\n",
+ offset, ret);
+ return 0;
+ }
+
+ return read_val;
+}
+
+static void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val)
+{
+ int ret;
+
+ ret = regmap_write(mtk_dp->regs, offset, val);
+ if (ret)
+ dev_err(mtk_dp->dev,
+ "Failed to write register 0x%x with value 0x%x: %d\n",
+ offset, val, ret);
+}
+
+static void mtk_dp_update_bits(struct mtk_dp *mtk_dp, u32 offset, u32 val,
+ u32 mask)
+{
+ int ret;
+
+ ret = regmap_update_bits(mtk_dp->regs, offset, mask, val);
+ if (ret)
+ dev_err(mtk_dp->dev,
+ "Failed to update register 0x%x with value 0x%x, mask 0x%x: %d\n",
+ offset, val, mask, ret);
+}
+
+static void mtk_dp_bulk_16bit_write(struct mtk_dp *mtk_dp, u32 offset, u8 *buf,
+ size_t length)
+{
+ int i;
+ int num_regs = (length + 1) / 2;
+
+ // 2 bytes per register
+ for (i = 0; i < num_regs; i++) {
+ u32 val = buf[i * 2] |
+ (i * 2 + 1 < length ? buf[i * 2 + 1] << 8 : 0);
+
+ mtk_dp_write(mtk_dp, offset + i * 4, val);
+ }
+}
+
+static unsigned long mtk_dp_sip_atf_call(unsigned int cmd, unsigned int para)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(MTK_DP_SIP_CONTROL_AARCH32, cmd, para, 0, 0, 0, 0, 0,
+ &res);
+
+ pr_debug("[DPTX]%s cmd 0x%x, p1 0x%x, ret 0x%lx-0x%lx", __func__, cmd,
+ para, res.a0, res.a1);
+ return res.a1;
+}
+
+static void mtk_dp_msa_bypass_disable(struct mtk_dp *mtk_dp)
+{
+ const u16 bits_to_set = BIT(HTOTAL_SEL_DP_ENC0_P0_SHIFT) |
+ BIT(VTOTAL_SEL_DP_ENC0_P0_SHIFT) |
+ BIT(HSTART_SEL_DP_ENC0_P0_SHIFT) |
+ BIT(VSTART_SEL_DP_ENC0_P0_SHIFT) |
+ BIT(HWIDTH_SEL_DP_ENC0_P0_SHIFT) |
+ BIT(VHEIGHT_SEL_DP_ENC0_P0_SHIFT) |
+ BIT(HSP_SEL_DP_ENC0_P0_SHIFT) |
+ BIT(HSW_SEL_DP_ENC0_P0_SHIFT) |
+ BIT(VSP_SEL_DP_ENC0_P0_SHIFT) |
+ BIT(VSW_SEL_DP_ENC0_P0_SHIFT);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3030, bits_to_set,
+ bits_to_set);
+}
+
+static void mtk_dp_set_msa(struct mtk_dp *mtk_dp)
+{
+ struct mtk_dp_timings *timings = &mtk_dp->info.timings;
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3010, timings->htotal,
+ HTOTAL_SW_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3018,
+ timings->vm.hsync_len + timings->vm.hback_porch,
+ HSTART_SW_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3028,
+ timings->vm.hsync_len << HSW_SW_DP_ENC0_P0_SHIFT,
+ HSW_SW_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3028, 0,
+ HSP_SW_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3020, timings->vm.hactive,
+ HWIDTH_SW_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3014, timings->vtotal,
+ VTOTAL_SW_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_301C,
+ timings->vm.vsync_len + timings->vm.vback_porch,
+ VSTART_SW_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_302C,
+ timings->vm.vsync_len << VSW_SW_DP_ENC0_P0_SHIFT,
+ VSW_SW_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_302C, 0,
+ VSP_SW_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3024, timings->vm.vactive,
+ VHEIGHT_SW_DP_ENC0_P0_MASK);
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3064, timings->vm.hactive,
+ HDE_NUM_LAST_DP_ENC0_P0_MASK);
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3154, timings->htotal,
+ PGEN_HTOTAL_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3158,
+ timings->vm.hfront_porch,
+ PGEN_HSYNC_RISING_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_315C, timings->vm.hsync_len,
+ PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3160,
+ timings->vm.hback_porch + timings->vm.hsync_len,
+ PGEN_HFDE_START_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3164, timings->vm.hactive,
+ PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3168, timings->vtotal,
+ PGEN_VTOTAL_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_316C,
+ timings->vm.vfront_porch,
+ PGEN_VSYNC_RISING_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3170, timings->vm.vsync_len,
+ PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3174,
+ timings->vm.vback_porch + timings->vm.vsync_len,
+ PGEN_VFDE_START_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3178, timings->vm.vactive,
+ PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK);
+}
+
+static void mtk_dp_set_color_format(struct mtk_dp *mtk_dp,
+ enum mtk_dp_color_format color_format)
+{
+ u32 val;
+
+ mtk_dp->info.format = color_format;
+
+ // Update MISC0
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034,
+ color_format << DP_TEST_COLOR_FORMAT_SHIFT,
+ DP_TEST_COLOR_FORMAT_MASK);
+
+ switch (color_format) {
+ case MTK_DP_COLOR_FORMAT_YUV_422:
+ val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422;
+ break;
+ case MTK_DP_COLOR_FORMAT_YUV_420:
+ val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR420;
+ break;
+ case MTK_DP_COLOR_FORMAT_YONLY:
+ case MTK_DP_COLOR_FORMAT_RAW:
+ case MTK_DP_COLOR_FORMAT_RESERVED:
+ case MTK_DP_COLOR_FORMAT_UNKNOWN:
+ drm_warn(mtk_dp->drm_dev, "Unsupported color format: %d\n",
+ color_format);
+ fallthrough;
+ case MTK_DP_COLOR_FORMAT_RGB_444:
+ case MTK_DP_COLOR_FORMAT_YUV_444:
+ val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB;
+ break;
+ }
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C, val,
+ PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK);
+}
+
+static void mtk_dp_set_color_depth(struct mtk_dp *mtk_dp,
+ enum mtk_dp_color_depth color_depth)
+{
+ u32 val;
+
+ mtk_dp->info.depth = color_depth;
+
+ // Update MISC0
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034,
+ color_depth << DP_TEST_BIT_DEPTH_SHIFT,
+ DP_TEST_BIT_DEPTH_MASK);
+
+ switch (color_depth) {
+ case MTK_DP_COLOR_DEPTH_6BIT:
+ val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_6BIT;
+ break;
+ case MTK_DP_COLOR_DEPTH_8BIT:
+ val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_8BIT;
+ break;
+ case MTK_DP_COLOR_DEPTH_10BIT:
+ val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_10BIT;
+ break;
+ case MTK_DP_COLOR_DEPTH_12BIT:
+ val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_12BIT;
+ break;
+ case MTK_DP_COLOR_DEPTH_16BIT:
+ val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_16BIT;
+ break;
+ case MTK_DP_COLOR_DEPTH_UNKNOWN:
+ drm_warn(mtk_dp->drm_dev, "Unsupported color depth %d\n",
+ color_depth);
+ return;
+ }
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C, val,
+ VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK);
+}
+
+static void mtk_dp_mn_overwrite_disable(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004, 0,
+ VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK);
+}
+
+static void mtk_dp_set_sram_read_start(struct mtk_dp *mtk_dp, u32 val)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,
+ val << SRAM_START_READ_THRD_DP_ENC0_P0_SHIFT,
+ SRAM_START_READ_THRD_DP_ENC0_P0_MASK);
+}
+
+static void mtk_dp_setup_encoder(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,
+ BIT(VIDEO_MN_GEN_EN_DP_ENC0_P0_SHIFT),
+ VIDEO_MN_GEN_EN_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3040,
+ 0x20 << SDP_DOWN_CNT_INIT_DP_ENC0_P0_SHIFT,
+ SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3364,
+ 0x20 << SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_SHIFT,
+ SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3300,
+ 2 << VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_SHIFT,
+ VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3364,
+ 4 << FIFO_READ_START_POINT_DP_ENC1_P0_SHIFT,
+ FIFO_READ_START_POINT_DP_ENC1_P0_MASK);
+ mtk_dp_write(mtk_dp, MTK_DP_ENC1_P0_3368,
+ 1 << VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0_SHIFT |
+ 1 << VIDEO_STABLE_CNT_THRD_DP_ENC1_P0_SHIFT |
+ BIT(SDP_DP13_EN_DP_ENC1_P0_SHIFT) |
+ 1 << BS2BS_MODE_DP_ENC1_P0_SHIFT);
+}
+
+static void mtk_dp_pg_disable(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3038, 0,
+ VIDEO_SOURCE_SEL_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_31B0, BIT(6), BIT(6));
+}
+
+static void mtk_dp_audio_setup_channels(struct mtk_dp *mtk_dp,
+ struct mtk_dp_audio_cfg *cfg)
+{
+ u32 channel_enable_bits;
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3324,
+ AUDIO_SOURCE_MUX_DP_ENC1_P0_DPRX,
+ AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK);
+
+ //audio channel count change reset
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_33F4, BIT(9), BIT(9));
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3304,
+ AU_PRTY_REGEN_DP_ENC1_P0_MASK,
+ AU_PRTY_REGEN_DP_ENC1_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3304,
+ AU_CH_STS_REGEN_DP_ENC1_P0_MASK,
+ AU_CH_STS_REGEN_DP_ENC1_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3304,
+ AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK,
+ AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK);
+
+ switch (cfg->channels) {
+ case 2:
+ channel_enable_bits = AUDIO_2CH_SEL_DP_ENC0_P0_MASK |
+ AUDIO_2CH_EN_DP_ENC0_P0_MASK;
+ break;
+ case 8:
+ default:
+ channel_enable_bits = AUDIO_8CH_SEL_DP_ENC0_P0_MASK |
+ AUDIO_8CH_EN_DP_ENC0_P0_MASK;
+ break;
+ }
+ mtk_dp_update_bits(
+ mtk_dp, MTK_DP_ENC0_P0_3088,
+ channel_enable_bits | AU_EN_DP_ENC0_P0_MASK,
+ AUDIO_2CH_SEL_DP_ENC0_P0_MASK | AUDIO_2CH_EN_DP_ENC0_P0_MASK |
+ AUDIO_8CH_SEL_DP_ENC0_P0_MASK |
+ AUDIO_8CH_EN_DP_ENC0_P0_MASK | AU_EN_DP_ENC0_P0_MASK);
+
+ //audio channel count change reset
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_33F4, 0, BIT(9));
+
+ //enable audio reset
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_33F4, BIT(0), BIT(0));
+}
+
+static void mtk_dp_audio_channel_status_set(struct mtk_dp *mtk_dp,
+ struct mtk_dp_audio_cfg *cfg)
+{
+ union mtk_dp_audio_channel_status channel_status;
+
+ memset(&channel_status, 0, sizeof(channel_status));
+
+ switch (cfg->sample_rate) {
+ case 32000:
+ channel_status.iec.sampling_freq = 3;
+ break;
+ case 44100:
+ channel_status.iec.sampling_freq = 0;
+ break;
+ case 48000:
+ channel_status.iec.sampling_freq = 2;
+ break;
+ case 88200:
+ channel_status.iec.sampling_freq = 8;
+ break;
+ case 96000:
+ channel_status.iec.sampling_freq = 0xA;
+ break;
+ case 192000:
+ channel_status.iec.sampling_freq = 0xE;
+ break;
+ default:
+ channel_status.iec.sampling_freq = 0x1;
+ break;
+ }
+
+ switch (cfg->word_length_bits) {
+ case 16:
+ channel_status.iec.word_len = 0x02;
+ break;
+ case 20:
+ channel_status.iec.word_len = 0x03;
+ break;
+ case 24:
+ channel_status.iec.word_len = 0x0B;
+ break;
+ }
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_308C,
+ channel_status.buf[1] << 8 | channel_status.buf[0],
+ CH_STATUS_0_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3090,
+ channel_status.buf[3] << 8 | channel_status.buf[2],
+ CH_STATUS_1_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3094, channel_status.buf[4],
+ CH_STATUS_2_DP_ENC0_P0_MASK);
+}
+
+static void mtk_dp_audio_sdp_asp_set_channels(struct mtk_dp *mtk_dp,
+ int channels)
+{
+ if (channels != 2 && channels != 8)
+ channels = 8;
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_312C,
+ (channels - 1) << ASP_HB3_DP_ENC0_P0_SHIFT,
+ ASP_HB2_DP_ENC0_P0_MASK | ASP_HB3_DP_ENC0_P0_MASK);
+}
+
+static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp, u8 divider)
+{
+ mtk_dp_update_bits(
+ mtk_dp, MTK_DP_ENC0_P0_30BC,
+ divider << AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT,
+ AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK);
+}
+
+static bool mtk_dp_plug_state(struct mtk_dp *mtk_dp)
+{
+ return !!(mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3414) &
+ HPD_DB_DP_TRANS_P0_MASK);
+}
+
+static void mtk_dp_sdp_trigger_packet(struct mtk_dp *mtk_dp,
+ enum mtk_dp_sdp_type type)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280, type,
+ SDP_PACKET_TYPE_DP_ENC1_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280, SDP_PACKET_W_DP_ENC1_P0,
+ SDP_PACKET_W_DP_ENC1_P0);
+}
+
+static void mtk_dp_sdp_set_data(struct mtk_dp *mtk_dp, u8 *data_bytes)
+{
+ mtk_dp_bulk_16bit_write(mtk_dp, MTK_DP_ENC1_P0_3200, data_bytes, 0x10);
+}
+
+static void mtk_dp_sdp_set_header(struct mtk_dp *mtk_dp,
+ enum mtk_dp_sdp_type type, u8 *header_bytes)
+{
+ u32 db_addr;
+
+ switch (type) {
+ case MTK_DP_SDP_DRM:
+ db_addr = MTK_DP_ENC0_P0_3138;
+ break;
+ case MTK_DP_SDP_PPS0:
+ case MTK_DP_SDP_PPS1:
+ case MTK_DP_SDP_PPS2:
+ case MTK_DP_SDP_PPS3:
+ db_addr = MTK_DP_ENC0_P0_3130;
+ break;
+ default:
+ db_addr = MTK_DP_ENC0_P0_30D8 + (type - MTK_DP_SDP_ACM) * 8;
+ }
+
+ mtk_dp_bulk_16bit_write(mtk_dp, db_addr, header_bytes, 4);
+}
+
+static const u32 mtk_dp_sdp_type_to_reg[MTK_DP_SDP_MAX_NUM] = {
+ /* MTK_DP_SDP_NONE => */ 0x0,
+ /* MTK_DP_SDP_ACM => */ MTK_DP_ENC0_P0_30B4,
+ /* MTK_DP_SDP_ISRC => */ MTK_DP_ENC0_P0_30B4 + 1,
+ /* MTK_DP_SDP_AVI => */ MTK_DP_ENC0_P0_30A4 + 1,
+ /* MTK_DP_SDP_AUI => */ MTK_DP_ENC0_P0_30A8,
+ /* MTK_DP_SDP_SPD => */ MTK_DP_ENC0_P0_30A8 + 1,
+ /* MTK_DP_SDP_MPEG => */ MTK_DP_ENC0_P0_30AC,
+ /* MTK_DP_SDP_NTSC => */ MTK_DP_ENC0_P0_30AC + 1,
+ /* MTK_DP_SDP_VSP => */ MTK_DP_ENC0_P0_30B0,
+ /* MTK_DP_SDP_VSC => */ MTK_DP_ENC0_P0_30B8,
+ /* MTK_DP_SDP_EXT => */ MTK_DP_ENC0_P0_30B0 + 1,
+ /* MTK_DP_SDP_PPS0 => */ MTK_DP_ENC0_P0_31E8,
+ /* MTK_DP_SDP_PPS1 => */ MTK_DP_ENC0_P0_31E8,
+ /* MTK_DP_SDP_PPS2 => */ MTK_DP_ENC0_P0_31E8,
+ /* MTK_DP_SDP_PPS3 => */ MTK_DP_ENC0_P0_31E8,
+ /* MTK_DP_SDP_DRM => */ MTK_DP_ENC0_P0_31DC,
+};
+
+static void mtk_dp_disable_sdp(struct mtk_dp *mtk_dp,
+ enum mtk_dp_sdp_type type)
+{
+ if (type == MTK_DP_SDP_NONE)
+ return;
+
+ // Disable periodic send
+ mtk_dp_update_bits(mtk_dp, mtk_dp_sdp_type_to_reg[type], 0, 0xFF);
+}
+
+static void mtk_dp_setup_sdp(struct mtk_dp *mtk_dp,
+ struct mtk_dp_sdp_packet *packet)
+{
+ mtk_dp_sdp_set_data(mtk_dp, packet->data);
+ mtk_dp_sdp_set_header(mtk_dp, packet->type, packet->header);
+
+ mtk_dp_disable_sdp(mtk_dp, packet->type);
+
+ switch (packet->type) {
+ case MTK_DP_SDP_NONE:
+ break;
+ case MTK_DP_SDP_ISRC:
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_31EC,
+ 0x1C << ISRC1_HB3_DP_ENC0_P0_SHIFT,
+ ISRC1_HB3_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280, MTK_DP_SDP_ISRC,
+ SDP_PACKET_TYPE_DP_ENC1_P0_MASK);
+
+ if (packet->header[3] & BIT(2))
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC,
+ BIT(ISRC_CONT_DP_ENC0_P0_SHIFT),
+ ISRC_CONT_DP_ENC0_P0_MASK);
+ else
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC, 0,
+ ISRC_CONT_DP_ENC0_P0_MASK);
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280,
+ SDP_PACKET_W_DP_ENC1_P0,
+ SDP_PACKET_W_DP_ENC1_P0);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30B4,
+ 5 << ISRC_CFG_DP_ENC0_P0_SHIFT,
+ ISRC_CFG_DP_ENC0_P0_MASK);
+ break;
+ case MTK_DP_SDP_DRM:
+ mtk_dp_sdp_trigger_packet(mtk_dp, packet->type);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_31DC,
+ 5 << HDR0_CFG_DP_ENC0_P0_SHIFT,
+ HDR0_CFG_DP_ENC0_P0_MASK);
+ break;
+ case MTK_DP_SDP_ACM:
+ case MTK_DP_SDP_AVI:
+ case MTK_DP_SDP_AUI:
+ case MTK_DP_SDP_SPD:
+ case MTK_DP_SDP_MPEG:
+ case MTK_DP_SDP_NTSC:
+ case MTK_DP_SDP_VSP:
+ case MTK_DP_SDP_VSC:
+ case MTK_DP_SDP_EXT:
+ case MTK_DP_SDP_PPS0:
+ case MTK_DP_SDP_PPS1:
+ case MTK_DP_SDP_PPS2:
+ case MTK_DP_SDP_PPS3:
+ mtk_dp_sdp_trigger_packet(mtk_dp, packet->type);
+ // Enable periodic sending
+ mtk_dp_update_bits(mtk_dp, mtk_dp_sdp_type_to_reg[packet->type],
+ 0x05, 0xff);
+ break;
+ default:
+ break;
+ }
+}
+
+static void mtk_dp_sdp_vsc_ext_disable(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30A0, 0,
+ BIT(7) | BIT(8) | BIT(12));
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_328C, 0, BIT(7));
+}
+
+static void mtk_dp_aux_irq_clear(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_write(
+ mtk_dp, MTK_DP_AUX_P0_3640,
+ BIT(AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_SHIFT) |
+ BIT(AUX_RX_DATA_RECV_IRQ_AUX_TX_P0_SHIFT) |
+ BIT(AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0_SHIFT) |
+ BIT(AUX_RX_CMD_RECV_IRQ_AUX_TX_P0_SHIFT) |
+ BIT(AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0_SHIFT) |
+ BIT(AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0_SHIFT) |
+ BIT(AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0_SHIFT));
+}
+
+static void mtk_dp_aux_set_cmd(struct mtk_dp *mtk_dp, u8 cmd, u32 addr)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3644, cmd,
+ MCU_REQUEST_COMMAND_AUX_TX_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3648, addr,
+ MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_364C, addr >> 16,
+ MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_MASK);
+}
+
+static void mtk_dp_aux_cmd_complete(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3650,
+ BIT(MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_SHIFT),
+ MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_MASK |
+ PHY_FIFO_RST_AUX_TX_P0_MASK |
+ MCU_REQ_DATA_NUM_AUX_TX_P0_MASK);
+}
+
+static void mtk_dp_aux_request_ready(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3630,
+ BIT(AUX_TX_REQUEST_READY_AUX_TX_P0_SHIFT),
+ AUX_TX_REQUEST_READY_AUX_TX_P0_MASK);
+}
+
+static void mtk_dp_aux_fill_write_fifo(struct mtk_dp *mtk_dp, u8 *buf,
+ size_t length)
+{
+ mtk_dp_bulk_16bit_write(mtk_dp, MTK_DP_AUX_P0_3708, buf, length);
+}
+
+static void mtk_dp_aux_read_rx_fifo(struct mtk_dp *mtk_dp, u8 *buf,
+ size_t length, int read_delay)
+{
+ int read_pos;
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3620, 0,
+ AUX_RD_MODE_AUX_TX_P0_MASK);
+
+ for (read_pos = 0; read_pos < length; read_pos++) {
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3620,
+ BIT(AUX_RX_FIFO_R_PULSE_TX_P0_SHIFT),
+ AUX_RX_FIFO_READ_PULSE_TX_P0_MASK);
+ udelay(read_delay);
+ buf[read_pos] =
+ (u8)(mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3620) &
+ AUX_RX_FIFO_READ_DATA_AUX_TX_P0_MASK >>
+ AUX_RX_FIFO_READ_DATA_AUX_TX_P0_SHIFT);
+ }
+}
+
+static void mtk_dp_aux_set_length(struct mtk_dp *mtk_dp, size_t length)
+{
+ if (length > 0) {
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3650,
+ (length - 1)
+ << MCU_REQ_DATA_NUM_AUX_TX_P0_SHIFT,
+ MCU_REQ_DATA_NUM_AUX_TX_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_362C, 0,
+ AUX_NO_LENGTH_AUX_TX_P0_MASK |
+ AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK |
+ AUX_RESERVED_RW_0_AUX_TX_P0_MASK);
+ } else {
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_362C,
+ BIT(AUX_NO_LENGTH_AUX_TX_P0_SHIFT),
+ AUX_NO_LENGTH_AUX_TX_P0_MASK |
+ AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK |
+ AUX_RESERVED_RW_0_AUX_TX_P0_MASK);
+ }
+}
+
+static int mtk_dp_aux_wait_for_completion(struct mtk_dp *mtk_dp, bool is_read)
+{
+ int wait_reply = MTK_DP_AUX_WAIT_REPLY_COUNT;
+
+ while (--wait_reply) {
+ u32 aux_irq_status;
+
+ if (is_read) {
+ u32 fifo_status =
+ mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3618);
+
+ if (fifo_status &
+ (AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK |
+ AUX_RX_FIFO_FULL_AUX_TX_P0_MASK)) {
+ return 0;
+ }
+ }
+
+ aux_irq_status = mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3640);
+ if (aux_irq_status & AUX_RX_RECV_COMPLETE_IRQ_TX_P0_MASK)
+ return 0;
+
+ if (aux_irq_status & AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_MASK)
+ return -ETIMEDOUT;
+
+ udelay(1);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int mtk_dp_aux_do_transfer(struct mtk_dp *mtk_dp, bool is_read, u8 cmd,
+ u32 addr, u8 *buf, size_t length)
+{
+ int ret;
+ u32 reply_cmd;
+
+ if (is_read && (length > DP_AUX_MAX_PAYLOAD_BYTES ||
+ (cmd == DP_AUX_NATIVE_READ && !length)))
+ return -EINVAL;
+
+ if (!is_read)
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3704,
+ BIT(AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_SHIFT),
+ AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_MASK);
+
+ mtk_dp_aux_cmd_complete(mtk_dp);
+ mtk_dp_aux_irq_clear(mtk_dp);
+ udelay(MTK_DP_AUX_WRITE_READ_WAIT_TIME_US);
+
+ mtk_dp_aux_set_cmd(mtk_dp, cmd, addr);
+ mtk_dp_aux_set_length(mtk_dp, length);
+
+ if (!is_read) {
+ if (length)
+ mtk_dp_aux_fill_write_fifo(mtk_dp, buf, length);
+
+ mtk_dp_update_bits(
+ mtk_dp, MTK_DP_AUX_P0_3704,
+ AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_MASK,
+ AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_MASK);
+ }
+
+ mtk_dp_aux_request_ready(mtk_dp);
+
+ ret = mtk_dp_aux_wait_for_completion(mtk_dp, is_read);
+
+ reply_cmd = mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3624) &
+ AUX_RX_REPLY_COMMAND_AUX_TX_P0_MASK;
+ if (ret || reply_cmd) {
+ u32 phy_status = mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3628) &
+ AUX_RX_PHY_STATE_AUX_TX_P0_MASK;
+ if (phy_status != AUX_RX_PHY_STATE_AUX_TX_P0_RX_IDLE) {
+ drm_err(mtk_dp->drm_dev,
+ "AUX Rx Aux hang, need SW reset\n");
+ ret = -EIO;
+ }
+
+ mtk_dp_aux_cmd_complete(mtk_dp);
+ mtk_dp_aux_irq_clear(mtk_dp);
+
+ udelay(MTK_DP_AUX_WRITE_READ_WAIT_TIME_US);
+ return ret;
+ }
+
+ if (!length) {
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_362C, 0,
+ AUX_NO_LENGTH_AUX_TX_P0_MASK |
+ AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK |
+ AUX_RESERVED_RW_0_AUX_TX_P0_MASK);
+ } else if (is_read) {
+ int read_delay;
+
+ if (cmd == (DP_AUX_I2C_READ | DP_AUX_I2C_MOT) ||
+ cmd == DP_AUX_I2C_READ)
+ read_delay = 500;
+ else
+ read_delay = 100;
+
+ mtk_dp_aux_read_rx_fifo(mtk_dp, buf, length, read_delay);
+ }
+
+ mtk_dp_aux_cmd_complete(mtk_dp);
+ mtk_dp_aux_irq_clear(mtk_dp);
+ udelay(MTK_DP_AUX_WRITE_READ_WAIT_TIME_US);
+
+ return 0;
+}
+
+static bool mtk_dp_set_swing_pre_emphasis(struct mtk_dp *mtk_dp, int lane_num,
+ int swingValue, int preEmphasis)
+{
+ u32 lane_shift = lane_num * DP_TX1_VOLT_SWING_SHIFT;
+
+ if (lane_num < 0 || lane_num > 3)
+ return false;
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_SWING_EMP,
+ swingValue << (DP_TX0_VOLT_SWING_SHIFT + lane_shift),
+ DP_TX0_VOLT_SWING_MASK << lane_shift);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_SWING_EMP,
+ preEmphasis << (DP_TX0_PRE_EMPH_SHIFT + lane_shift),
+ DP_TX0_PRE_EMPH_MASK << lane_shift);
+
+ return true;
+}
+
+static void mtk_dp_reset_swing_pre_emphasis(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_SWING_EMP, 0,
+ DP_TX0_VOLT_SWING_MASK | DP_TX1_VOLT_SWING_MASK |
+ DP_TX2_VOLT_SWING_MASK |
+ DP_TX3_VOLT_SWING_MASK |
+ DP_TX0_PRE_EMPH_MASK | DP_TX1_PRE_EMPH_MASK |
+ DP_TX2_PRE_EMPH_MASK | DP_TX3_PRE_EMPH_MASK);
+}
+
+static void mtk_dp_fec_enable(struct mtk_dp *mtk_dp, bool enable)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3540,
+ enable ? BIT(FEC_EN_DP_TRANS_P0_SHIFT) : 0,
+ FEC_EN_DP_TRANS_P0_MASK);
+}
+
+static u32 mtk_dp_swirq_get_clear(struct mtk_dp *mtk_dp)
+{
+ u32 irq_status = mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_35D0) &
+ SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK;
+
+ if (irq_status) {
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35C8, irq_status,
+ SW_IRQ_CLR_DP_TRANS_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35C8, 0,
+ SW_IRQ_CLR_DP_TRANS_P0_MASK);
+ }
+
+ return irq_status;
+}
+
+static u32 mtk_dp_hwirq_get_clear(struct mtk_dp *mtk_dp)
+{
+ u8 irq_status = (mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3418) &
+ IRQ_STATUS_DP_TRANS_P0_MASK) >>
+ IRQ_STATUS_DP_TRANS_P0_SHIFT;
+
+ if (irq_status) {
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3418, irq_status,
+ IRQ_CLR_DP_TRANS_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3418, 0,
+ IRQ_CLR_DP_TRANS_P0_MASK);
+ }
+
+ return irq_status;
+}
+
+static void mtk_dp_hwirq_enable(struct mtk_dp *mtk_dp, bool enable)
+{
+ u32 val = 0;
+
+ if (!enable)
+ val = IRQ_MASK_DP_TRANS_P0_DISC_IRQ |
+ IRQ_MASK_DP_TRANS_P0_CONN_IRQ |
+ IRQ_MASK_DP_TRANS_P0_INT_IRQ;
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3418, val,
+ IRQ_MASK_DP_TRANS_P0_MASK);
+}
+
+void mtk_dp_initialize_settings(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_342C,
+ XTAL_FREQ_DP_TRANS_P0_DEFAULT,
+ XTAL_FREQ_DP_TRANS_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3540,
+ BIT(FEC_CLOCK_EN_MODE_DP_TRANS_P0_SHIFT),
+ FEC_CLOCK_EN_MODE_DP_TRANS_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_31EC,
+ BIT(AUDIO_CH_SRC_SEL_DP_ENC0_P0_SHIFT),
+ AUDIO_CH_SRC_SEL_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_304C, 0,
+ SDP_VSYNC_RISING_MASK_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_IRQ_MASK, IRQ_MASK_AUX_TOP_IRQ,
+ IRQ_MASK_AUX_TOP_IRQ);
+}
+
+static void mtk_dp_initialize_hpd_detect_settings(struct mtk_dp *mtk_dp)
+{
+ // Debounce threshold
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
+ 8 << HPD_DEB_THD_DP_TRANS_P0_SHIFT,
+ HPD_DEB_THD_DP_TRANS_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
+ (HPD_INT_THD_DP_TRANS_P0_LOWER_500US |
+ HPD_INT_THD_DP_TRANS_P0_UPPER_1100US)
+ << HPD_INT_THD_DP_TRANS_P0_SHIFT,
+ HPD_INT_THD_DP_TRANS_P0_MASK);
+
+ // Connect threshold 1.5ms + 5 x 0.1ms = 2ms
+ // Disconnect threshold 1.5ms + 5 x 0.1ms = 2ms
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
+ (5 << HPD_DISC_THD_DP_TRANS_P0_SHIFT) |
+ (5 << HPD_CONN_THD_DP_TRANS_P0_SHIFT),
+ HPD_DISC_THD_DP_TRANS_P0_MASK |
+ HPD_CONN_THD_DP_TRANS_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3430,
+ HPD_INT_THD_ECO_DP_TRANS_P0_HIGH_BOUND_EXT,
+ HPD_INT_THD_ECO_DP_TRANS_P0_MASK);
+}
+
+static void mtk_dp_initialize_phy_settings(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, DP_PWR_STATE_BANDGAP,
+ DP_PWR_STATE_MASK);
+ mtk_dp_write(mtk_dp, DP_PHY_DIG_BIT_RATE, 0);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
+ DP_PWR_STATE_BANDGAP_TPLL_LANE, DP_PWR_STATE_MASK);
+
+ mtk_dp_write(mtk_dp, MTK_DP_LANE0_DRIVING_PARAM_3,
+ DRIVING_PARAM_3_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE1_DRIVING_PARAM_3,
+ DRIVING_PARAM_3_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE2_DRIVING_PARAM_3,
+ DRIVING_PARAM_3_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE3_DRIVING_PARAM_3,
+ DRIVING_PARAM_3_DEFAULT);
+
+ mtk_dp_write(mtk_dp, MTK_DP_LANE0_DRIVING_PARAM_4,
+ DRIVING_PARAM_4_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE1_DRIVING_PARAM_4,
+ DRIVING_PARAM_4_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE2_DRIVING_PARAM_4,
+ DRIVING_PARAM_4_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE3_DRIVING_PARAM_4,
+ DRIVING_PARAM_4_DEFAULT);
+
+ mtk_dp_write(mtk_dp, MTK_DP_LANE0_DRIVING_PARAM_5,
+ DRIVING_PARAM_5_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE1_DRIVING_PARAM_5,
+ DRIVING_PARAM_5_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE2_DRIVING_PARAM_5,
+ DRIVING_PARAM_5_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE3_DRIVING_PARAM_5,
+ DRIVING_PARAM_5_DEFAULT);
+
+ mtk_dp_write(mtk_dp, MTK_DP_LANE0_DRIVING_PARAM_6,
+ DRIVING_PARAM_6_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE1_DRIVING_PARAM_6,
+ DRIVING_PARAM_6_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE2_DRIVING_PARAM_6,
+ DRIVING_PARAM_6_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE3_DRIVING_PARAM_6,
+ DRIVING_PARAM_6_DEFAULT);
+
+ mtk_dp_write(mtk_dp, MTK_DP_LANE0_DRIVING_PARAM_7,
+ DRIVING_PARAM_7_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE1_DRIVING_PARAM_7,
+ DRIVING_PARAM_7_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE2_DRIVING_PARAM_7,
+ DRIVING_PARAM_7_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE3_DRIVING_PARAM_7,
+ DRIVING_PARAM_7_DEFAULT);
+
+ mtk_dp_write(mtk_dp, MTK_DP_LANE0_DRIVING_PARAM_8,
+ DRIVING_PARAM_8_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE1_DRIVING_PARAM_8,
+ DRIVING_PARAM_8_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE2_DRIVING_PARAM_8,
+ DRIVING_PARAM_8_DEFAULT);
+ mtk_dp_write(mtk_dp, MTK_DP_LANE3_DRIVING_PARAM_8,
+ DRIVING_PARAM_8_DEFAULT);
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3690,
+ BIT(RX_REPLY_COMPLETE_MODE_AUX_TX_P0_SHIFT),
+ RX_REPLY_COMPLETE_MODE_AUX_TX_P0_MASK);
+}
+
+static void mtk_dp_initialize_aux_settings(struct mtk_dp *mtk_dp)
+{
+ // modify timeout threshold = 1595 [12 : 8]
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_360C, 0x1595,
+ AUX_TIMEOUT_THR_AUX_TX_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3658, 0,
+ AUX_TX_OV_EN_AUX_TX_P0_MASK);
+ // 25 for 26M
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3634,
+ 25 << AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_SHIFT,
+ AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK);
+ // 13 for 26M
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3614,
+ 13 << AUX_RX_UI_CNT_THR_AUX_TX_P0_SHIFT,
+ AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_37C8,
+ BIT(MTK_ATOP_EN_AUX_TX_P0_SHIFT),
+ MTK_ATOP_EN_AUX_TX_P0_MASK);
+}
+
+static void mtk_dp_initialize_digital_settings(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_304C, 0,
+ VBID_VIDEO_MUTE_DP_ENC0_P0_MASK);
+ mtk_dp_set_color_format(mtk_dp, MTK_DP_COLOR_FORMAT_RGB_444);
+ mtk_dp_set_color_depth(mtk_dp, MTK_DP_COLOR_DEPTH_8BIT);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3368,
+ 1 << BS2BS_MODE_DP_ENC1_P0_SHIFT,
+ BS2BS_MODE_DP_ENC1_P0_MASK);
+
+ // dp tx encoder reset all sw
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,
+ BIT(DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0_SHIFT),
+ DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0_MASK);
+ mdelay(1);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004, 0,
+ DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0_MASK);
+}
+
+static void mtk_dp_ssc_enable(struct mtk_dp *mtk_dp, bool enable)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, DP_PWR_STATE_BANDGAP,
+ DP_PWR_STATE_MASK);
+ mtk_dp_update_bits(mtk_dp, DP_PHY_DIG_PLL_CTL_1,
+ enable ? TPLL_SSC_EN : 0, TPLL_SSC_EN);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
+ DP_PWR_STATE_BANDGAP_TPLL_LANE, DP_PWR_STATE_MASK);
+
+ udelay(50);
+}
+
+
+static void mtk_dp_digital_sw_reset(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_340C,
+ BIT(DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0_SHIFT),
+ DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0_MASK);
+ mdelay(1);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_340C, 0,
+ DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0_MASK);
+}
+
+
+static void mtk_dp_phyd_reset(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, DP_PHY_DIG_SW_RST, 0, DP_GLB_SW_RST_PHYD);
+ udelay(50);
+ mtk_dp_update_bits(mtk_dp, DP_PHY_DIG_SW_RST, DP_GLB_SW_RST_PHYD,
+ DP_GLB_SW_RST_PHYD);
+}
+
+static void mtk_dp_set_lanes(struct mtk_dp *mtk_dp, int lanes)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35F0,
+ lanes == 0 ? 0 : BIT(3), BIT(3) | BIT(2));
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000, lanes,
+ LANE_NUM_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_34A4,
+ lanes << LANE_NUM_DP_TRANS_P0_SHIFT,
+ LANE_NUM_DP_TRANS_P0_MASK);
+}
+
+static void mtk_dp_set_tx_rate(struct mtk_dp *mtk_dp,
+ enum mtk_dp_linkrate linkrate)
+{
+ u32 val;
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, DP_PWR_STATE_BANDGAP,
+ DP_PWR_STATE_MASK);
+
+ switch (linkrate) {
+ default:
+ drm_err(mtk_dp->drm_dev,
+ "Implementation error, unknown linkrate %x\n",
+ linkrate);
+ fallthrough;
+ case MTK_DP_LINKRATE_RBR:
+ val = BIT_RATE_RBR;
+ break;
+ case MTK_DP_LINKRATE_HBR:
+ val = BIT_RATE_HBR;
+ break;
+ case MTK_DP_LINKRATE_HBR2:
+ val = BIT_RATE_HBR2;
+ break;
+ case MTK_DP_LINKRATE_HBR3:
+ val = BIT_RATE_HBR3;
+ break;
+ }
+ mtk_dp_write(mtk_dp, DP_PHY_DIG_BIT_RATE, val);
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
+ DP_PWR_STATE_BANDGAP_TPLL_LANE, DP_PWR_STATE_MASK);
+}
+
+static void mtk_dp_set_idle_pattern(struct mtk_dp *mtk_dp, bool enable)
+{
+ const u32 val = POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_MASK |
+ POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_MASK |
+ POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_MASK |
+ POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_MASK;
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3580, enable ? val : 0, val);
+}
+
+static void mtk_dp_train_set_pattern(struct mtk_dp *mtk_dp, int pattern)
+{
+ if (pattern < 0 || pattern > 4) {
+ drm_err(mtk_dp->drm_dev,
+ "Implementation error, no such pattern %d\n", pattern);
+ return;
+ }
+
+ if (pattern == 1) // TPS1
+ mtk_dp_set_idle_pattern(mtk_dp, false);
+
+ mtk_dp_update_bits(
+ mtk_dp, MTK_DP_TRANS_P0_3400,
+ pattern ? BIT(pattern - 1) << PATTERN1_EN_DP_TRANS_P0_SHIFT : 0,
+ PATTERN1_EN_DP_TRANS_P0_MASK |
+ PATTERN2_EN_DP_TRANS_P0_MASK |
+ PATTERN3_EN_DP_TRANS_P0_MASK |
+ PATTERN4_EN_DP_TRANS_P0_MASK);
+}
+
+static void mtk_dp_set_enhanced_frame_mode(struct mtk_dp *mtk_dp, bool enable)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000,
+ enable ? BIT(ENHANCED_FRAME_EN_DP_ENC0_P0_SHIFT) : 0,
+ ENHANCED_FRAME_EN_DP_ENC0_P0_MASK);
+}
+
+static void mtk_dp_training_set_scramble(struct mtk_dp *mtk_dp, bool enable)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3404,
+ enable ? DP_SCR_EN_DP_TRANS_P0_MASK : 0,
+ DP_SCR_EN_DP_TRANS_P0_MASK);
+}
+
+static void mtk_dp_video_mute(struct mtk_dp *mtk_dp, bool enable)
+{
+ u32 val = BIT(VIDEO_MUTE_SEL_DP_ENC0_P0_SHIFT);
+
+ if (enable)
+ val |= BIT(VIDEO_MUTE_SW_DP_ENC0_P0_SHIFT);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000, val,
+ VIDEO_MUTE_SEL_DP_ENC0_P0_MASK |
+ VIDEO_MUTE_SW_DP_ENC0_P0_MASK);
+
+ if (mtk_dp->driver_data->is_edp)
+ mtk_dp_sip_atf_call(MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE, enable);
+ else
+ mtk_dp_sip_atf_call(MTK_DP_SIP_ATF_VIDEO_UNMUTE, enable);
+}
+
+static void mtk_dp_audio_mute(struct mtk_dp *mtk_dp, bool mute)
+{
+ if (mute) {
+ mtk_dp_update_bits(
+ mtk_dp, MTK_DP_ENC0_P0_3030,
+ BIT(VBID_AUDIO_MUTE_SW_DP_ENC0_P0_SHIFT) |
+ BIT(VBID_AUDIO_MUTE_SEL_DP_ENC0_P0_SHIFT),
+ VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0_MASK |
+ VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0_MASK);
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3088, 0,
+ AU_EN_DP_ENC0_P0_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30A4, 0,
+ AU_TS_CFG_DP_ENC0_P0_MASK);
+
+ } else {
+ mtk_dp_update_bits(
+ mtk_dp, MTK_DP_ENC0_P0_3030, 0,
+ VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0_MASK |
+ VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0_MASK);
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3088,
+ BIT(AU_EN_DP_ENC0_P0_SHIFT),
+ AU_EN_DP_ENC0_P0_MASK);
+ // Send one every two frames
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30A4, 0x0F,
+ AU_TS_CFG_DP_ENC0_P0_MASK);
+ }
+}
+
+static void mtk_dp_power_enable(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_RESET_AND_PROBE, 0,
+ SW_RST_B_PHYD);
+ udelay(10);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_RESET_AND_PROBE, SW_RST_B_PHYD,
+ SW_RST_B_PHYD);
+}
+
+static void mtk_dp_power_disable(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_write(mtk_dp, MTK_DP_TOP_PWR_STATE, 0);
+ udelay(10);
+ mtk_dp_write(mtk_dp, 0x0034, 0x4AA);
+ mtk_dp_write(mtk_dp, 0x1040, 0x0);
+ mtk_dp_write(mtk_dp, MTK_DP_TOP_MEM_PD,
+ 0x550 | BIT(FUSE_SEL_SHIFT) | BIT(MEM_ISO_EN_SHIFT));
+}
+
+static void mtk_dp_initialize_priv_data(struct mtk_dp *mtk_dp)
+{
+ mtk_dp->train_info.link_rate = MTK_DP_LINKRATE_HBR2;
+ mtk_dp->train_info.lane_count = MTK_DP_MAX_LANES;
+ mtk_dp->train_info.irq_status = 0;
+ mtk_dp->train_info.cable_plugged_in = false;
+ mtk_dp->train_info.cable_state_change = false;
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_STARTUP;
+ mtk_dp->state = MTK_DP_STATE_INITIAL;
+
+ mtk_dp->info.format = MTK_DP_COLOR_FORMAT_RGB_444;
+ mtk_dp->info.depth = MTK_DP_COLOR_DEPTH_8BIT;
+ memset(&mtk_dp->info.timings, 0,
+ sizeof(struct mtk_dp_timings));
+ mtk_dp->info.timings.frame_rate = 60;
+
+ mtk_dp->has_fec = false;
+ mtk_dp->audio_enable = false;
+}
+
+static void mtk_dp_sdp_set_down_cnt_init(struct mtk_dp *mtk_dp,
+ u32 Sram_Read_Start)
+{
+ u32 sdp_down_cnt_init = 0;
+ u32 dc_offset;
+
+ if (mtk_dp->info.timings.pix_rate_khz > 0)
+ sdp_down_cnt_init = Sram_Read_Start *
+ mtk_dp->train_info.link_rate * 2700 * 8 /
+ (mtk_dp->info.timings.pix_rate_khz * 4);
+
+ switch (mtk_dp->train_info.lane_count) {
+ case 1:
+ sdp_down_cnt_init = sdp_down_cnt_init > 0x1A ?
+ sdp_down_cnt_init : 0x1A; //26
+ break;
+ case 2:
+ // case for LowResolution && High Audio Sample Rate
+ dc_offset = mtk_dp->info.timings.vtotal <= 525 ?
+ 0x04 : 0x00;
+ sdp_down_cnt_init = sdp_down_cnt_init > 0x10 ?
+ sdp_down_cnt_init : 0x10 + dc_offset; //20 or 16
+ break;
+ case 4:
+ default:
+ sdp_down_cnt_init = sdp_down_cnt_init > 0x06 ?
+ sdp_down_cnt_init : 0x06; //6
+ break;
+ }
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3040,
+ sdp_down_cnt_init
+ << SDP_DOWN_CNT_INIT_DP_ENC0_P0_SHIFT,
+ SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK);
+}
+
+static void mtk_dp_sdp_set_down_cnt_init_in_hblank(struct mtk_dp *mtk_dp)
+{
+ int pix_clk_mhz;
+ u32 dc_offset;
+ u32 spd_down_cnt_init = 0;
+
+ pix_clk_mhz = mtk_dp->info.format == MTK_DP_COLOR_FORMAT_YUV_420 ?
+ mtk_dp->info.timings.pix_rate_khz/2000 :
+ mtk_dp->info.timings.pix_rate_khz/1000;
+
+ switch (mtk_dp->train_info.lane_count) {
+ case 1:
+ spd_down_cnt_init = 0x20;
+ break;
+ case 2:
+ dc_offset = (mtk_dp->info.timings.vtotal <= 525) ? 0x14 : 0x00;
+ spd_down_cnt_init = 0x18 + dc_offset;
+ break;
+ case 4:
+ default:
+ dc_offset = (mtk_dp->info.timings.vtotal <= 525) ? 0x08 : 0x00;
+ if (pix_clk_mhz > mtk_dp->train_info.link_rate * 27)
+ spd_down_cnt_init = 0x8;
+ else
+ spd_down_cnt_init = 0x10 + dc_offset;
+ break;
+ }
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3364, spd_down_cnt_init,
+ SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK);
+}
+
+static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp)
+{
+ u32 sram_read_start = MTK_DP_TBC_BUF_READ_START_ADDR;
+
+ if (mtk_dp->train_info.lane_count > 0) {
+ sram_read_start =
+ min_t(u32, MTK_DP_TBC_BUF_READ_START_ADDR,
+ mtk_dp->info.timings.vm.hactive /
+ (mtk_dp->train_info.lane_count *
+ 4 * 2 * 2));
+ mtk_dp_set_sram_read_start(mtk_dp, sram_read_start);
+ }
+
+ mtk_dp_setup_encoder(mtk_dp);
+ mtk_dp_sdp_set_down_cnt_init_in_hblank(mtk_dp);
+ mtk_dp_sdp_set_down_cnt_init(mtk_dp, sram_read_start);
+}
+
+static void mtk_dp_calculate_pixrate(struct mtk_dp *mtk_dp)
+{
+ int ubTargetFrameRate = 60;
+ int ulTargetPixelclk;
+
+ if (mtk_dp->info.timings.frame_rate > 0) {
+ ubTargetFrameRate = mtk_dp->info.timings.frame_rate;
+ ulTargetPixelclk = (int)mtk_dp->info.timings.htotal *
+ (int)mtk_dp->info.timings.vtotal *
+ ubTargetFrameRate;
+ } else if (mtk_dp->info.timings.pix_rate_khz > 0) {
+ ulTargetPixelclk = mtk_dp->info.timings.pix_rate_khz * 1000;
+ } else {
+ ulTargetPixelclk = (int)mtk_dp->info.timings.htotal *
+ (int)mtk_dp->info.timings.vtotal *
+ ubTargetFrameRate;
+ }
+
+ if (ulTargetPixelclk > 0)
+ mtk_dp->info.timings.pix_rate_khz = ulTargetPixelclk / 1000;
+}
+
+static void mtk_dp_set_tx_out(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_msa_bypass_disable(mtk_dp);
+ mtk_dp_calculate_pixrate(mtk_dp);
+ mtk_dp_pg_disable(mtk_dp);
+ mtk_dp_setup_tu(mtk_dp);
+}
+
+static void mtk_dp_hpd_sink_event(struct mtk_dp *mtk_dp)
+{
+ ssize_t ret;
+ u8 sink_count;
+ u8 link_status[DP_LINK_STATUS_SIZE] = {};
+ u32 sink_count_reg;
+ u32 link_status_reg;
+ bool locked;
+
+ sink_count_reg = DP_SINK_COUNT_ESI;
+ link_status_reg = DP_LANE0_1_STATUS_ESI;
+
+ ret = drm_dp_dpcd_readb(&mtk_dp->aux, sink_count_reg, &sink_count);
+ if (ret < 0) {
+ drm_info(mtk_dp->drm_dev,
+ "Read sink count failed: %ld\n", ret);
+ return;
+ }
+
+ ret = drm_dp_dpcd_readb(&mtk_dp->aux, DP_SINK_COUNT, &sink_count);
+ if (ret < 0) {
+ drm_info(mtk_dp->drm_dev,
+ "Read DP_SINK_COUNT_ESI failed: %ld\n", ret);
+ return;
+ }
+
+ ret = drm_dp_dpcd_read(&mtk_dp->aux, link_status_reg, link_status,
+ sizeof(link_status));
+ if (!ret) {
+ drm_info(mtk_dp->drm_dev, "Read link status failed: %ld\n",
+ ret);
+ return;
+ }
+
+ locked = drm_dp_channel_eq_ok(link_status,
+ mtk_dp->train_info.lane_count);
+ if (!locked && mtk_dp->train_state > MTK_DP_TRAIN_STATE_TRAINING_PRE)
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_TRAINING_PRE;
+
+ if (link_status[1] & DP_REMOTE_CONTROL_COMMAND_PENDING)
+ drm_dp_dpcd_writeb(&mtk_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
+ DP_REMOTE_CONTROL_COMMAND_PENDING);
+
+ if (DP_GET_SINK_COUNT(sink_count) &&
+ (link_status[2] & DP_DOWNSTREAM_PORT_STATUS_CHANGED)) {
+ mtk_dp->train_info.check_cap_count = 0;
+ kfree(mtk_dp->edid);
+ mtk_dp->edid = NULL;
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_CHECKEDID;
+ mdelay(20);
+ }
+}
+
+static void mtk_dp_sdp_stop_sending(struct mtk_dp *mtk_dp)
+{
+ u8 packet_type;
+
+ for (packet_type = MTK_DP_SDP_ACM; packet_type < MTK_DP_SDP_MAX_NUM;
+ packet_type++)
+ mtk_dp_disable_sdp(mtk_dp, packet_type);
+
+ mtk_dp_sdp_vsc_ext_disable(mtk_dp);
+}
+
+static int mtk_dp_train_hpd_handle(struct mtk_dp *mtk_dp)
+{
+ int ret = 0;
+
+ if (mtk_dp->train_info.cable_state_change) {
+ mtk_dp->train_info.cable_state_change = false;
+
+ if (!mtk_dp->train_info.cable_plugged_in ||
+ !mtk_dp_plug_state(mtk_dp)) {
+ mtk_dp_video_mute(mtk_dp, true);
+ mtk_dp_audio_mute(mtk_dp, true);
+
+ mtk_dp_initialize_priv_data(mtk_dp);
+ mtk_dp_set_idle_pattern(mtk_dp, true);
+ if (mtk_dp->has_fec)
+ mtk_dp_fec_enable(mtk_dp, false);
+ mtk_dp_sdp_stop_sending(mtk_dp);
+ mtk_dp_power_disable(mtk_dp);
+
+ clk_disable_unprepare(mtk_dp->dp_tx_clk);
+
+ kfree(mtk_dp->edid);
+ mtk_dp->edid = NULL;
+ ret = -ENODEV;
+ }
+ }
+
+ return ret;
+}
+
+static void mtk_dp_train_update_swing_pre(struct mtk_dp *mtk_dp, int lanes,
+ u8 dpcd_adjust_req[2])
+{
+ int lane;
+
+ for (lane = 0; lane < lanes; ++lane) {
+ u8 val;
+ u8 swing;
+ u8 preemphasis;
+ int index = lane / 2;
+ int shift = lane % 2 ? DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 0;
+
+ swing = (dpcd_adjust_req[index] >> shift) &
+ DP_ADJUST_VOLTAGE_SWING_LANE0_MASK;
+ preemphasis = ((dpcd_adjust_req[index] >> shift) &
+ DP_ADJUST_PRE_EMPHASIS_LANE0_MASK) >>
+ DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT;
+ val = swing << DP_TRAIN_VOLTAGE_SWING_SHIFT |
+ preemphasis << DP_TRAIN_PRE_EMPHASIS_SHIFT;
+
+ if (swing == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
+ val |= DP_TRAIN_MAX_SWING_REACHED;
+ if (preemphasis == 3)
+ val |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+ mtk_dp_set_swing_pre_emphasis(mtk_dp, lane, swing, preemphasis);
+ drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_LANE0_SET + lane,
+ val);
+ }
+
+ // Wait for the signal to be stable enough
+ mdelay(2);
+}
+
+static void mtk_dp_read_link_status(struct mtk_dp *mtk_dp,
+ u8 link_status[DP_LINK_STATUS_SIZE])
+{
+ drm_dp_dpcd_read(&mtk_dp->aux, DP_LANE0_1_STATUS, link_status,
+ DP_LINK_STATUS_SIZE);
+}
+
+static int mtk_dp_train_flow(struct mtk_dp *mtk_dp, int link_rate,
+ int lane_count)
+{
+ u8 link_status[DP_LINK_STATUS_SIZE] = {};
+ int target_link_rate = link_rate;
+ int target_lane_count = lane_count;
+ u8 lane_adjust[2] = {};
+ bool pass_tps1 = false;
+ bool pass_tps2_3 = false;
+ int train_retries;
+ int status_control;
+ int iteration_count;
+ u8 prev_lane_adjust;
+ u8 val;
+
+ drm_dp_dpcd_readb(&mtk_dp->aux, DP_SET_POWER, &val);
+ if (val != DP_SET_POWER_D0) {
+ drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
+ mdelay(1);
+ }
+
+ drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LINK_BW_SET, target_link_rate);
+ drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET,
+ target_lane_count | DP_LANE_COUNT_ENHANCED_FRAME_EN);
+
+ if (mtk_dp->train_info.sink_ssc)
+ drm_dp_dpcd_writeb(&mtk_dp->aux, DP_DOWNSPREAD_CTRL,
+ DP_SPREAD_AMP_0_5);
+
+ train_retries = 0;
+ status_control = 0;
+ iteration_count = 1;
+ prev_lane_adjust = 0xFF;
+
+ mtk_dp_set_lanes(mtk_dp, target_lane_count/2);
+ mtk_dp_set_tx_rate(mtk_dp, target_link_rate);
+
+ do {
+ train_retries++;
+ if (!mtk_dp->train_info.cable_plugged_in ||
+ ((mtk_dp->train_info.irq_status &
+ MTK_DP_HPD_DISCONNECT) != 0x0)) {
+ return -ENODEV;
+ }
+
+ if (mtk_dp->train_state < MTK_DP_TRAIN_STATE_TRAINING)
+ return -EAGAIN;
+
+ if (!pass_tps1) {
+ mtk_dp_training_set_scramble(mtk_dp, false);
+
+ if (status_control == 0) {
+ status_control = 1;
+ mtk_dp_train_set_pattern(mtk_dp, 1);
+ val = DP_LINK_SCRAMBLING_DISABLE |
+ DP_TRAINING_PATTERN_1;
+ drm_dp_dpcd_writeb(
+ &mtk_dp->aux, DP_TRAINING_PATTERN_SET,
+ DP_LINK_SCRAMBLING_DISABLE |
+ DP_TRAINING_PATTERN_1);
+ drm_dp_dpcd_read(&mtk_dp->aux,
+ DP_ADJUST_REQUEST_LANE0_1,
+ lane_adjust,
+ sizeof(lane_adjust));
+ iteration_count++;
+
+ mtk_dp_train_update_swing_pre(mtk_dp,
+ target_lane_count, lane_adjust);
+ }
+
+ drm_dp_link_train_clock_recovery_delay(&mtk_dp->aux,
+ mtk_dp->rx_cap);
+ mtk_dp_read_link_status(mtk_dp, link_status);
+
+ if (drm_dp_clock_recovery_ok(link_status,
+ target_lane_count)) {
+ mtk_dp->train_info.cr_done = true;
+ pass_tps1 = true;
+ train_retries = 0;
+ iteration_count = 1;
+ } else if (prev_lane_adjust == link_status[4]) {
+ iteration_count++;
+ if (prev_lane_adjust &
+ DP_ADJUST_VOLTAGE_SWING_LANE0_MASK)
+ break;
+ } else {
+ prev_lane_adjust = link_status[4];
+ }
+ } else if (pass_tps1 && !pass_tps2_3) {
+ if (status_control == 1) {
+ status_control = 2;
+ if (mtk_dp->train_info.tps4) {
+ mtk_dp_train_set_pattern(mtk_dp, 4);
+ val = DP_TRAINING_PATTERN_4;
+ } else if (mtk_dp->train_info.tps3) {
+ mtk_dp_train_set_pattern(mtk_dp, 3);
+ val = DP_LINK_SCRAMBLING_DISABLE |
+ DP_TRAINING_PATTERN_3;
+ } else {
+ mtk_dp_train_set_pattern(mtk_dp, 2);
+ val = DP_LINK_SCRAMBLING_DISABLE |
+ DP_TRAINING_PATTERN_2;
+ }
+ drm_dp_dpcd_writeb(&mtk_dp->aux,
+ DP_TRAINING_PATTERN_SET,
+ val);
+
+ drm_dp_dpcd_read(&mtk_dp->aux,
+ DP_ADJUST_REQUEST_LANE0_1,
+ lane_adjust,
+ sizeof(lane_adjust));
+
+ iteration_count++;
+ mtk_dp_train_update_swing_pre(
+ mtk_dp, target_lane_count, lane_adjust);
+ }
+
+ drm_dp_link_train_channel_eq_delay(&mtk_dp->aux,
+ mtk_dp->rx_cap);
+
+ mtk_dp_read_link_status(mtk_dp, link_status);
+
+ if (!drm_dp_clock_recovery_ok(link_status,
+ target_lane_count)) {
+ mtk_dp->train_info.cr_done = false;
+ mtk_dp->train_info.eq_done = false;
+ break;
+ }
+
+ if (drm_dp_channel_eq_ok(link_status,
+ target_lane_count)) {
+ mtk_dp->train_info.eq_done = true;
+ pass_tps2_3 = true;
+ break;
+ }
+
+ if (prev_lane_adjust == link_status[4])
+ iteration_count++;
+ else
+ prev_lane_adjust = link_status[4];
+ }
+ } while (train_retries < MTK_DP_TRAIN_RETRY_LIMIT &&
+ iteration_count < MTK_DP_TRAIN_MAX_ITERATIONS);
+
+ drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_DISABLE);
+ mtk_dp_train_set_pattern(mtk_dp, 0);
+
+ if (pass_tps2_3) {
+ mtk_dp->train_info.link_rate = target_link_rate;
+ mtk_dp->train_info.lane_count = target_lane_count;
+
+ mtk_dp_training_set_scramble(mtk_dp, true);
+
+ drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET,
+ target_lane_count |
+ DP_LANE_COUNT_ENHANCED_FRAME_EN);
+ mtk_dp_set_enhanced_frame_mode(mtk_dp, true);
+
+ return 0;
+ }
+
+ return -ETIMEDOUT;
+}
+
+static void mtk_dp_fec_set_capabilities(struct mtk_dp *mtk_dp)
+{
+ u8 fec_capabilities;
+
+ drm_dp_dpcd_readb(&mtk_dp->aux, DP_FEC_CAPABILITY, &fec_capabilities);
+
+ mtk_dp->has_fec = !!(fec_capabilities & DP_FEC_CAPABLE);
+ if (!mtk_dp->has_fec)
+ return;
+
+ drm_dp_dpcd_writeb(&mtk_dp->aux, DP_FEC_CONFIGURATION,
+ DP_FEC_BIT_ERROR_COUNT | DP_FEC_READY);
+}
+
+static bool mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp)
+{
+ u8 buf[DP_RECEIVER_CAP_SIZE] = {};
+ u8 val;
+ struct mtk_dp_train_info *train_info = &mtk_dp->train_info;
+
+ if (!mtk_dp_plug_state(mtk_dp))
+ return false;
+
+ drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
+ mdelay(2);
+
+ drm_dp_dpcd_read(&mtk_dp->aux, DP_DPCD_REV, buf, sizeof(buf));
+
+ memcpy(mtk_dp->rx_cap, buf, min(sizeof(mtk_dp->rx_cap), sizeof(buf)));
+ mtk_dp->rx_cap[DP_TRAINING_AUX_RD_INTERVAL] &= DP_TRAINING_AUX_RD_MASK;
+
+ if (buf[DP_DPCD_REV] >= DP_DPCD_REV_14)
+ mtk_dp_fec_set_capabilities(mtk_dp);
+
+ train_info->link_rate =
+ min_t(int, MTK_DP_MAX_LINK_RATE, buf[DP_MAX_LINK_RATE]);
+ train_info->lane_count =
+ min_t(int, MTK_DP_MAX_LANES, drm_dp_max_lane_count(buf));
+
+ train_info->tps3 = drm_dp_tps3_supported(buf);
+ train_info->tps4 = drm_dp_tps4_supported(buf);
+
+ train_info->sink_ssc =
+ !!(buf[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
+
+ drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val);
+ if (val & DP_MST_CAP) {
+ // Clear DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0
+ drm_dp_dpcd_readb(&mtk_dp->aux,
+ DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0, &val);
+ if (val)
+ drm_dp_dpcd_writeb(&mtk_dp->aux,
+ DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0,
+ val);
+ }
+
+ return true;
+}
+
+static int mtk_dp_edid_parse_audio_capabilities(struct mtk_dp *mtk_dp,
+ struct mtk_dp_audio_cfg *cfg)
+{
+ struct cea_sad *sads;
+ int sad_count;
+ int i;
+ int ret = 0;
+
+ if (mtk_dp->edid == NULL) {
+ dev_err(mtk_dp->dev, "EDID not found!\n");
+ return -EINVAL;
+ }
+
+ sad_count = drm_edid_to_sad(mtk_dp->edid, &sads);
+ if (sad_count <= 0) {
+ drm_info(mtk_dp->drm_dev, "The SADs is NULL\n");
+ return 0;
+ }
+
+ for (i = 0; i < sad_count; i++) {
+ int sample_rate;
+ int word_length;
+ // Only PCM supported at the moment
+ if (sads[i].format != HDMI_AUDIO_CODING_TYPE_PCM)
+ continue;
+
+ sample_rate = drm_cea_sad_get_sample_rate(&sads[i]);
+ word_length =
+ drm_cea_sad_get_uncompressed_word_length(&sads[i]);
+ if (sample_rate <= 0 || word_length <= 0)
+ continue;
+
+ cfg->channels = sads[i].channels;
+ cfg->word_length_bits = word_length;
+ cfg->sample_rate = sample_rate;
+ ret = 1;
+ break;
+ }
+ kfree(sads);
+
+ return ret;
+}
+
+static void mtk_dp_train_change_mode(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_phyd_reset(mtk_dp);
+ mtk_dp_reset_swing_pre_emphasis(mtk_dp);
+ mtk_dp_ssc_enable(mtk_dp, mtk_dp->train_info.sink_ssc);
+
+ mdelay(2);
+}
+
+static int mtk_dp_train_start(struct mtk_dp *mtk_dp)
+{
+ int ret = 0;
+ int lane_count;
+ int link_rate;
+ int train_limit;
+ int max_link_rate;
+ int plug_wait;
+
+ for (plug_wait = 7; !mtk_dp_plug_state(mtk_dp) && plug_wait > 0;
+ --plug_wait)
+ mdelay(1);
+ if (plug_wait == 0) {
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_DPIDLE;
+ return -ENODEV;
+ }
+
+ drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
+
+ link_rate = mtk_dp->rx_cap[1];
+ lane_count = mtk_dp->rx_cap[2] & 0x1F;
+
+ mtk_dp->train_info.link_rate = min(MTK_DP_MAX_LINK_RATE, link_rate);
+ mtk_dp->train_info.lane_count =
+ min(MTK_DP_MAX_LANES, lane_count);
+ link_rate = mtk_dp->train_info.link_rate;
+ lane_count = mtk_dp->train_info.lane_count;
+
+ switch (link_rate) {
+ case MTK_DP_LINKRATE_RBR:
+ case MTK_DP_LINKRATE_HBR:
+ case MTK_DP_LINKRATE_HBR2:
+ case MTK_DP_LINKRATE_HBR25:
+ case MTK_DP_LINKRATE_HBR3:
+ break;
+ default:
+ mtk_dp->train_info.link_rate = MTK_DP_LINKRATE_HBR3;
+ break;
+ };
+
+ max_link_rate = link_rate;
+ for (train_limit = 0; train_limit <= 6; ++train_limit) {
+ mtk_dp->train_info.cr_done = false;
+ mtk_dp->train_info.eq_done = false;
+
+ mtk_dp_train_change_mode(mtk_dp);
+ ret = mtk_dp_train_flow(mtk_dp, link_rate, lane_count);
+ if (ret == -ENODEV || ret == -EAGAIN)
+ return ret;
+
+ if (!mtk_dp->train_info.cr_done) {
+ switch (link_rate) {
+ case MTK_DP_LINKRATE_RBR:
+ lane_count = lane_count/2;
+ link_rate = max_link_rate;
+ if (lane_count == 0x0) {
+ mtk_dp->train_state
+ = MTK_DP_TRAIN_STATE_DPIDLE;
+ return -EIO;
+ }
+ break;
+ case MTK_DP_LINKRATE_HBR:
+ link_rate = MTK_DP_LINKRATE_RBR;
+ break;
+ case MTK_DP_LINKRATE_HBR2:
+ link_rate = MTK_DP_LINKRATE_HBR;
+ break;
+ case MTK_DP_LINKRATE_HBR3:
+ link_rate = MTK_DP_LINKRATE_HBR2;
+ break;
+ default:
+ return -EINVAL;
+ };
+ } else if (!mtk_dp->train_info.eq_done) {
+ lane_count /= 2;
+ if (lane_count == 0)
+ return -EIO;
+ } else
+ return 0;
+
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int mtk_dp_train_handler(struct mtk_dp *mtk_dp)
+{
+ int ret = 0;
+
+ ret = mtk_dp_train_hpd_handle(mtk_dp);
+
+ if (!mtk_dp->train_info.cable_plugged_in)
+ return -ENODEV;
+
+ if (mtk_dp->train_state == MTK_DP_TRAIN_STATE_NORMAL)
+ return ret;
+
+ switch (mtk_dp->train_state) {
+ case MTK_DP_TRAIN_STATE_STARTUP:
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_CHECKCAP;
+ break;
+
+ case MTK_DP_TRAIN_STATE_CHECKCAP:
+ if (mtk_dp_parse_capabilities(mtk_dp)) {
+ mtk_dp->train_info.check_cap_count = 0;
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_CHECKEDID;
+ } else {
+ mtk_dp->train_info.check_cap_count++;
+
+ if (mtk_dp->train_info.check_cap_count >
+ MTK_DP_CHECK_SINK_CAP_TIMEOUT_COUNT) {
+ mtk_dp->train_info.check_cap_count = 0;
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_DPIDLE;
+ ret = -ETIMEDOUT;
+ }
+ }
+ break;
+
+ case MTK_DP_TRAIN_STATE_CHECKEDID:
+ if (mtk_dp->edid) {
+ int caps_found;
+
+ memset(&mtk_dp->info.audio_caps, 0,
+ sizeof(mtk_dp->info.audio_caps));
+ caps_found = mtk_dp_edid_parse_audio_capabilities(
+ mtk_dp, &mtk_dp->info.audio_caps);
+ if (caps_found > 0)
+ mtk_dp->audio_enable = true;
+ } else {
+ drm_info(mtk_dp->drm_dev, "Read EDID Fail!\n");
+ }
+
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_TRAINING_PRE;
+ break;
+
+ case MTK_DP_TRAIN_STATE_TRAINING_PRE:
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_TRAINING;
+ break;
+
+ case MTK_DP_TRAIN_STATE_TRAINING:
+ ret = mtk_dp_train_start(mtk_dp);
+ if (!ret) {
+ mtk_dp_video_mute(mtk_dp, true);
+ mtk_dp_audio_mute(mtk_dp, true);
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_CHECKTIMING;
+ mtk_dp_fec_enable(mtk_dp, mtk_dp->has_fec);
+ } else if (ret != -EAGAIN)
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_DPIDLE;
+
+ ret = 0;
+ break;
+
+ case MTK_DP_TRAIN_STATE_CHECKTIMING:
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_NORMAL;
+ break;
+ case MTK_DP_TRAIN_STATE_NORMAL:
+ break;
+ case MTK_DP_TRAIN_STATE_POWERSAVE:
+ break;
+ case MTK_DP_TRAIN_STATE_DPIDLE:
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static void mtk_dp_video_enable(struct mtk_dp *mtk_dp, bool enable)
+{
+ if (enable) {
+ mtk_dp_set_tx_out(mtk_dp);
+ mtk_dp_video_mute(mtk_dp, false);
+ } else {
+ mtk_dp_video_mute(mtk_dp, true);
+ }
+}
+
+static void mtk_dp_audio_sdp_setup(struct mtk_dp *mtk_dp,
+ struct mtk_dp_audio_cfg *cfg)
+{
+ struct mtk_dp_sdp_packet packet;
+ struct hdmi_audio_infoframe frame;
+
+ hdmi_audio_infoframe_init(&frame);
+ frame.coding_type = HDMI_AUDIO_CODING_TYPE_PCM;
+ frame.channels = cfg->channels;
+ frame.sample_frequency = cfg->sample_rate;
+
+ switch (cfg->word_length_bits) {
+ case 16:
+ frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+ break;
+ case 20:
+ frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_20;
+ break;
+ case 24:
+ default:
+ frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_24;
+ break;
+ }
+
+ packet.type = MTK_DP_SDP_AUI;
+ hdmi_audio_infoframe_pack_for_dp(&frame, packet.header,
+ sizeof(packet.header), packet.data,
+ sizeof(packet.data),
+ MTK_DP_DP_VERSION_11);
+
+ mtk_dp_audio_sdp_asp_set_channels(mtk_dp, cfg->channels);
+ mtk_dp_setup_sdp(mtk_dp, &packet);
+}
+
+static void mtk_dp_audio_setup(struct mtk_dp *mtk_dp,
+ struct mtk_dp_audio_cfg *cfg)
+{
+ mtk_dp_audio_sdp_setup(mtk_dp, cfg);
+ mtk_dp_audio_channel_status_set(mtk_dp, cfg);
+
+ mtk_dp_audio_setup_channels(mtk_dp, cfg);
+ mtk_dp_audio_set_divider(mtk_dp, 5);
+}
+
+static void mtk_dp_video_config(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_mn_overwrite_disable(mtk_dp);
+
+ mtk_dp_set_msa(mtk_dp);
+
+ mtk_dp_set_color_depth(mtk_dp, mtk_dp->info.depth);
+ mtk_dp_set_color_format(mtk_dp, mtk_dp->info.format);
+}
+
+static int mtk_dp_state_handler(struct mtk_dp *mtk_dp)
+{
+ int ret = 0;
+
+ if (!mtk_dp->train_info.cable_plugged_in)
+ return -ENODEV;
+
+ switch (mtk_dp->state) {
+ case MTK_DP_STATE_INITIAL:
+ mtk_dp_video_mute(mtk_dp, true);
+ mtk_dp_audio_mute(mtk_dp, true);
+ mtk_dp->state = MTK_DP_STATE_IDLE;
+ break;
+
+ case MTK_DP_STATE_IDLE:
+ if (mtk_dp->train_state == MTK_DP_TRAIN_STATE_NORMAL)
+ mtk_dp->state = MTK_DP_STATE_PREPARE;
+ break;
+
+ case MTK_DP_STATE_PREPARE:
+ mtk_dp_video_config(mtk_dp);
+ mtk_dp_video_enable(mtk_dp, true);
+
+ if (mtk_dp->audio_enable) {
+ mtk_dp_audio_setup(mtk_dp, &mtk_dp->info.audio_caps);
+ mtk_dp_audio_mute(mtk_dp, false);
+ }
+
+ mtk_dp->state = MTK_DP_STATE_NORMAL;
+ break;
+
+ case MTK_DP_STATE_NORMAL:
+ if (mtk_dp->train_state != MTK_DP_TRAIN_STATE_NORMAL) {
+ mtk_dp_video_mute(mtk_dp, true);
+ mtk_dp_audio_mute(mtk_dp, true);
+ mtk_dp_sdp_stop_sending(mtk_dp);
+ mtk_dp->state = MTK_DP_STATE_IDLE;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static void mtk_dp_init_port(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_set_idle_pattern(mtk_dp, true);
+ mtk_dp_initialize_priv_data(mtk_dp);
+
+ mtk_dp_initialize_settings(mtk_dp);
+ mtk_dp_initialize_aux_settings(mtk_dp);
+ mtk_dp_initialize_digital_settings(mtk_dp);
+ mtk_dp_initialize_phy_settings(mtk_dp);
+ mtk_dp_initialize_hpd_detect_settings(mtk_dp);
+
+ mtk_dp_digital_sw_reset(mtk_dp);
+}
+
+static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)
+{
+ struct mtk_dp *mtk_dp = dev;
+ int event;
+
+ event = mtk_dp_plug_state(mtk_dp) ? connector_status_connected :
+ connector_status_disconnected;
+
+ if (event < 0)
+ return IRQ_HANDLED;
+
+ if (mtk_dp->drm_dev)
+ drm_helper_hpd_irq_event(mtk_dp->bridge.dev);
+
+ if (mtk_dp->train_info.irq_status & MTK_DP_HPD_INTERRUPT) {
+ dev_info(mtk_dp->dev, "MTK_DP_HPD_INTERRUPT\n");
+ mtk_dp->train_info.irq_status &= ~MTK_DP_HPD_INTERRUPT;
+ mtk_dp_hpd_sink_event(mtk_dp);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t mtk_dp_hpd_isr_handler(struct mtk_dp *mtk_dp)
+{
+ bool connected;
+ u16 swirq_status = mtk_dp_swirq_get_clear(mtk_dp);
+ u8 hwirq_status = mtk_dp_hwirq_get_clear(mtk_dp);
+ struct mtk_dp_train_info *train_info = &mtk_dp->train_info;
+
+ train_info->irq_status |= hwirq_status | swirq_status;
+
+ if (!train_info->irq_status)
+ return IRQ_HANDLED;
+
+ connected = mtk_dp_plug_state(mtk_dp);
+ if (connected || !train_info->cable_plugged_in)
+ train_info->irq_status &= ~MTK_DP_HPD_DISCONNECT;
+ else if (!connected || train_info->cable_plugged_in)
+ train_info->irq_status &= ~MTK_DP_HPD_CONNECT;
+
+ if (!(train_info->irq_status &
+ (MTK_DP_HPD_CONNECT | MTK_DP_HPD_DISCONNECT)))
+ return IRQ_HANDLED;
+
+ if (train_info->irq_status & MTK_DP_HPD_CONNECT) {
+ train_info->irq_status &= ~MTK_DP_HPD_CONNECT;
+ train_info->cable_plugged_in = true;
+ } else {
+ train_info->irq_status &= ~MTK_DP_HPD_DISCONNECT;
+ train_info->cable_plugged_in = false;
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_STARTUP;
+ }
+ train_info->cable_state_change = true;
+ return IRQ_WAKE_THREAD;
+}
+
+static irqreturn_t mtk_dp_hpd_event(int hpd, void *dev)
+{
+ struct mtk_dp *mtk_dp = dev;
+ uint32_t irq_status;
+
+ irq_status = mtk_dp_read(mtk_dp, MTK_DP_TOP_IRQ_STATUS);
+
+ if (!irq_status)
+ return IRQ_HANDLED;
+
+ if (irq_status & RGS_IRQ_STATUS_TRANSMITTER)
+ return mtk_dp_hpd_isr_handler(mtk_dp);
+
+ return IRQ_HANDLED;
+}
+
+static int mtk_dp_dt_parse_pdata(struct mtk_dp *mtk_dp,
+ struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int ret = 0;
+ void __iomem *base;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ mtk_dp->regs = devm_regmap_init_mmio(dev, base, &mtk_dp_regmap_config);
+ if (IS_ERR(mtk_dp->regs))
+ return PTR_ERR(mtk_dp->regs);
+
+ dev_err(dev, "Registered regmap: %p\n", mtk_dp->regs);
+
+ mtk_dp->dp_tx_clk = devm_clk_get(dev, "faxi");
+ if (IS_ERR(mtk_dp->dp_tx_clk)) {
+ ret = PTR_ERR(mtk_dp->dp_tx_clk);
+ dev_err(dev, "Failed to get dptx clock: %d\n", ret);
+ mtk_dp->dp_tx_clk = NULL;
+ }
+
+ return 0;
+}
+
+static void mtk_dp_update_plugged_status(struct mtk_dp *mtk_dp)
+{
+ bool connected;
+
+ mutex_lock(&mtk_dp->update_plugged_status_lock);
+ connected = mtk_dp_plug_state(mtk_dp);
+ if (mtk_dp->plugged_cb && mtk_dp->codec_dev)
+ mtk_dp->plugged_cb(mtk_dp->codec_dev, connected);
+ mutex_unlock(&mtk_dp->update_plugged_status_lock);
+}
+
+static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge *bridge)
+{
+ struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
+ enum drm_connector_status ret;
+
+ ret = mtk_dp_plug_state(mtk_dp) ? connector_status_connected :
+ connector_status_disconnected;
+
+ if (mtk_dp->driver_data->is_edp)
+ return connector_status_connected;
+
+ mtk_dp_update_plugged_status(mtk_dp);
+ return ret;
+}
+
+static struct edid *mtk_dp_get_edid(struct drm_bridge *bridge,
+ struct drm_connector *connector)
+{
+ struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
+ bool pre_enabled = mtk_dp->pre_enabled;
+
+ if (mtk_dp->edid)
+ kfree(mtk_dp->edid);
+
+ if (!pre_enabled)
+ drm_bridge_chain_pre_enable(bridge);
+
+ if (mtk_dp_plug_state(mtk_dp))
+ mtk_dp->edid = drm_get_edid(connector, &mtk_dp->aux.ddc);
+ else
+ mtk_dp->edid = NULL;
+
+ if (!pre_enabled)
+ drm_bridge_chain_post_disable(bridge);
+
+ if (!mtk_dp->edid)
+ return NULL;
+
+ return drm_edid_duplicate(mtk_dp->edid);
+}
+
+static ssize_t mtk_dp_aux_transfer(struct drm_dp_aux *mtk_aux,
+ struct drm_dp_aux_msg *msg)
+{
+ ssize_t err = -EAGAIN;
+ struct mtk_dp *mtk_dp;
+ bool is_read;
+ u8 request;
+ size_t accessed_bytes = 0;
+ int ret = 0;
+
+ mtk_dp = container_of(mtk_aux, struct mtk_dp, aux);
+
+ if (!mtk_dp->train_info.cable_plugged_in ||
+ mtk_dp->train_info.irq_status & MTK_DP_HPD_DISCONNECT) {
+ mtk_dp->train_state = MTK_DP_TRAIN_STATE_CHECKCAP;
+ err = -EAGAIN;
+ goto err;
+ }
+
+ switch (msg->request) {
+ case DP_AUX_I2C_MOT:
+ case DP_AUX_I2C_WRITE:
+ case DP_AUX_NATIVE_WRITE:
+ case DP_AUX_I2C_WRITE_STATUS_UPDATE:
+ case DP_AUX_I2C_WRITE_STATUS_UPDATE | DP_AUX_I2C_MOT:
+ request = msg->request & ~DP_AUX_I2C_WRITE_STATUS_UPDATE;
+ is_read = false;
+ break;
+ case DP_AUX_I2C_READ:
+ case DP_AUX_NATIVE_READ:
+ case DP_AUX_I2C_READ | DP_AUX_I2C_MOT:
+ request = msg->request;
+ is_read = true;
+ break;
+ default:
+ drm_err(mtk_aux->drm_dev, "invalid aux cmd = %d\n",
+ msg->request);
+ err = -EINVAL;
+ goto err;
+ }
+
+ while (accessed_bytes < msg->size) {
+ size_t to_access = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES,
+ msg->size - accessed_bytes);
+
+ ret = mtk_dp_aux_do_transfer(mtk_dp, is_read, request,
+ msg->address + accessed_bytes,
+ msg->buffer + accessed_bytes,
+ to_access);
+ accessed_bytes += to_access;
+ if (ret) {
+ drm_info(mtk_dp->drm_dev,
+ "Failed to do AUX transfer: %ld\n", ret);
+ break;
+ }
+ }
+
+err:
+ if (!ret) {
+ msg->reply = DP_AUX_NATIVE_REPLY_ACK | DP_AUX_I2C_REPLY_ACK;
+ ret = msg->size;
+ } else {
+ msg->reply = DP_AUX_NATIVE_REPLY_NACK | DP_AUX_I2C_REPLY_NACK;
+ return err;
+ }
+
+ msg->reply = DP_AUX_NATIVE_REPLY_ACK | DP_AUX_I2C_REPLY_ACK;
+ return msg->size;
+}
+
+static void mtk_dp_aux_init(struct mtk_dp *mtk_dp)
+{
+ drm_dp_aux_init(&mtk_dp->aux);
+ mtk_dp->aux.name = "aux_mtk_dp";
+ mtk_dp->aux.transfer = mtk_dp_aux_transfer;
+}
+
+static void mtk_dp_poweroff(struct mtk_dp *mtk_dp)
+{
+ mutex_lock(&mtk_dp->dp_lock);
+
+ mtk_dp_hwirq_enable(mtk_dp, false);
+ mtk_dp_power_disable(mtk_dp);
+ clk_disable_unprepare(mtk_dp->dp_tx_clk);
+
+ mutex_unlock(&mtk_dp->dp_lock);
+}
+
+static int mtk_dp_poweron(struct mtk_dp *mtk_dp)
+{
+ int ret = 0;
+
+ mutex_lock(&mtk_dp->dp_lock);
+
+ ret = clk_prepare_enable(mtk_dp->dp_tx_clk);
+ if (ret < 0) {
+ dev_err(mtk_dp->dev, "Fail to enable clock: %d\n", ret);
+ goto err;
+ }
+ mtk_dp_init_port(mtk_dp);
+ mtk_dp_power_enable(mtk_dp);
+ mtk_dp_hwirq_enable(mtk_dp, true);
+
+err:
+ mutex_unlock(&mtk_dp->dp_lock);
+ return ret;
+}
+
+static int mtk_dp_bridge_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
+ int ret;
+
+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+ drm_err(mtk_dp->drm_dev,
+ "Driver does not provide a connector!");
+ return -EINVAL;
+ }
+
+ ret = mtk_dp_poweron(mtk_dp);
+ if (ret)
+ return ret;
+
+ if (mtk_dp->next_bridge) {
+ ret = drm_bridge_attach(bridge->encoder, mtk_dp->next_bridge,
+ &mtk_dp->bridge, flags);
+ if (ret) {
+ drm_warn(mtk_dp->drm_dev,
+ "Failed to attach external bridge: %d\n", ret);
+ return ret;
+ }
+ }
+
+ mtk_dp->drm_dev = bridge->dev;
+
+ return 0;
+}
+
+static void mtk_dp_bridge_detach(struct drm_bridge *bridge)
+{
+ struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
+
+ mtk_dp->drm_dev = NULL;
+
+ mtk_dp_poweroff(mtk_dp);
+}
+
+static void mtk_dp_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_state)
+{
+ struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
+
+ mtk_dp->enabled = false;
+}
+
+static void mtk_dp_bridge_post_disable(struct drm_bridge *bridge)
+{
+ struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
+
+ mtk_dp->pre_enabled = false;
+}
+static void mtk_dp_bridge_pre_enable(struct drm_bridge *bridge)
+{
+ struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
+
+ mtk_dp->pre_enabled = true;
+}
+
+static void mtk_dp_parse_drm_mode_timings(struct mtk_dp *mtk_dp,
+ struct drm_display_mode *mode)
+{
+ struct mtk_dp_timings *timings = &mtk_dp->info.timings;
+
+ drm_display_mode_to_videomode(mode, &timings->vm);
+ timings->frame_rate = mode->clock * 1000 / mode->htotal / mode->vtotal;
+ timings->htotal = mode->htotal;
+ timings->vtotal = mode->vtotal;
+}
+
+static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_state)
+{
+ struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
+ struct drm_connector *conn;
+ struct drm_connector_state *conn_state;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *crtc_state;
+ int ret = 0;
+ int i;
+
+ conn = drm_atomic_get_new_connector_for_encoder(old_state->base.state,
+ bridge->encoder);
+ if (!conn) {
+ drm_err(mtk_dp->drm_dev,
+ "Can't enable bridge as connector is missing\n");
+ return;
+ }
+
+ memcpy(mtk_dp->connector_eld, conn->eld, MAX_ELD_BYTES);
+
+ conn_state = drm_atomic_get_new_connector_state(
+ old_state->base.state, conn);
+ if (!conn_state) {
+ drm_err(mtk_dp->drm_dev,
+ "Can't enable bridge as connector state is missing\n");
+ return;
+ }
+
+ crtc = conn_state->crtc;
+ if (!crtc) {
+ drm_err(mtk_dp->drm_dev,
+ "Can't enable bridge as connector state doesn't "
+ "have a crtc\n");
+ return;
+ }
+ crtc_state = drm_atomic_get_new_crtc_state(
+ old_state->base.state, crtc);
+ if (!crtc_state) {
+ drm_err(mtk_dp->drm_dev,
+ "Can't enable bridge as crtc state is missing\n");
+ return;
+ }
+
+ mtk_dp_parse_drm_mode_timings(mtk_dp, &crtc_state->adjusted_mode);
+
+ mtk_dp_parse_capabilities(mtk_dp);
+ //training
+ for (i = 0; i < 50; i++) {
+ ret = mtk_dp_train_handler(mtk_dp);
+ if (ret) {
+ drm_err(mtk_dp->drm_dev, "Train handler failed %d\n",
+ ret);
+ return;
+ }
+
+ ret = mtk_dp_state_handler(mtk_dp);
+ if (ret) {
+ drm_err(mtk_dp->drm_dev, "State handler failed %d\n",
+ ret);
+ return;
+ }
+ }
+
+ mtk_dp->enabled = true;
+}
+
+static const struct drm_bridge_funcs mtk_dp_bridge_funcs = {
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .attach = mtk_dp_bridge_attach,
+ .detach = mtk_dp_bridge_detach,
+ .pre_enable = mtk_dp_bridge_pre_enable,
+ .atomic_enable = mtk_dp_bridge_atomic_enable,
+ .atomic_disable = mtk_dp_bridge_atomic_disable,
+ .post_disable = mtk_dp_bridge_post_disable,
+ .get_edid = mtk_dp_get_edid,
+ .detect = mtk_dp_bdg_detect,
+};
+
+/*
+ * HDMI audio codec callbacks
+ */
+static int mtk_dp_audio_hw_params(struct device *dev, void *data,
+ struct hdmi_codec_daifmt *daifmt,
+ struct hdmi_codec_params *params)
+{
+ struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
+ struct mtk_dp_audio_cfg cfg;
+
+ if (!mtk_dp->enabled) {
+ pr_err("%s, DP is not ready!\n", __func__);
+ return -ENODEV;
+ }
+
+ cfg.channels = params->cea.channels;
+ cfg.sample_rate = params->sample_rate;
+ cfg.word_length_bits = 24;
+
+ mtk_dp_audio_setup(mtk_dp, &cfg);
+
+ return 0;
+}
+
+static int mtk_dp_audio_startup(struct device *dev, void *data)
+{
+ struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
+
+ mtk_dp_audio_mute(mtk_dp, false);
+
+ return 0;
+}
+
+static void mtk_dp_audio_shutdown(struct device *dev, void *data)
+{
+ struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
+
+ mtk_dp_audio_mute(mtk_dp, true);
+}
+
+static int mtk_dp_audio_get_eld(struct device *dev, void *data, uint8_t *buf,
+ size_t len)
+{
+ struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
+
+ if (mtk_dp->enabled)
+ memcpy(buf, mtk_dp->connector_eld, len);
+ else
+ memset(buf, 0, len);
+
+ return 0;
+}
+
+static int mtk_dp_audio_hook_plugged_cb(struct device *dev, void *data,
+ hdmi_codec_plugged_cb fn,
+ struct device *codec_dev)
+{
+ struct mtk_dp *mtk_dp = data;
+
+ mutex_lock(&mtk_dp->update_plugged_status_lock);
+ mtk_dp->plugged_cb = fn;
+ mtk_dp->codec_dev = codec_dev;
+ mutex_unlock(&mtk_dp->update_plugged_status_lock);
+
+ mtk_dp_update_plugged_status(mtk_dp);
+
+ return 0;
+}
+
+static const struct hdmi_codec_ops mtk_dp_audio_codec_ops = {
+ .hw_params = mtk_dp_audio_hw_params,
+ .audio_startup = mtk_dp_audio_startup,
+ .audio_shutdown = mtk_dp_audio_shutdown,
+ .get_eld = mtk_dp_audio_get_eld,
+ .hook_plugged_cb = mtk_dp_audio_hook_plugged_cb,
+ .no_capture_mute = 1,
+};
+
+static int mtk_dp_register_audio_driver(struct device *dev)
+{
+ struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
+ struct hdmi_codec_pdata codec_data = {
+ .ops = &mtk_dp_audio_codec_ops,
+ .max_i2s_channels = 8,
+ .i2s = 1,
+ .data = mtk_dp,
+ };
+ struct platform_device *pdev;
+
+ pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
+ PLATFORM_DEVID_AUTO, &codec_data,
+ sizeof(codec_data));
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ return 0;
+}
+
+static int mtk_dp_probe(struct platform_device *pdev)
+{
+ struct mtk_dp *mtk_dp;
+ struct device *dev = &pdev->dev;
+ int ret;
+ int irq_num = 0;
+ struct drm_panel *panel;
+
+ mtk_dp = devm_kzalloc(dev, sizeof(*mtk_dp), GFP_KERNEL);
+ if (!mtk_dp)
+ return -ENOMEM;
+
+ mtk_dp->dev = dev;
+
+ irq_num = platform_get_irq(pdev, 0);
+ if (irq_num < 0) {
+ dev_err(&pdev->dev, "failed to request dp irq resource\n");
+ return -EPROBE_DEFER;
+ }
+
+ mtk_dp->driver_data = of_device_get_match_data(dev);
+ if (!mtk_dp->driver_data)
+ return -EINVAL;
+
+ if (mtk_dp->driver_data->is_edp) {
+ ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0,
+ &panel, &mtk_dp->next_bridge);
+ if (ret) {
+ dev_err(dev, "Failed to find panel or bridge: %d\n",
+ ret);
+ return -EPROBE_DEFER;
+ }
+
+ if (panel) {
+ mtk_dp->next_bridge =
+ devm_drm_panel_bridge_add(dev, panel);
+ if (IS_ERR(mtk_dp->next_bridge)) {
+ ret = PTR_ERR(mtk_dp->next_bridge);
+ dev_err(dev, "Failed to create bridge: %d\n",
+ ret);
+ return -EPROBE_DEFER;
+ }
+ }
+ }
+
+ ret = mtk_dp_dt_parse_pdata(mtk_dp, pdev);
+ if (ret)
+ return ret;
+
+ mtk_dp_aux_init(mtk_dp);
+
+ ret = devm_request_threaded_irq(&pdev->dev, irq_num, mtk_dp_hpd_event,
+ mtk_dp_hpd_event_thread,
+ IRQ_TYPE_LEVEL_HIGH,
+ dev_name(&pdev->dev), mtk_dp);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request mediatek dptx irq\n");
+ return -EPROBE_DEFER;
+ }
+
+ mutex_init(&mtk_dp->dp_lock);
+
+ platform_set_drvdata(pdev, mtk_dp);
+
+ if (!mtk_dp->driver_data->is_edp) {
+ mutex_init(&mtk_dp->update_plugged_status_lock);
+ ret = mtk_dp_register_audio_driver(dev);
+ if (ret) {
+ dev_err(dev, "Failed to register audio driver: %d\n",
+ ret);
+ return ret;
+ }
+ }
+ mtk_dp->bridge.funcs = &mtk_dp_bridge_funcs;
+ mtk_dp->bridge.of_node = pdev->dev.of_node;
+ if (mtk_dp->driver_data->is_edp)
+ mtk_dp->bridge.type = DRM_MODE_CONNECTOR_eDP;
+ else
+ mtk_dp->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
+
+ mtk_dp->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
+ DRM_BRIDGE_OP_HPD;
+ drm_bridge_add(&mtk_dp->bridge);
+
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
+
+ platform_set_drvdata(pdev, mtk_dp);
+
+ return 0;
+}
+
+static int mtk_dp_remove(struct platform_device *pdev)
+{
+ struct mtk_dp *mtk_dp = platform_get_drvdata(pdev);
+
+ mtk_dp_video_mute(mtk_dp, true);
+ mtk_dp_audio_mute(mtk_dp, true);
+
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int mtk_dp_suspend(struct device *dev)
+{
+ struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
+
+ mtk_dp_power_disable(mtk_dp);
+ mtk_dp_hwirq_enable(mtk_dp, false);
+
+ pm_runtime_put_sync(dev);
+
+ return 0;
+}
+
+static int mtk_dp_resume(struct device *dev)
+{
+ struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
+
+ pm_runtime_get_sync(dev);
+
+ mtk_dp_init_port(mtk_dp);
+ mtk_dp_power_enable(mtk_dp);
+ mtk_dp_hwirq_enable(mtk_dp, true);
+
+ return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops,
+ mtk_dp_suspend, mtk_dp_resume);
+
+static const struct mtk_dp_driver_data mt8195_dp_driver_data = {
+ .is_edp = false,
+};
+
+static const struct mtk_dp_driver_data mt8195_edp_driver_data = {
+ .is_edp = true,
+};
+
+static const struct of_device_id mtk_dp_of_match[] = {
+ {
+ .compatible = "mediatek,mt8195-dp_tx",
+ .data = &mt8195_dp_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt8195-edp_tx",
+ .data = &mt8195_edp_driver_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_dp_of_match);
+
+struct platform_driver mtk_dp_driver = {
+ .probe = mtk_dp_probe,
+ .remove = mtk_dp_remove,
+ .driver = {
+ .name = "mediatek-drm-dp",
+ .of_match_table = mtk_dp_of_match,
+ .pm = &mtk_dp_pm_ops,
+ },
+};
+
diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
new file mode 100644
index 000000000000..26ed3b66da91
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
@@ -0,0 +1,580 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Copyright (c) 2021 BayLibre
+ */
+#ifndef _MTK_DP_REG_H_
+#define _MTK_DP_REG_H_
+
+#define MTK_DP_SIP_CONTROL_AARCH32 0x82000523
+# define MTK_DP_SIP_ATF_VIDEO_UNMUTE 0x20
+# define MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE 0x21
+
+#define TOP_OFFSET 0x2000
+#define ENC0_OFFSET 0x3000
+#define ENC1_OFFSET 0x3200
+#define TRANS_OFFSET 0x3400
+#define AUX_OFFSET 0x3600
+#define SEC_OFFSET 0x4000
+
+#define MTK_DP_HPD_DISCONNECT BIT(1)
+#define MTK_DP_HPD_CONNECT BIT(2)
+#define MTK_DP_HPD_INTERRUPT BIT(3)
+
+#define MTK_DP_ENC0_P0_3000 (ENC0_OFFSET + 0x000)
+# define LANE_NUM_DP_ENC0_P0_MASK 0x3
+# define VIDEO_MUTE_SW_DP_ENC0_P0_MASK 0x4
+# define VIDEO_MUTE_SW_DP_ENC0_P0_SHIFT 2
+# define VIDEO_MUTE_SEL_DP_ENC0_P0_MASK 0x8
+# define VIDEO_MUTE_SEL_DP_ENC0_P0_SHIFT 3
+# define ENHANCED_FRAME_EN_DP_ENC0_P0_MASK 0x10
+# define ENHANCED_FRAME_EN_DP_ENC0_P0_SHIFT 4
+
+#define MTK_DP_ENC0_P0_3004 (ENC0_OFFSET + 0x004)
+# define VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK 0x100
+# define VIDEO_M_CODE_SEL_DP_ENC0_P0_SHIFT 8
+# define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0_MASK 0x200
+# define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0_SHIFT 9
+
+#define MTK_DP_ENC0_P0_3008 (ENC0_OFFSET + 0x008)
+# define VIDEO_M_CODE_SW_0_DP_ENC0_P0_MASK 0xffff
+
+#define MTK_DP_ENC0_P0_300C (ENC0_OFFSET + 0x00C)
+# define VIDEO_M_CODE_SW_1_DP_ENC0_P0_MASK 0xff
+
+#define MTK_DP_ENC0_P0_3010 (ENC0_OFFSET + 0x010)
+# define HTOTAL_SW_DP_ENC0_P0_MASK 0xffff
+
+#define MTK_DP_ENC0_P0_3014 (ENC0_OFFSET + 0x014)
+# define VTOTAL_SW_DP_ENC0_P0_MASK 0xffff
+
+#define MTK_DP_ENC0_P0_3018 (ENC0_OFFSET + 0x018)
+# define HSTART_SW_DP_ENC0_P0_MASK 0xffff
+
+#define MTK_DP_ENC0_P0_301C (ENC0_OFFSET + 0x01C)
+# define VSTART_SW_DP_ENC0_P0_MASK 0xffff
+
+#define MTK_DP_ENC0_P0_3020 (ENC0_OFFSET + 0x020)
+# define HWIDTH_SW_DP_ENC0_P0_MASK 0xffff
+
+#define MTK_DP_ENC0_P0_3024 (ENC0_OFFSET + 0x024)
+# define VHEIGHT_SW_DP_ENC0_P0_MASK 0xffff
+
+#define MTK_DP_ENC0_P0_3028 (ENC0_OFFSET + 0x028)
+# define HSW_SW_DP_ENC0_P0_MASK 0x7fff
+# define HSW_SW_DP_ENC0_P0_SHIFT 0
+# define HSP_SW_DP_ENC0_P0_MASK 0x8000
+
+#define MTK_DP_ENC0_P0_302C (ENC0_OFFSET + 0x02C)
+# define VSW_SW_DP_ENC0_P0_MASK 0x7fff
+# define VSW_SW_DP_ENC0_P0_SHIFT 0
+# define VSP_SW_DP_ENC0_P0_MASK 0x8000
+
+#define MTK_DP_ENC0_P0_3030 (ENC0_OFFSET + 0x030)
+# define HTOTAL_SEL_DP_ENC0_P0_SHIFT 0
+# define VTOTAL_SEL_DP_ENC0_P0_SHIFT 1
+# define HSTART_SEL_DP_ENC0_P0_SHIFT 2
+# define VSTART_SEL_DP_ENC0_P0_SHIFT 3
+# define HWIDTH_SEL_DP_ENC0_P0_SHIFT 4
+# define VHEIGHT_SEL_DP_ENC0_P0_SHIFT 5
+# define HSP_SEL_DP_ENC0_P0_SHIFT 6
+# define HSW_SEL_DP_ENC0_P0_SHIFT 7
+# define VSP_SEL_DP_ENC0_P0_SHIFT 8
+# define VSW_SEL_DP_ENC0_P0_SHIFT 9
+# define VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0_MASK 0x800
+# define VBID_AUDIO_MUTE_SW_DP_ENC0_P0_SHIFT 11
+# define VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0_MASK 0x1000
+# define VBID_AUDIO_MUTE_SEL_DP_ENC0_P0_SHIFT 12
+
+#define MTK_DP_ENC0_P0_3034 (ENC0_OFFSET + 0x034)
+
+#define MTK_DP_ENC0_P0_3038 (ENC0_OFFSET + 0x038)
+# define VIDEO_SOURCE_SEL_DP_ENC0_P0_MASK 0x800
+# define VIDEO_SOURCE_SEL_DP_ENC0_P0_SHIFT 11
+
+#define MTK_DP_ENC0_P0_303C (ENC0_OFFSET + 0x03C)
+# define SRAM_START_READ_THRD_DP_ENC0_P0_MASK 0x3f
+# define SRAM_START_READ_THRD_DP_ENC0_P0_SHIFT 0
+# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK 0x700
+# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_SHIFT 8
+# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_16BIT (0 << VIDEO_COLOR_DEPTH_DP_ENC0_P0_SHIFT)
+# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_12BIT (1 << VIDEO_COLOR_DEPTH_DP_ENC0_P0_SHIFT)
+# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_10BIT (2 << VIDEO_COLOR_DEPTH_DP_ENC0_P0_SHIFT)
+# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_8BIT (3 << VIDEO_COLOR_DEPTH_DP_ENC0_P0_SHIFT)
+# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_6BIT (4 << VIDEO_COLOR_DEPTH_DP_ENC0_P0_SHIFT)
+# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK 0x7000
+# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_SHIFT 12
+# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB (0 << PIXEL_ENCODE_FORMAT_DP_ENC0_P0_SHIFT)
+# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422 (1 << PIXEL_ENCODE_FORMAT_DP_ENC0_P0_SHIFT)
+# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR420 (2 << PIXEL_ENCODE_FORMAT_DP_ENC0_P0_SHIFT)
+# define VIDEO_MN_GEN_EN_DP_ENC0_P0_MASK 0x8000
+# define VIDEO_MN_GEN_EN_DP_ENC0_P0_SHIFT 15
+
+#define MTK_DP_ENC0_P0_3040 (ENC0_OFFSET + 0x040)
+# define SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK 0xfff
+# define SDP_DOWN_CNT_INIT_DP_ENC0_P0_SHIFT 0
+
+#define MTK_DP_ENC0_P0_3044 (ENC0_OFFSET + 0x044)
+# define VIDEO_N_CODE_0_DP_ENC0_P0_MASK 0xffff
+
+#define MTK_DP_ENC0_P0_3048 (ENC0_OFFSET + 0x048)
+# define VIDEO_N_CODE_1_DP_ENC0_P0_MASK 0xff
+
+#define MTK_DP_ENC0_P0_304C (ENC0_OFFSET + 0x04C)
+# define VBID_VIDEO_MUTE_DP_ENC0_P0_MASK 0x4
+# define SDP_VSYNC_RISING_MASK_DP_ENC0_P0_MASK 0x100
+
+#define MTK_DP_ENC0_P0_3050 (ENC0_OFFSET + 0x050)
+# define VIDEO_N_CODE_MN_GEN_0_DP_ENC0_P0_MASK 0xffff
+
+#define MTK_DP_ENC0_P0_3054 (ENC0_OFFSET + 0x054)
+# define VIDEO_N_CODE_MN_GEN_1_DP_ENC0_P0_MASK 0xff
+
+#define MTK_DP_ENC0_P0_3064 (ENC0_OFFSET + 0x064)
+# define HDE_NUM_LAST_DP_ENC0_P0_MASK 0xffff
+
+#define MTK_DP_ENC0_P0_3088 (ENC0_OFFSET + 0x088)
+# define AU_EN_DP_ENC0_P0_MASK 0x40
+# define AU_EN_DP_ENC0_P0_SHIFT 6
+# define AUDIO_8CH_EN_DP_ENC0_P0_MASK 0x80
+# define AUDIO_8CH_SEL_DP_ENC0_P0_MASK 0x100
+# define AUDIO_2CH_EN_DP_ENC0_P0_MASK 0x4000
+# define AUDIO_2CH_SEL_DP_ENC0_P0_MASK 0x8000
+
+#define MTK_DP_ENC0_P0_308C (ENC0_OFFSET + 0x08C)
+# define CH_STATUS_0_DP_ENC0_P0_MASK 0xffff
+
+#define MTK_DP_ENC0_P0_3090 (ENC0_OFFSET + 0x090)
+# define CH_STATUS_1_DP_ENC0_P0_MASK 0xffff
+
+#define MTK_DP_ENC0_P0_3094 (ENC0_OFFSET + 0x094)
+# define CH_STATUS_2_DP_ENC0_P0_MASK 0xff
+
+#define MTK_DP_ENC0_P0_30A0 (ENC0_OFFSET + 0x0A0)
+
+#define MTK_DP_ENC0_P0_30A4 (ENC0_OFFSET + 0x0A4)
+# define AU_TS_CFG_DP_ENC0_P0_MASK 0xff
+
+#define MTK_DP_ENC0_P0_30A8 (ENC0_OFFSET + 0x0A8)
+
+#define MTK_DP_ENC0_P0_30AC (ENC0_OFFSET + 0x0AC)
+
+#define MTK_DP_ENC0_P0_30B0 (ENC0_OFFSET + 0x0B0)
+
+#define MTK_DP_ENC0_P0_30B4 (ENC0_OFFSET + 0x0B4)
+# define ISRC_CFG_DP_ENC0_P0_MASK 0xff00
+# define ISRC_CFG_DP_ENC0_P0_SHIFT 8
+
+#define MTK_DP_ENC0_P0_30B8 (ENC0_OFFSET + 0x0B8)
+
+#define MTK_DP_ENC0_P0_30BC (ENC0_OFFSET + 0x0BC)
+# define ISRC_CONT_DP_ENC0_P0_MASK 0x1
+# define ISRC_CONT_DP_ENC0_P0_SHIFT 0
+# define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK 0x700
+# define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT 8
+
+#define MTK_DP_ENC0_P0_30D8 (ENC0_OFFSET + 0x0D8)
+
+#define MTK_DP_ENC0_P0_312C (ENC0_OFFSET + 0x12C)
+# define ASP_HB2_DP_ENC0_P0_MASK 0xff
+# define ASP_HB3_DP_ENC0_P0_MASK 0xff00
+# define ASP_HB3_DP_ENC0_P0_SHIFT 8
+
+#define MTK_DP_ENC0_P0_3130 (ENC0_OFFSET + 0x130)
+
+#define MTK_DP_ENC0_P0_3138 (ENC0_OFFSET + 0x138)
+
+#define MTK_DP_ENC0_P0_3154 (ENC0_OFFSET + 0x154)
+# define PGEN_HTOTAL_DP_ENC0_P0_MASK 0x3fff
+
+#define MTK_DP_ENC0_P0_3158 (ENC0_OFFSET + 0x158)
+# define PGEN_HSYNC_RISING_DP_ENC0_P0_MASK 0x3fff
+
+#define MTK_DP_ENC0_P0_315C (ENC0_OFFSET + 0x15C)
+# define PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK 0x3fff
+
+#define MTK_DP_ENC0_P0_3160 (ENC0_OFFSET + 0x160)
+# define PGEN_HFDE_START_DP_ENC0_P0_MASK 0x3fff
+
+#define MTK_DP_ENC0_P0_3164 (ENC0_OFFSET + 0x164)
+# define PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK 0x3fff
+
+#define MTK_DP_ENC0_P0_3168 (ENC0_OFFSET + 0x168)
+# define PGEN_VTOTAL_DP_ENC0_P0_MASK 0x1fff
+
+#define MTK_DP_ENC0_P0_316C (ENC0_OFFSET + 0x16C)
+# define PGEN_VSYNC_RISING_DP_ENC0_P0_MASK 0x1fff
+
+#define MTK_DP_ENC0_P0_3170 (ENC0_OFFSET + 0x170)
+# define PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK 0x1fff
+
+#define MTK_DP_ENC0_P0_3174 (ENC0_OFFSET + 0x174)
+# define PGEN_VFDE_START_DP_ENC0_P0_MASK 0x1fff
+
+#define MTK_DP_ENC0_P0_3178 (ENC0_OFFSET + 0x178)
+# define PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK 0x1fff
+
+#define MTK_DP_ENC0_P0_31B0 (ENC0_OFFSET + 0x1B0)
+
+#define MTK_DP_ENC0_P0_31C8 (ENC0_OFFSET + 0x1C8)
+# define VSC_EXT_VESA_HB0_DP_ENC0_P0_MASK 0xff
+# define VSC_EXT_VESA_HB1_DP_ENC0_P0_MASK 0xff00
+# define VSC_EXT_VESA_HB1_DP_ENC0_P0_SHIFT 8
+
+#define MTK_DP_ENC0_P0_31CC (ENC0_OFFSET + 0x1CC)
+# define VSC_EXT_VESA_HB2_DP_ENC0_P0_MASK 0xff
+# define VSC_EXT_VESA_HB2_DP_ENC0_P0_SHIFT 0
+# define VSC_EXT_VESA_HB3_DP_ENC0_P0_MASK 0xff00
+
+#define MTK_DP_ENC0_P0_31D0 (ENC0_OFFSET + 0x1D0)
+# define VSC_EXT_CEA_HB0_DP_ENC0_P0_MASK 0xff
+# define VSC_EXT_CEA_HB1_DP_ENC0_P0_MASK 0xff00
+# define VSC_EXT_CEA_HB1_DP_ENC0_P0_SHIFT 8
+
+#define MTK_DP_ENC0_P0_31D4 (ENC0_OFFSET + 0x1D4)
+# define VSC_EXT_CEA_HB2_DP_ENC0_P0_MASK 0xff
+# define VSC_EXT_CEA_HB2_DP_ENC0_P0_SHIFT 0
+# define VSC_EXT_CEA_HB3_DP_ENC0_P0_MASK 0xff00
+
+#define MTK_DP_ENC0_P0_31D8 (ENC0_OFFSET + 0x1D8)
+# define VSC_EXT_VESA_NUM_DP_ENC0_P0_MASK 0x3f
+# define VSC_EXT_VESA_NUM_DP_ENC0_P0_SHIFT 0
+# define VSC_EXT_CEA_NUM_DP_ENC0_P0_MASK 0x3f00
+# define VSC_EXT_CEA_NUM_DP_ENC0_P0_SHIFT 8
+
+#define MTK_DP_ENC0_P0_31DC (ENC0_OFFSET + 0x1DC)
+# define HDR0_CFG_DP_ENC0_P0_MASK 0xff
+# define HDR0_CFG_DP_ENC0_P0_SHIFT 0
+
+#define MTK_DP_ENC0_P0_31E8 (ENC0_OFFSET + 0x1E8)
+
+#define MTK_DP_ENC0_P0_31EC (ENC0_OFFSET + 0x1EC)
+# define AUDIO_CH_SRC_SEL_DP_ENC0_P0_MASK 0x10
+# define AUDIO_CH_SRC_SEL_DP_ENC0_P0_SHIFT 4
+# define ISRC1_HB3_DP_ENC0_P0_MASK 0xff00
+# define ISRC1_HB3_DP_ENC0_P0_SHIFT 8
+
+#define MTK_DP_ENC1_P0_3200 (ENC1_OFFSET + 0x000)
+
+#define MTK_DP_ENC1_P0_3280 (ENC1_OFFSET + 0x080)
+# define SDP_PACKET_TYPE_DP_ENC1_P0_MASK 0x1f
+# define SDP_PACKET_W_DP_ENC1_P0 0x20
+# define SDP_PACKET_W_DP_ENC1_P0_MASK 0x20
+# define SDP_PACKET_W_DP_ENC1_P0_SHIFT 5
+
+#define MTK_DP_ENC1_P0_328C (ENC1_OFFSET + 0x08C)
+
+#define MTK_DP_ENC1_P0_3290 (ENC1_OFFSET + 0x090)
+
+#define MTK_DP_ENC1_P0_32A0 (ENC1_OFFSET + 0x0A0)
+
+#define MTK_DP_ENC1_P0_32A4 (ENC1_OFFSET + 0x0A4)
+
+#define MTK_DP_ENC1_P0_3300 (ENC1_OFFSET + 0x100)
+# define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK 0x300
+# define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_SHIFT 8
+
+#define MTK_DP_ENC1_P0_3304 (ENC1_OFFSET + 0x104)
+# define AU_PRTY_REGEN_DP_ENC1_P0_MASK 0x100
+# define AU_CH_STS_REGEN_DP_ENC1_P0_MASK 0x200
+# define AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK 0x1000
+
+#define MTK_DP_ENC1_P0_3324 (ENC1_OFFSET + 0x124)
+# define AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK 0x300
+# define AUDIO_SOURCE_MUX_DP_ENC1_P0_SHIFT 8
+# define AUDIO_SOURCE_MUX_DP_ENC1_P0_DPRX (0 << AUDIO_SOURCE_MUX_DP_ENC1_P0_SHIFT)
+
+#define MTK_DP_ENC1_P0_3364 (ENC1_OFFSET + 0x164)
+# define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK 0xfff
+# define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_SHIFT 0
+# define FIFO_READ_START_POINT_DP_ENC1_P0_MASK 0xf000
+# define FIFO_READ_START_POINT_DP_ENC1_P0_SHIFT 12
+
+#define MTK_DP_ENC1_P0_3368 (ENC1_OFFSET + 0x168)
+# define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0_SHIFT 0
+# define VIDEO_STABLE_CNT_THRD_DP_ENC1_P0_SHIFT 4
+# define SDP_DP13_EN_DP_ENC1_P0_SHIFT 8
+# define BS2BS_MODE_DP_ENC1_P0_MASK 0x3000
+# define BS2BS_MODE_DP_ENC1_P0_SHIFT 12
+
+#define MTK_DP_ENC1_P0_33F4 (ENC1_OFFSET + 0x1F4)
+
+#define MTK_DP_TRANS_P0_3400 (TRANS_OFFSET + 0x000)
+# define PATTERN1_EN_DP_TRANS_P0_MASK 0x1000
+# define PATTERN1_EN_DP_TRANS_P0_SHIFT 12
+# define PATTERN2_EN_DP_TRANS_P0_MASK 0x2000
+# define PATTERN3_EN_DP_TRANS_P0_MASK 0x4000
+# define PATTERN4_EN_DP_TRANS_P0_MASK 0x8000
+
+#define MTK_DP_TRANS_P0_3404 (TRANS_OFFSET + 0x004)
+# define DP_SCR_EN_DP_TRANS_P0_MASK 0x1
+
+#define MTK_DP_TRANS_P0_340C (TRANS_OFFSET + 0x00C)
+# define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0_MASK 0x2000
+# define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0_SHIFT 13
+
+#define MTK_DP_TRANS_P0_3410 (TRANS_OFFSET + 0x010)
+# define HPD_DEB_THD_DP_TRANS_P0_MASK 0xf
+# define HPD_DEB_THD_DP_TRANS_P0_SHIFT 0
+# define HPD_INT_THD_DP_TRANS_P0_MASK 0xf0
+# define HPD_INT_THD_DP_TRANS_P0_SHIFT 4
+# define HPD_INT_THD_DP_TRANS_P0_LOWER_500US (2 << HPD_INT_THD_DP_TRANS_P0_SHIFT)
+# define HPD_INT_THD_DP_TRANS_P0_UPPER_1100US (2 << (HPD_INT_THD_DP_TRANS_P0_SHIFT + 2))
+# define HPD_DISC_THD_DP_TRANS_P0_MASK 0xf00
+# define HPD_DISC_THD_DP_TRANS_P0_SHIFT 8
+# define HPD_CONN_THD_DP_TRANS_P0_MASK 0xf000
+# define HPD_CONN_THD_DP_TRANS_P0_SHIFT 12
+
+#define MTK_DP_TRANS_P0_3414 (TRANS_OFFSET + 0x014)
+# define HPD_DB_DP_TRANS_P0_MASK 0x4
+
+#define MTK_DP_TRANS_P0_3418 (TRANS_OFFSET + 0x018)
+# define IRQ_CLR_DP_TRANS_P0_MASK 0xf
+# define IRQ_MASK_DP_TRANS_P0_MASK 0xf0
+# define IRQ_MASK_DP_TRANS_P0_SHIFT 4
+# define IRQ_MASK_DP_TRANS_P0_DISC_IRQ (BIT(1) << IRQ_MASK_DP_TRANS_P0_SHIFT)
+# define IRQ_MASK_DP_TRANS_P0_CONN_IRQ (BIT(2) << IRQ_MASK_DP_TRANS_P0_SHIFT)
+# define IRQ_MASK_DP_TRANS_P0_INT_IRQ (BIT(3) << IRQ_MASK_DP_TRANS_P0_SHIFT)
+# define IRQ_STATUS_DP_TRANS_P0_MASK 0xf000
+# define IRQ_STATUS_DP_TRANS_P0_SHIFT 12
+
+#define MTK_DP_TRANS_P0_342C (TRANS_OFFSET + 0x02C)
+# define XTAL_FREQ_DP_TRANS_P0_DEFAULT 0x69
+# define XTAL_FREQ_DP_TRANS_P0_MASK 0xff
+
+#define MTK_DP_TRANS_P0_3430 (TRANS_OFFSET + 0x030)
+# define HPD_INT_THD_ECO_DP_TRANS_P0_MASK 0x3
+# define HPD_INT_THD_ECO_DP_TRANS_P0_HIGH_BOUND_EXT BIT(1)
+
+#define MTK_DP_TRANS_P0_34A4 (TRANS_OFFSET + 0x0A4)
+# define LANE_NUM_DP_TRANS_P0_MASK 0xc
+# define LANE_NUM_DP_TRANS_P0_SHIFT 2
+
+#define MTK_DP_TRANS_P0_3540 (TRANS_OFFSET + 0x140)
+# define FEC_EN_DP_TRANS_P0_MASK 0x1
+# define FEC_EN_DP_TRANS_P0_SHIFT 0
+# define FEC_CLOCK_EN_MODE_DP_TRANS_P0_MASK 0x8
+# define FEC_CLOCK_EN_MODE_DP_TRANS_P0_SHIFT 3
+
+#define MTK_DP_TRANS_P0_3580 (TRANS_OFFSET + 0x180)
+# define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_MASK 0x100
+# define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_MASK 0x200
+# define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_MASK 0x400
+# define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_MASK 0x800
+
+#define MTK_DP_TRANS_P0_35C4 (TRANS_OFFSET + 0x1C4)
+# define SW_IRQ_MASK_DP_TRANS_P0_MASK 0xffff
+
+#define MTK_DP_TRANS_P0_35C8 (TRANS_OFFSET + 0x1C8)
+# define SW_IRQ_CLR_DP_TRANS_P0_MASK 0xffff
+
+# define SW_IRQ_STATUS_DP_TRANS_P0_MASK 0xffff
+# define SW_IRQ_STATUS_DP_TRANS_P0_SHIFT 0
+
+#define MTK_DP_TRANS_P0_35D0 (TRANS_OFFSET + 0x1D0)
+# define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK 0xffff
+
+#define MTK_DP_TRANS_P0_35F0 (TRANS_OFFSET + 0x1F0)
+
+#define MTK_DP_AUX_P0_360C (AUX_OFFSET + 0x00C)
+# define AUX_TIMEOUT_THR_AUX_TX_P0_MASK 0x1fff
+
+#define MTK_DP_AUX_P0_3614 (AUX_OFFSET + 0x014)
+# define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK 0x7f
+# define AUX_RX_UI_CNT_THR_AUX_TX_P0_SHIFT 0
+
+#define MTK_DP_AUX_P0_3618 (AUX_OFFSET + 0x018)
+# define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK 0x200
+# define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK 0xf
+
+#define MTK_DP_AUX_P0_3620 (AUX_OFFSET + 0x020)
+# define AUX_RD_MODE_AUX_TX_P0_MASK 0x200
+# define AUX_RX_FIFO_READ_PULSE_TX_P0_MASK 0x100
+# define AUX_RX_FIFO_R_PULSE_TX_P0_SHIFT 8
+# define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_MASK 0xff
+# define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_SHIFT 0
+
+#define MTK_DP_AUX_P0_3624 (AUX_OFFSET + 0x024)
+# define AUX_RX_REPLY_COMMAND_AUX_TX_P0_MASK 0xf
+
+#define MTK_DP_AUX_P0_3628 (AUX_OFFSET + 0x028)
+# define AUX_RX_PHY_STATE_AUX_TX_P0_MASK 0x3ff
+# define AUX_RX_PHY_STATE_AUX_TX_P0_SHIFT 0
+# define AUX_RX_PHY_STATE_AUX_TX_P0_RX_IDLE (BIT(1) << AUX_RX_PHY_STATE_AUX_TX_P0_SHIFT)
+
+#define MTK_DP_AUX_P0_362C (AUX_OFFSET + 0x02C)
+# define AUX_NO_LENGTH_AUX_TX_P0_MASK 0x1
+# define AUX_NO_LENGTH_AUX_TX_P0_SHIFT 0
+# define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK 0x2
+# define AUX_RESERVED_RW_0_AUX_TX_P0_MASK 0xfffc
+
+#define MTK_DP_AUX_P0_3630 (AUX_OFFSET + 0x030)
+# define AUX_TX_REQUEST_READY_AUX_TX_P0_MASK 0x8
+# define AUX_TX_REQUEST_READY_AUX_TX_P0_SHIFT 3
+
+#define MTK_DP_AUX_P0_3634 (AUX_OFFSET + 0x034)
+# define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK 0xff00
+# define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_SHIFT 8
+
+#define MTK_DP_AUX_P0_3640 (AUX_OFFSET + 0x040)
+# define AUX_RX_RECV_COMPLETE_IRQ_TX_P0_MASK 0x40
+# define AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0_SHIFT 6
+# define AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0_SHIFT 5
+# define AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0_SHIFT 4
+# define AUX_RX_CMD_RECV_IRQ_AUX_TX_P0_SHIFT 3
+# define AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0_SHIFT 2
+# define AUX_RX_DATA_RECV_IRQ_AUX_TX_P0_SHIFT 1
+# define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_MASK 0x1
+# define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_SHIFT 0
+
+#define MTK_DP_AUX_P0_3644 (AUX_OFFSET + 0x044)
+# define MCU_REQUEST_COMMAND_AUX_TX_P0_MASK 0xf
+
+#define MTK_DP_AUX_P0_3648 (AUX_OFFSET + 0x048)
+# define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK 0xffff
+
+#define MTK_DP_AUX_P0_364C (AUX_OFFSET + 0x04C)
+# define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_MASK 0xf
+
+#define MTK_DP_AUX_P0_3650 (AUX_OFFSET + 0x050)
+# define MCU_REQ_DATA_NUM_AUX_TX_P0_MASK 0xf000
+# define MCU_REQ_DATA_NUM_AUX_TX_P0_SHIFT 12
+# define PHY_FIFO_RST_AUX_TX_P0_MASK 0x200
+# define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_MASK 0x100
+# define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_SHIFT 8
+
+#define MTK_DP_AUX_P0_3658 (AUX_OFFSET + 0x058)
+# define AUX_TX_OV_EN_AUX_TX_P0_MASK 0x1
+
+#define MTK_DP_AUX_P0_3690 (AUX_OFFSET + 0x090)
+# define RX_REPLY_COMPLETE_MODE_AUX_TX_P0_MASK 0x100
+# define RX_REPLY_COMPLETE_MODE_AUX_TX_P0_SHIFT 8
+
+#define MTK_DP_AUX_P0_3704 (AUX_OFFSET + 0x104)
+# define AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_MASK 0x2
+# define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_MASK 0x4
+# define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_SHIFT 2
+
+#define MTK_DP_AUX_P0_3708 (AUX_OFFSET + 0x108)
+
+#define MTK_DP_AUX_P0_37C8 (AUX_OFFSET + 0x1C8)
+# define MTK_ATOP_EN_AUX_TX_P0_MASK 0x1
+# define MTK_ATOP_EN_AUX_TX_P0_SHIFT 0
+
+#define MTK_DP_TOP_PWR_STATE (TOP_OFFSET + 0x00)
+# define DP_PWR_STATE_MASK 0x3
+# define DP_PWR_STATE_BANDGAP 1
+# define DP_PWR_STATE_BANDGAP_TPLL 2
+# define DP_PWR_STATE_BANDGAP_TPLL_LANE 3
+
+#define MTK_DP_TOP_SWING_EMP (TOP_OFFSET + 0x04)
+# define DP_TX0_VOLT_SWING_MASK 0x3
+# define DP_TX0_VOLT_SWING_SHIFT 0
+# define DP_TX0_PRE_EMPH_MASK 0xc
+# define DP_TX0_PRE_EMPH_SHIFT 2
+# define DP_TX1_VOLT_SWING_MASK 0x300
+# define DP_TX1_VOLT_SWING_SHIFT 8
+# define DP_TX1_PRE_EMPH_MASK 0xc00
+# define DP_TX2_VOLT_SWING_MASK 0x30000
+# define DP_TX2_PRE_EMPH_MASK 0xc0000
+# define DP_TX3_VOLT_SWING_MASK 0x3000000
+# define DP_TX3_PRE_EMPH_MASK 0xc000000
+
+#define MTK_DP_TOP_RESET_AND_PROBE (TOP_OFFSET + 0x20)
+# define SW_RST_B_SHIFT 0
+# define SW_RST_B_PHYD (BIT(4) << SW_RST_B_SHIFT)
+
+#define MTK_DP_TOP_IRQ_STATUS (TOP_OFFSET + 0x28)
+# define RGS_IRQ_STATUS_SHIFT 0
+# define RGS_IRQ_STATUS_TRANSMITTER (BIT(1) << RGS_IRQ_STATUS_SHIFT)
+
+#define MTK_DP_TOP_IRQ_MASK (TOP_OFFSET + 0x2C)
+# define IRQ_MASK_AUX_TOP_IRQ BIT(2)
+
+#define MTK_DP_TOP_MEM_PD (TOP_OFFSET + 0x38)
+# define MEM_ISO_EN_SHIFT 0
+# define FUSE_SEL_SHIFT 2
+
+#define DP_PHY_DIG_PLL_CTL_1 0x1014
+# define TPLL_SSC_EN BIT(3)
+
+#define DP_PHY_DIG_BIT_RATE 0x103C
+# define BIT_RATE_RBR 0
+# define BIT_RATE_HBR 1
+# define BIT_RATE_HBR2 2
+# define BIT_RATE_HBR3 3
+
+#define DP_PHY_DIG_SW_RST 0x1038
+# define DP_GLB_SW_RST_PHYD BIT(0)
+
+#define MTK_DP_LANE0_DRIVING_PARAM_3 0x1138
+#define MTK_DP_LANE1_DRIVING_PARAM_3 0x1238
+#define MTK_DP_LANE2_DRIVING_PARAM_3 0x1338
+#define MTK_DP_LANE3_DRIVING_PARAM_3 0x1438
+# define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT 0x10
+# define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (0x14 << 8)
+# define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT (0x18 << 16)
+# define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT (0x20 << 24)
+# define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \
+ XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \
+ XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \
+ XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT)
+
+#define MTK_DP_LANE0_DRIVING_PARAM_4 0x113C
+#define MTK_DP_LANE1_DRIVING_PARAM_4 0x123C
+#define MTK_DP_LANE2_DRIVING_PARAM_4 0x133C
+#define MTK_DP_LANE3_DRIVING_PARAM_4 0x143C
+# define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT 0x18
+# define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT (0x1e << 8)
+# define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (0x24 << 16)
+# define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT (0x20 << 24)
+# define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \
+ XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \
+ XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \
+ XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT)
+
+#define MTK_DP_LANE0_DRIVING_PARAM_5 0x1140
+#define MTK_DP_LANE1_DRIVING_PARAM_5 0x1240
+#define MTK_DP_LANE2_DRIVING_PARAM_5 0x1340
+#define MTK_DP_LANE3_DRIVING_PARAM_5 0x1440
+# define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT 0x28
+# define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT (0x30 << 8)
+# define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \
+ XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT)
+
+#define MTK_DP_LANE0_DRIVING_PARAM_6 0x1144
+#define MTK_DP_LANE1_DRIVING_PARAM_6 0x1244
+#define MTK_DP_LANE2_DRIVING_PARAM_6 0x1344
+#define MTK_DP_LANE3_DRIVING_PARAM_6 0x1444
+# define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0x00
+# define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT (0x04 << 8)
+# define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT (0x08 << 16)
+# define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT (0x10 << 24)
+# define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \
+ XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \
+ XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \
+ XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT)
+
+#define MTK_DP_LANE0_DRIVING_PARAM_7 0x1148
+#define MTK_DP_LANE1_DRIVING_PARAM_7 0x1248
+#define MTK_DP_LANE2_DRIVING_PARAM_7 0x1348
+#define MTK_DP_LANE3_DRIVING_PARAM_7 0x1448
+# define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0x00
+# define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT (0x06 << 8)
+# define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT (0x0c << 16)
+# define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT (0x00 << 24)
+# define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \
+ XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \
+ XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \
+ XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT)
+
+#define MTK_DP_LANE0_DRIVING_PARAM_8 0x114C
+#define MTK_DP_LANE1_DRIVING_PARAM_8 0x124C
+#define MTK_DP_LANE2_DRIVING_PARAM_8 0x134C
+#define MTK_DP_LANE3_DRIVING_PARAM_8 0x144C
+# define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT 0x08
+# define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT (0x00 << 8)
+# define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
+ XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
+
+#endif /*_MTK_DP_REG_H_*/
--
2.33.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v1 1/6] dt-bindings: mediatek,dpi: Add mt8195 dpintf
2021-09-06 19:35 ` [PATCH v1 1/6] dt-bindings: mediatek,dpi: Add mt8195 dpintf Markus Schneider-Pargmann
@ 2021-09-06 20:14 ` Sam Ravnborg
2021-09-09 12:49 ` Markus Schneider-Pargmann
0 siblings, 1 reply; 22+ messages in thread
From: Sam Ravnborg @ 2021-09-06 20:14 UTC (permalink / raw)
To: Markus Schneider-Pargmann
Cc: Chun-Kuang Hu, Philipp Zabel, dri-devel, linux-mediatek,
linux-arm-kernel
Hi Markus,
On Mon, Sep 06, 2021 at 09:35:24PM +0200, Markus Schneider-Pargmann wrote:
> DP_INTF is similar to the actual dpi. They differ in some points
> regarding registers and what needs to be set but the function blocks
> itself are similar in design.
>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
I fail to see why they share the same dt-schema as the main content in
the schema is the clocks and they differ.
A new mediatek,dpintf schema seems more appropriate.
I recall I though so when reading the RFC variant but failed to comment on it.
Sam
> ---
> .../display/mediatek/mediatek,dpi.yaml | 43 ++++++++++++++++---
> 1 file changed, 37 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> index dd2896a40ff0..1a158b719ce6 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> @@ -4,7 +4,7 @@
> $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: mediatek DPI Controller Device Tree Bindings
> +title: mediatek DPI/DP_INTF Controller Device Tree Bindings
>
> maintainers:
> - CK Hu <ck.hu@mediatek.com>
> @@ -13,7 +13,8 @@ maintainers:
> description: |
> The Mediatek DPI function block is a sink of the display subsystem and
> provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
> - output bus.
> + output bus. The Mediatek DP_INTF is a similar function block that is
> + connected to the (embedded) display port function block.
>
> properties:
> compatible:
> @@ -23,6 +24,7 @@ properties:
> - mediatek,mt8173-dpi
> - mediatek,mt8183-dpi
> - mediatek,mt8192-dpi
> + - mediatek,mt8195-dpintf
>
> reg:
> maxItems: 1
> @@ -37,10 +39,11 @@ properties:
> - description: DPI PLL
>
> clock-names:
> - items:
> - - const: pixel
> - - const: engine
> - - const: pll
> + description:
> + For dpi clocks pixel, engine and pll are required. For dpintf pixel,
> + hf_fmm and hf_fdp are required.
> + minItems: 3
> + maxItems: 3
>
> pinctrl-0: true
> pinctrl-1: true
> @@ -64,6 +67,34 @@ required:
> - clock-names
> - port
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - mediatek,mt8195-dpintf
> + then:
> + properties:
> + clocks:
> + minItems: 3
> + maxItems: 3
> + clock-names:
> + items:
> + - const: pixel
> + - const: hf_fmm
> + - const: hf_fdp
> + else:
> + properties:
> + clocks:
> + minItems: 3
> + maxItems: 3
> + clock-names:
> + items:
> + - const: pixel
> + - const: engine
> + - const: pll
> +
> additionalProperties: false
>
> examples:
> --
> 2.33.0
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 3/6] drm/edid: Add cea_sad helpers for freq/length
2021-09-06 19:35 ` [PATCH v1 3/6] drm/edid: Add cea_sad helpers for freq/length Markus Schneider-Pargmann
@ 2021-09-06 20:19 ` Sam Ravnborg
2021-09-07 7:38 ` Markus Schneider-Pargmann
0 siblings, 1 reply; 22+ messages in thread
From: Sam Ravnborg @ 2021-09-06 20:19 UTC (permalink / raw)
To: Markus Schneider-Pargmann
Cc: Chun-Kuang Hu, Philipp Zabel, dri-devel, linux-mediatek,
linux-arm-kernel
Hi Markus,
On Mon, Sep 06, 2021 at 09:35:26PM +0200, Markus Schneider-Pargmann wrote:
> This patch adds two helper functions that extract the frequency and word
> length from a struct cea_sad.
>
> For these helper functions new defines are added that help translate the
> 'freq' and 'byte2' fields into real numbers.
>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
> drivers/gpu/drm/drm_edid.c | 57 ++++++++++++++++++++++++++++++++++++++
> include/drm/drm_edid.h | 18 ++++++++++--
> 2 files changed, 73 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 81d5f2524246..2389d34ce10e 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4666,6 +4666,63 @@ int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
> }
> EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
>
> +/**
> + * drm_cea_sad_get_sample_rate - Extract the sample rate from cea_sad
> + * @sad: Pointer to the cea_sad struct
> + *
> + * Extracts the cea_sad frequency field and returns the sample rate in Hz.
> + *
> + * Return: Sample rate in Hz or a negative errno if parsing failed.
> + */
> +int drm_cea_sad_get_sample_rate(struct cea_sad *sad)
It would be nice to use const struct cea_sad *sad here.
> +{
> + switch (sad->freq) {
> + case CEA_SAD_FREQ_32KHZ:
> + return 32000;
> + case CEA_SAD_FREQ_44KHZ:
> + return 44100;
> + case CEA_SAD_FREQ_48KHZ:
> + return 48000;
> + case CEA_SAD_FREQ_88KHZ:
> + return 88200;
> + case CEA_SAD_FREQ_96KHZ:
> + return 96000;
> + case CEA_SAD_FREQ_176KHZ:
> + return 176400;
> + case CEA_SAD_FREQ_192KHZ:
> + return 192000;
> + default:
> + return -EINVAL;
> + }
> +}
> +EXPORT_SYMBOL(drm_cea_sad_get_sample_rate);
> +
> +/**
> + * drm_cea_sad_get_uncompressed_word_length - Extract word length
> + * @sad: Pointer to the cea_sad struct
> + *
> + * Extracts the cea_sad byte2 field and returns the word length for an
> + * uncompressed stream.
> + *
> + * Note: This function may only be called for uncompressed audio.
Can you check or this and WARN (or drm_WARN) if this is not the case?
> + *
> + * Return: Word length in bits or a negative errno if parsing failed.
> + */
> +int drm_cea_sad_get_uncompressed_word_length(struct cea_sad *sad)
Again, consider to use const.
Sam
> +{
> + switch (sad->byte2) {
> + case CEA_SAD_UNCOMPRESSED_WORD_16BIT:
> + return 16;
> + case CEA_SAD_UNCOMPRESSED_WORD_20BIT:
> + return 20;
> + case CEA_SAD_UNCOMPRESSED_WORD_24BIT:
> + return 24;
> + default:
> + return -EINVAL;
> + }
> +}
> +EXPORT_SYMBOL(drm_cea_sad_get_uncompressed_word_length);
> +
> /**
> * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
> * @connector: connector associated with the HDMI/DP sink
> diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
> index 759328a5eeb2..bed091a749ef 100644
> --- a/include/drm/drm_edid.h
> +++ b/include/drm/drm_edid.h
> @@ -361,12 +361,24 @@ struct edid {
>
> /* Short Audio Descriptor */
> struct cea_sad {
> - u8 format;
> + u8 format; /* See HDMI_AUDIO_CODING_TYPE_* */
> u8 channels; /* max number of channels - 1 */
> - u8 freq;
> + u8 freq; /* See CEA_SAD_FREQ_* */
> u8 byte2; /* meaning depends on format */
> };
>
> +#define CEA_SAD_FREQ_32KHZ BIT(0)
> +#define CEA_SAD_FREQ_44KHZ BIT(1)
> +#define CEA_SAD_FREQ_48KHZ BIT(2)
> +#define CEA_SAD_FREQ_88KHZ BIT(3)
> +#define CEA_SAD_FREQ_96KHZ BIT(4)
> +#define CEA_SAD_FREQ_176KHZ BIT(5)
> +#define CEA_SAD_FREQ_192KHZ BIT(6)
> +
> +#define CEA_SAD_UNCOMPRESSED_WORD_16BIT BIT(0)
> +#define CEA_SAD_UNCOMPRESSED_WORD_20BIT BIT(1)
> +#define CEA_SAD_UNCOMPRESSED_WORD_24BIT BIT(2)
> +
> struct drm_encoder;
> struct drm_connector;
> struct drm_connector_state;
> @@ -374,6 +386,8 @@ struct drm_display_mode;
>
> int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
> int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);
> +int drm_cea_sad_get_sample_rate(struct cea_sad *sad);
> +int drm_cea_sad_get_uncompressed_word_length(struct cea_sad *sad);
> int drm_av_sync_delay(struct drm_connector *connector,
> const struct drm_display_mode *mode);
>
> --
> 2.33.0
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 4/6] video/hdmi: Add audio_infoframe packing for DP
2021-09-06 19:35 ` [PATCH v1 4/6] video/hdmi: Add audio_infoframe packing for DP Markus Schneider-Pargmann
@ 2021-09-06 20:30 ` Sam Ravnborg
2021-09-07 8:59 ` Markus Schneider-Pargmann
0 siblings, 1 reply; 22+ messages in thread
From: Sam Ravnborg @ 2021-09-06 20:30 UTC (permalink / raw)
To: Markus Schneider-Pargmann
Cc: Chun-Kuang Hu, Philipp Zabel, dri-devel, linux-mediatek,
linux-arm-kernel
Hi Markus,
On Mon, Sep 06, 2021 at 09:35:27PM +0200, Markus Schneider-Pargmann wrote:
> Similar to HDMI, DP uses audio infoframes as well which are structured
> very similar to the HDMI ones.
>
> This patch adds a helper function to pack the HDMI audio infoframe for
> DP, called hdmi_audio_infoframe_pack_for_dp().
> hdmi_audio_infoframe_pack_only() is split into two parts. One of them
> packs the payload only and can be used for HDMI and DP.
>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
> drivers/video/hdmi.c | 87 +++++++++++++++++++++++++++++++++++---------
> include/linux/hdmi.h | 4 ++
> 2 files changed, 73 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
> index 947be761dfa4..59c4341549e4 100644
> --- a/drivers/video/hdmi.c
> +++ b/drivers/video/hdmi.c
> @@ -387,6 +387,28 @@ int hdmi_audio_infoframe_check(struct hdmi_audio_infoframe *frame)
> }
> EXPORT_SYMBOL(hdmi_audio_infoframe_check);
>
> +static void
> +hdmi_audio_infoframe_pack_payload(const struct hdmi_audio_infoframe *frame,
> + u8 *buffer)
> +{
> + u8 channels;
> +
> + if (frame->channels >= 2)
> + channels = frame->channels - 1;
> + else
> + channels = 0;
> +
> + buffer[0] = ((frame->coding_type & 0xf) << 4) | (channels & 0x7);
> + buffer[1] = ((frame->sample_frequency & 0x7) << 2) |
> + (frame->sample_size & 0x3);
> + buffer[2] = frame->coding_type_ext & 0x1f;
> + buffer[3] = frame->channel_allocation;
> + buffer[4] = (frame->level_shift_value & 0xf) << 3;
> +
> + if (frame->downmix_inhibit)
> + buffer[4] |= BIT(7);
> +}
> +
> /**
> * hdmi_audio_infoframe_pack_only() - write HDMI audio infoframe to binary buffer
> * @frame: HDMI audio infoframe
> @@ -404,7 +426,6 @@ EXPORT_SYMBOL(hdmi_audio_infoframe_check);
> ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *frame,
> void *buffer, size_t size)
> {
> - unsigned char channels;
> u8 *ptr = buffer;
> size_t length;
> int ret;
> @@ -420,28 +441,13 @@ ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *frame,
>
> memset(buffer, 0, size);
>
> - if (frame->channels >= 2)
> - channels = frame->channels - 1;
> - else
> - channels = 0;
> -
> ptr[0] = frame->type;
> ptr[1] = frame->version;
> ptr[2] = frame->length;
> ptr[3] = 0; /* checksum */
>
> - /* start infoframe payload */
> - ptr += HDMI_INFOFRAME_HEADER_SIZE;
> -
> - ptr[0] = ((frame->coding_type & 0xf) << 4) | (channels & 0x7);
> - ptr[1] = ((frame->sample_frequency & 0x7) << 2) |
> - (frame->sample_size & 0x3);
> - ptr[2] = frame->coding_type_ext & 0x1f;
> - ptr[3] = frame->channel_allocation;
> - ptr[4] = (frame->level_shift_value & 0xf) << 3;
> -
> - if (frame->downmix_inhibit)
> - ptr[4] |= BIT(7);
> + hdmi_audio_infoframe_pack_payload(frame,
> + ptr + HDMI_INFOFRAME_HEADER_SIZE);
>
> hdmi_infoframe_set_checksum(buffer, length);
>
> @@ -479,6 +485,51 @@ ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_infoframe *frame,
> }
> EXPORT_SYMBOL(hdmi_audio_infoframe_pack);
>
> +/**
> + * hdmi_audio_infoframe_pack_for_dp - Pack a HDMI Audio infoframe for
> + * displayport
> + *
> + * @frame HDMI Audio infoframe
> + * @header Header buffer to be used
> + * @header_size Size of header buffer
> + * @data Data buffer to be used
> + * @data_size Size of data buffer
> + * @dp_version Display Port version to be encoded in the header
> + *
> + * Packs a HDMI Audio Infoframe to be sent over Display Port. This function
> + * fills both header and data buffer with the required data.
> + *
> + * Return: Number of total written bytes or a negative errno on failure.
> + */
> +ssize_t hdmi_audio_infoframe_pack_for_dp(struct hdmi_audio_infoframe *frame,
> + void *header, size_t header_size,
> + void *data, size_t data_size,
> + u8 dp_version)
> +{
> + int ret;
> + u8 *hdr_ptr = header;
> +
> + ret = hdmi_audio_infoframe_check(frame);
> + if (ret)
> + return ret;
> +
> + if (header_size < 4 || data_size < frame->length)
> + return -ENOSPC;
> +
> + memset(header, 0, header_size);
> + memset(data, 0, data_size);
> +
> + // Secondary-data packet header
> + hdr_ptr[1] = frame->type;
> + hdr_ptr[2] = 0x1B; // As documented by DP spec for Secondary-data Packets
Any constant we could use or define and use here?
Hard coding 0x1b is the less desireable option.
Sam
> + hdr_ptr[3] = (dp_version & 0x3f) << 2;
> +
> + hdmi_audio_infoframe_pack_payload(frame, data);
> +
> + return frame->length + 4;
> +}
> +EXPORT_SYMBOL(hdmi_audio_infoframe_pack_for_dp);
> +
> /**
> * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe
> * @frame: HDMI vendor infoframe
> diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
> index c8ec982ff498..f576a0b08c85 100644
> --- a/include/linux/hdmi.h
> +++ b/include/linux/hdmi.h
> @@ -334,6 +334,10 @@ struct hdmi_audio_infoframe {
> int hdmi_audio_infoframe_init(struct hdmi_audio_infoframe *frame);
> ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_infoframe *frame,
> void *buffer, size_t size);
> +ssize_t hdmi_audio_infoframe_pack_for_dp(struct hdmi_audio_infoframe *frame,
> + void *header, size_t header_size,
> + void *data, size_t data_size,
> + u8 dp_version);
> ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *frame,
> void *buffer, size_t size);
> int hdmi_audio_infoframe_check(struct hdmi_audio_infoframe *frame);
> --
> 2.33.0
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver
2021-09-06 19:35 ` [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver Markus Schneider-Pargmann
@ 2021-09-06 20:39 ` Sam Ravnborg
2021-09-09 12:45 ` Markus Schneider-Pargmann
2021-09-07 8:47 ` Philipp Zabel
2021-09-09 23:37 ` Chun-Kuang Hu
2 siblings, 1 reply; 22+ messages in thread
From: Sam Ravnborg @ 2021-09-06 20:39 UTC (permalink / raw)
To: Markus Schneider-Pargmann
Cc: Chun-Kuang Hu, Philipp Zabel, dri-devel, linux-mediatek,
linux-arm-kernel
Hi Markus,
On Mon, Sep 06, 2021 at 09:35:29PM +0200, Markus Schneider-Pargmann wrote:
> This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
>
> It supports both functional units on the mt8195, the embedded
> DisplayPort as well as the external DisplayPort units. It offers
> hot-plug-detection, audio up to 8 channels, and DisplayPort 1.4 with up
> to 4 lanes.
>
> This driver is based on an initial version by
> Jason-JH.Lin <jason-jh.lin@mediatek.com>.
>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
>
> Notes:
> Changes RFC -> v1:
> - Removed unused register definitions.
> - Replaced workqueue with threaded irq.
> - Removed connector code.
> - Move to atomic_* drm functions.
> - General cleanups of the code.
> - Remove unused select GENERIC_PHY.
>
> drivers/gpu/drm/mediatek/Kconfig | 6 +
> drivers/gpu/drm/mediatek/Makefile | 2 +
> drivers/gpu/drm/mediatek/mtk_dp.c | 2881 +++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_dp_reg.h | 580 +++++
> 4 files changed, 3469 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h
>
> +
> +static const struct drm_bridge_funcs mtk_dp_bridge_funcs = {
> + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> + .atomic_reset = drm_atomic_helper_bridge_reset,
> + .attach = mtk_dp_bridge_attach,
> + .detach = mtk_dp_bridge_detach,
> + .pre_enable = mtk_dp_bridge_pre_enable,
Use the atomic variant here as pre_enable is deprecated.
> + .atomic_enable = mtk_dp_bridge_atomic_enable,
> + .atomic_disable = mtk_dp_bridge_atomic_disable,
> + .post_disable = mtk_dp_bridge_post_disable,
Use the atomic variant here as .post_disable is deprecated.
> + .get_edid = mtk_dp_get_edid,
> + .detect = mtk_dp_bdg_detect,
> +};
Everything else I skimmed looked fine. But it was a quick skim so..
Sam
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 3/6] drm/edid: Add cea_sad helpers for freq/length
2021-09-06 20:19 ` Sam Ravnborg
@ 2021-09-07 7:38 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-07 7:38 UTC (permalink / raw)
To: Sam Ravnborg
Cc: Chun-Kuang Hu, Philipp Zabel, dri-devel, linux-mediatek,
linux-arm-kernel
Hi Sam,
On Mon, Sep 06, 2021 at 10:19:00PM +0200, Sam Ravnborg wrote:
> Hi Markus,
>
> On Mon, Sep 06, 2021 at 09:35:26PM +0200, Markus Schneider-Pargmann wrote:
> > This patch adds two helper functions that extract the frequency and word
> > length from a struct cea_sad.
> >
> > For these helper functions new defines are added that help translate the
> > 'freq' and 'byte2' fields into real numbers.
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > ---
> > drivers/gpu/drm/drm_edid.c | 57 ++++++++++++++++++++++++++++++++++++++
> > include/drm/drm_edid.h | 18 ++++++++++--
> > 2 files changed, 73 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 81d5f2524246..2389d34ce10e 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -4666,6 +4666,63 @@ int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
> > }
> > EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
> >
> > +/**
> > + * drm_cea_sad_get_sample_rate - Extract the sample rate from cea_sad
> > + * @sad: Pointer to the cea_sad struct
> > + *
> > + * Extracts the cea_sad frequency field and returns the sample rate in Hz.
> > + *
> > + * Return: Sample rate in Hz or a negative errno if parsing failed.
> > + */
> > +int drm_cea_sad_get_sample_rate(struct cea_sad *sad)
>
> It would be nice to use const struct cea_sad *sad here.
Thanks, fixing it for the next version.
>
> > +{
> > + switch (sad->freq) {
> > + case CEA_SAD_FREQ_32KHZ:
> > + return 32000;
> > + case CEA_SAD_FREQ_44KHZ:
> > + return 44100;
> > + case CEA_SAD_FREQ_48KHZ:
> > + return 48000;
> > + case CEA_SAD_FREQ_88KHZ:
> > + return 88200;
> > + case CEA_SAD_FREQ_96KHZ:
> > + return 96000;
> > + case CEA_SAD_FREQ_176KHZ:
> > + return 176400;
> > + case CEA_SAD_FREQ_192KHZ:
> > + return 192000;
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +EXPORT_SYMBOL(drm_cea_sad_get_sample_rate);
> > +
> > +/**
> > + * drm_cea_sad_get_uncompressed_word_length - Extract word length
> > + * @sad: Pointer to the cea_sad struct
> > + *
> > + * Extracts the cea_sad byte2 field and returns the word length for an
> > + * uncompressed stream.
> > + *
> > + * Note: This function may only be called for uncompressed audio.
> Can you check or this and WARN (or drm_WARN) if this is not the case?
Good idea, I added a check, a DRM_WARN and return -EINVAL now.
Thanks,
Markus
>
> > + *
> > + * Return: Word length in bits or a negative errno if parsing failed.
> > + */
> > +int drm_cea_sad_get_uncompressed_word_length(struct cea_sad *sad)
> Again, consider to use const.
>
> Sam
>
> > +{
> > + switch (sad->byte2) {
> > + case CEA_SAD_UNCOMPRESSED_WORD_16BIT:
> > + return 16;
> > + case CEA_SAD_UNCOMPRESSED_WORD_20BIT:
> > + return 20;
> > + case CEA_SAD_UNCOMPRESSED_WORD_24BIT:
> > + return 24;
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +EXPORT_SYMBOL(drm_cea_sad_get_uncompressed_word_length);
> > +
> > /**
> > * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
> > * @connector: connector associated with the HDMI/DP sink
> > diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
> > index 759328a5eeb2..bed091a749ef 100644
> > --- a/include/drm/drm_edid.h
> > +++ b/include/drm/drm_edid.h
> > @@ -361,12 +361,24 @@ struct edid {
> >
> > /* Short Audio Descriptor */
> > struct cea_sad {
> > - u8 format;
> > + u8 format; /* See HDMI_AUDIO_CODING_TYPE_* */
> > u8 channels; /* max number of channels - 1 */
> > - u8 freq;
> > + u8 freq; /* See CEA_SAD_FREQ_* */
> > u8 byte2; /* meaning depends on format */
> > };
> >
> > +#define CEA_SAD_FREQ_32KHZ BIT(0)
> > +#define CEA_SAD_FREQ_44KHZ BIT(1)
> > +#define CEA_SAD_FREQ_48KHZ BIT(2)
> > +#define CEA_SAD_FREQ_88KHZ BIT(3)
> > +#define CEA_SAD_FREQ_96KHZ BIT(4)
> > +#define CEA_SAD_FREQ_176KHZ BIT(5)
> > +#define CEA_SAD_FREQ_192KHZ BIT(6)
> > +
> > +#define CEA_SAD_UNCOMPRESSED_WORD_16BIT BIT(0)
> > +#define CEA_SAD_UNCOMPRESSED_WORD_20BIT BIT(1)
> > +#define CEA_SAD_UNCOMPRESSED_WORD_24BIT BIT(2)
> > +
> > struct drm_encoder;
> > struct drm_connector;
> > struct drm_connector_state;
> > @@ -374,6 +386,8 @@ struct drm_display_mode;
> >
> > int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
> > int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);
> > +int drm_cea_sad_get_sample_rate(struct cea_sad *sad);
> > +int drm_cea_sad_get_uncompressed_word_length(struct cea_sad *sad);
> > int drm_av_sync_delay(struct drm_connector *connector,
> > const struct drm_display_mode *mode);
> >
> > --
> > 2.33.0
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver
2021-09-06 19:35 ` [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver Markus Schneider-Pargmann
2021-09-06 20:39 ` Sam Ravnborg
@ 2021-09-07 8:47 ` Philipp Zabel
2021-09-09 9:16 ` Markus Schneider-Pargmann
2021-09-09 23:37 ` Chun-Kuang Hu
2 siblings, 1 reply; 22+ messages in thread
From: Philipp Zabel @ 2021-09-07 8:47 UTC (permalink / raw)
To: Markus Schneider-Pargmann, Chun-Kuang Hu
Cc: Sam Ravnborg, dri-devel, linux-mediatek, linux-arm-kernel
Hi Markus,
On Mon, 2021-09-06 at 21:35 +0200, Markus Schneider-Pargmann wrote:
> This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
>
> It supports both functional units on the mt8195, the embedded
> DisplayPort as well as the external DisplayPort units. It offers
> hot-plug-detection, audio up to 8 channels, and DisplayPort 1.4 with up
> to 4 lanes.
>
> This driver is based on an initial version by
> Jason-JH.Lin <jason-jh.lin@mediatek.com>.
>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
[...]
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
> new file mode 100644
> index 000000000000..1bd07c8d2f69
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -0,0 +1,2881 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Copyright (c) 2021 BayLibre
> + */
> +
[...]
> +#include <linux/component.h>
[...]
> +#include <linux/extcon.h>
> +#include <linux/extcon-provider.h>
[...]
> +#include <linux/kthread.h>
> +#include <linux/mfd/syscon.h>
[...]
> +#include <linux/of_gpio.h>
> +#include <linux/of_graph.h>
[...]
> +#include <linux/phy/phy.h>
The list of included headers could be pruned a bit, from a quick look it
seems like neither of these are actually used.
[...]
> +static void mtk_dp_ssc_enable(struct mtk_dp *mtk_dp, bool enable)
> +{
> + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, DP_PWR_STATE_BANDGAP,
> + DP_PWR_STATE_MASK);
> + mtk_dp_update_bits(mtk_dp, DP_PHY_DIG_PLL_CTL_1,
> + enable ? TPLL_SSC_EN : 0, TPLL_SSC_EN);
> + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
> + DP_PWR_STATE_BANDGAP_TPLL_LANE, DP_PWR_STATE_MASK);
> +
> + udelay(50);
Can usleep_range() be used here? Same for the other delays.
[...]
> +static void mtk_dp_hpd_sink_event(struct mtk_dp *mtk_dp)
> +{
[...]
> +
> + if (DP_GET_SINK_COUNT(sink_count) &&
> + (link_status[2] & DP_DOWNSTREAM_PORT_STATUS_CHANGED)) {
> + mtk_dp->train_info.check_cap_count = 0;
> + kfree(mtk_dp->edid);
> + mtk_dp->edid = NULL;
Should this be protect by a lock? This looks like it could race with the
access in mtk_dp_edid_parse_audio_capabilities() or mtk_dp_get_edid()
[...]
> +static int mtk_dp_train_handler(struct mtk_dp *mtk_dp)
> +{
> + int ret = 0;
> +
> + ret = mtk_dp_train_hpd_handle(mtk_dp);
> +
> + if (!mtk_dp->train_info.cable_plugged_in)
> + return -ENODEV;
> +
> + if (mtk_dp->train_state == MTK_DP_TRAIN_STATE_NORMAL)
> + return ret;
> +
> + switch (mtk_dp->train_state) {
[...]
> + case MTK_DP_TRAIN_STATE_TRAINING:
> + ret = mtk_dp_train_start(mtk_dp);
> + if (!ret) {
> + mtk_dp_video_mute(mtk_dp, true);
> + mtk_dp_audio_mute(mtk_dp, true);
> + mtk_dp->train_state = MTK_DP_TRAIN_STATE_CHECKTIMING;
> + mtk_dp_fec_enable(mtk_dp, mtk_dp->has_fec);
> + } else if (ret != -EAGAIN)
> + mtk_dp->train_state = MTK_DP_TRAIN_STATE_DPIDLE;
A small whitespace issue and missing braces.
Consider running this through checkpatch.pl --strict once for style
issues.
[...]
> +static irqreturn_t mtk_dp_hpd_event(int hpd, void *dev)
> +{
> + struct mtk_dp *mtk_dp = dev;
> + uint32_t irq_status;
> +
> + irq_status = mtk_dp_read(mtk_dp, MTK_DP_TOP_IRQ_STATUS);
> +
> + if (!irq_status)
> + return IRQ_HANDLED;
This check seems superfluous given that only the
RGS_IRQ_STATUS_TRANSMITTER bit is checked right below:
> + if (irq_status & RGS_IRQ_STATUS_TRANSMITTER)
> + return mtk_dp_hpd_isr_handler(mtk_dp);
> +
> + return IRQ_HANDLED;
> +}
[...]
> +static struct edid *mtk_dp_get_edid(struct drm_bridge *bridge,
> + struct drm_connector *connector)
> +{
> + struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
> + bool pre_enabled = mtk_dp->pre_enabled;
> +
> + if (mtk_dp->edid)
> + kfree(mtk_dp->edid);
Unnecessary check, kfree() accepts NULL.
regards
Philipp
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 4/6] video/hdmi: Add audio_infoframe packing for DP
2021-09-06 20:30 ` Sam Ravnborg
@ 2021-09-07 8:59 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-07 8:59 UTC (permalink / raw)
To: Sam Ravnborg
Cc: Chun-Kuang Hu, Philipp Zabel, dri-devel, linux-mediatek,
linux-arm-kernel
Hi Sam,
On Mon, Sep 06, 2021 at 10:30:26PM +0200, Sam Ravnborg wrote:
> Hi Markus,
>
> On Mon, Sep 06, 2021 at 09:35:27PM +0200, Markus Schneider-Pargmann wrote:
> > Similar to HDMI, DP uses audio infoframes as well which are structured
> > very similar to the HDMI ones.
> >
> > This patch adds a helper function to pack the HDMI audio infoframe for
> > DP, called hdmi_audio_infoframe_pack_for_dp().
> > hdmi_audio_infoframe_pack_only() is split into two parts. One of them
> > packs the payload only and can be used for HDMI and DP.
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > ---
> > drivers/video/hdmi.c | 87 +++++++++++++++++++++++++++++++++++---------
> > include/linux/hdmi.h | 4 ++
> > 2 files changed, 73 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
> > index 947be761dfa4..59c4341549e4 100644
> > --- a/drivers/video/hdmi.c
> > +++ b/drivers/video/hdmi.c
> > @@ -387,6 +387,28 @@ int hdmi_audio_infoframe_check(struct hdmi_audio_infoframe *frame)
> > }
> > EXPORT_SYMBOL(hdmi_audio_infoframe_check);
> >
> > +static void
> > +hdmi_audio_infoframe_pack_payload(const struct hdmi_audio_infoframe *frame,
> > + u8 *buffer)
> > +{
> > + u8 channels;
> > +
> > + if (frame->channels >= 2)
> > + channels = frame->channels - 1;
> > + else
> > + channels = 0;
> > +
> > + buffer[0] = ((frame->coding_type & 0xf) << 4) | (channels & 0x7);
> > + buffer[1] = ((frame->sample_frequency & 0x7) << 2) |
> > + (frame->sample_size & 0x3);
> > + buffer[2] = frame->coding_type_ext & 0x1f;
> > + buffer[3] = frame->channel_allocation;
> > + buffer[4] = (frame->level_shift_value & 0xf) << 3;
> > +
> > + if (frame->downmix_inhibit)
> > + buffer[4] |= BIT(7);
> > +}
> > +
> > /**
> > * hdmi_audio_infoframe_pack_only() - write HDMI audio infoframe to binary buffer
> > * @frame: HDMI audio infoframe
> > @@ -404,7 +426,6 @@ EXPORT_SYMBOL(hdmi_audio_infoframe_check);
> > ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *frame,
> > void *buffer, size_t size)
> > {
> > - unsigned char channels;
> > u8 *ptr = buffer;
> > size_t length;
> > int ret;
> > @@ -420,28 +441,13 @@ ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *frame,
> >
> > memset(buffer, 0, size);
> >
> > - if (frame->channels >= 2)
> > - channels = frame->channels - 1;
> > - else
> > - channels = 0;
> > -
> > ptr[0] = frame->type;
> > ptr[1] = frame->version;
> > ptr[2] = frame->length;
> > ptr[3] = 0; /* checksum */
> >
> > - /* start infoframe payload */
> > - ptr += HDMI_INFOFRAME_HEADER_SIZE;
> > -
> > - ptr[0] = ((frame->coding_type & 0xf) << 4) | (channels & 0x7);
> > - ptr[1] = ((frame->sample_frequency & 0x7) << 2) |
> > - (frame->sample_size & 0x3);
> > - ptr[2] = frame->coding_type_ext & 0x1f;
> > - ptr[3] = frame->channel_allocation;
> > - ptr[4] = (frame->level_shift_value & 0xf) << 3;
> > -
> > - if (frame->downmix_inhibit)
> > - ptr[4] |= BIT(7);
> > + hdmi_audio_infoframe_pack_payload(frame,
> > + ptr + HDMI_INFOFRAME_HEADER_SIZE);
> >
> > hdmi_infoframe_set_checksum(buffer, length);
> >
> > @@ -479,6 +485,51 @@ ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_infoframe *frame,
> > }
> > EXPORT_SYMBOL(hdmi_audio_infoframe_pack);
> >
> > +/**
> > + * hdmi_audio_infoframe_pack_for_dp - Pack a HDMI Audio infoframe for
> > + * displayport
> > + *
> > + * @frame HDMI Audio infoframe
> > + * @header Header buffer to be used
> > + * @header_size Size of header buffer
> > + * @data Data buffer to be used
> > + * @data_size Size of data buffer
> > + * @dp_version Display Port version to be encoded in the header
> > + *
> > + * Packs a HDMI Audio Infoframe to be sent over Display Port. This function
> > + * fills both header and data buffer with the required data.
> > + *
> > + * Return: Number of total written bytes or a negative errno on failure.
> > + */
> > +ssize_t hdmi_audio_infoframe_pack_for_dp(struct hdmi_audio_infoframe *frame,
> > + void *header, size_t header_size,
> > + void *data, size_t data_size,
> > + u8 dp_version)
> > +{
> > + int ret;
> > + u8 *hdr_ptr = header;
> > +
> > + ret = hdmi_audio_infoframe_check(frame);
> > + if (ret)
> > + return ret;
> > +
> > + if (header_size < 4 || data_size < frame->length)
> > + return -ENOSPC;
> > +
> > + memset(header, 0, header_size);
> > + memset(data, 0, data_size);
> > +
> > + // Secondary-data packet header
> > + hdr_ptr[1] = frame->type;
> > + hdr_ptr[2] = 0x1B; // As documented by DP spec for Secondary-data Packets
> Any constant we could use or define and use here?
> Hard coding 0x1b is the less desireable option.
I couldn't find a constant for this, but I will add one.
Also thanks to looking for these defines, I found a struct dp_sdp that
could be used instead of the header and data pointers which I would
prefer, so I will fix that for the next version.
Thanks for your feedback.
Best,
Markus
>
> Sam
>
> > + hdr_ptr[3] = (dp_version & 0x3f) << 2;
> > +
> > + hdmi_audio_infoframe_pack_payload(frame, data);
> > +
> > + return frame->length + 4;
> > +}
> > +EXPORT_SYMBOL(hdmi_audio_infoframe_pack_for_dp);
> > +
> > /**
> > * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe
> > * @frame: HDMI vendor infoframe
> > diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
> > index c8ec982ff498..f576a0b08c85 100644
> > --- a/include/linux/hdmi.h
> > +++ b/include/linux/hdmi.h
> > @@ -334,6 +334,10 @@ struct hdmi_audio_infoframe {
> > int hdmi_audio_infoframe_init(struct hdmi_audio_infoframe *frame);
> > ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_infoframe *frame,
> > void *buffer, size_t size);
> > +ssize_t hdmi_audio_infoframe_pack_for_dp(struct hdmi_audio_infoframe *frame,
> > + void *header, size_t header_size,
> > + void *data, size_t data_size,
> > + u8 dp_version);
> > ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *frame,
> > void *buffer, size_t size);
> > int hdmi_audio_infoframe_check(struct hdmi_audio_infoframe *frame);
> > --
> > 2.33.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver
2021-09-07 8:47 ` Philipp Zabel
@ 2021-09-09 9:16 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-09 9:16 UTC (permalink / raw)
To: Philipp Zabel
Cc: Chun-Kuang Hu, Sam Ravnborg, dri-devel, linux-mediatek, linux-arm-kernel
Hi Philipp,
On Tue, Sep 07, 2021 at 10:47:41AM +0200, Philipp Zabel wrote:
> Hi Markus,
>
> On Mon, 2021-09-06 at 21:35 +0200, Markus Schneider-Pargmann wrote:
> > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
> >
> > It supports both functional units on the mt8195, the embedded
> > DisplayPort as well as the external DisplayPort units. It offers
> > hot-plug-detection, audio up to 8 channels, and DisplayPort 1.4 with up
> > to 4 lanes.
> >
> > This driver is based on an initial version by
> > Jason-JH.Lin <jason-jh.lin@mediatek.com>.
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > ---
> [...]
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
> > new file mode 100644
> > index 000000000000..1bd07c8d2f69
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> > @@ -0,0 +1,2881 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2019 MediaTek Inc.
> > + * Copyright (c) 2021 BayLibre
> > + */
> > +
> [...]
> > +#include <linux/component.h>
> [...]
> > +#include <linux/extcon.h>
> > +#include <linux/extcon-provider.h>
> [...]
> > +#include <linux/kthread.h>
> > +#include <linux/mfd/syscon.h>
> [...]
> > +#include <linux/of_gpio.h>
> > +#include <linux/of_graph.h>
> [...]
> > +#include <linux/phy/phy.h>
>
> The list of included headers could be pruned a bit, from a quick look it
> seems like neither of these are actually used.
Thank you. I fixed the includes for the next version.
>
> [...]
> > +static void mtk_dp_ssc_enable(struct mtk_dp *mtk_dp, bool enable)
> > +{
> > + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, DP_PWR_STATE_BANDGAP,
> > + DP_PWR_STATE_MASK);
> > + mtk_dp_update_bits(mtk_dp, DP_PHY_DIG_PLL_CTL_1,
> > + enable ? TPLL_SSC_EN : 0, TPLL_SSC_EN);
> > + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
> > + DP_PWR_STATE_BANDGAP_TPLL_LANE, DP_PWR_STATE_MASK);
> > +
> > + udelay(50);
>
> Can usleep_range() be used here? Same for the other delays.
Yes, thanks, I replaced it here and everywhere else.
>
> [...]
> > +static void mtk_dp_hpd_sink_event(struct mtk_dp *mtk_dp)
> > +{
> [...]
> > +
> > + if (DP_GET_SINK_COUNT(sink_count) &&
> > + (link_status[2] & DP_DOWNSTREAM_PORT_STATUS_CHANGED)) {
> > + mtk_dp->train_info.check_cap_count = 0;
> > + kfree(mtk_dp->edid);
> > + mtk_dp->edid = NULL;
>
> Should this be protect by a lock? This looks like it could race with the
> access in mtk_dp_edid_parse_audio_capabilities() or mtk_dp_get_edid()
Completely right, I guarded all edid accesses with a mutex now. Thanks.
>
> [...]
> > +static int mtk_dp_train_handler(struct mtk_dp *mtk_dp)
> > +{
> > + int ret = 0;
> > +
> > + ret = mtk_dp_train_hpd_handle(mtk_dp);
> > +
> > + if (!mtk_dp->train_info.cable_plugged_in)
> > + return -ENODEV;
> > +
> > + if (mtk_dp->train_state == MTK_DP_TRAIN_STATE_NORMAL)
> > + return ret;
> > +
> > + switch (mtk_dp->train_state) {
> [...]
> > + case MTK_DP_TRAIN_STATE_TRAINING:
> > + ret = mtk_dp_train_start(mtk_dp);
> > + if (!ret) {
> > + mtk_dp_video_mute(mtk_dp, true);
> > + mtk_dp_audio_mute(mtk_dp, true);
> > + mtk_dp->train_state = MTK_DP_TRAIN_STATE_CHECKTIMING;
> > + mtk_dp_fec_enable(mtk_dp, mtk_dp->has_fec);
> > + } else if (ret != -EAGAIN)
> > + mtk_dp->train_state = MTK_DP_TRAIN_STATE_DPIDLE;
>
> A small whitespace issue and missing braces.
Thanks for spotting, fixed.
>
> Consider running this through checkpatch.pl --strict once for style
> issues.
Thanks for the tip, I didn't know about --strict. I now added it to my
editor tooling. Interesting thing: It picked up the missing braces as
well as all the udelays, but not the extra space before else.
>
> [...]
> > +static irqreturn_t mtk_dp_hpd_event(int hpd, void *dev)
> > +{
> > + struct mtk_dp *mtk_dp = dev;
> > + uint32_t irq_status;
> > +
> > + irq_status = mtk_dp_read(mtk_dp, MTK_DP_TOP_IRQ_STATUS);
> > +
> > + if (!irq_status)
> > + return IRQ_HANDLED;
>
> This check seems superfluous given that only the
> RGS_IRQ_STATUS_TRANSMITTER bit is checked right below:
Thanks, I removed it.
>
> > + if (irq_status & RGS_IRQ_STATUS_TRANSMITTER)
> > + return mtk_dp_hpd_isr_handler(mtk_dp);
> > +
> > + return IRQ_HANDLED;
> > +}
> [...]
> > +static struct edid *mtk_dp_get_edid(struct drm_bridge *bridge,
> > + struct drm_connector *connector)
> > +{
> > + struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
> > + bool pre_enabled = mtk_dp->pre_enabled;
> > +
> > + if (mtk_dp->edid)
> > + kfree(mtk_dp->edid);
>
> Unnecessary check, kfree() accepts NULL.
Fixed.
Thank you Philipp for the review.
Best,
Markus
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver
2021-09-06 20:39 ` Sam Ravnborg
@ 2021-09-09 12:45 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-09 12:45 UTC (permalink / raw)
To: Sam Ravnborg
Cc: Chun-Kuang Hu, Philipp Zabel, dri-devel, linux-mediatek,
linux-arm-kernel
Hi Sam,
On Mon, Sep 06, 2021 at 10:39:21PM +0200, Sam Ravnborg wrote:
> Hi Markus,
>
> On Mon, Sep 06, 2021 at 09:35:29PM +0200, Markus Schneider-Pargmann wrote:
> > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
> >
> > It supports both functional units on the mt8195, the embedded
> > DisplayPort as well as the external DisplayPort units. It offers
> > hot-plug-detection, audio up to 8 channels, and DisplayPort 1.4 with up
> > to 4 lanes.
> >
> > This driver is based on an initial version by
> > Jason-JH.Lin <jason-jh.lin@mediatek.com>.
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > ---
> >
> > Notes:
> > Changes RFC -> v1:
> > - Removed unused register definitions.
> > - Replaced workqueue with threaded irq.
> > - Removed connector code.
> > - Move to atomic_* drm functions.
> > - General cleanups of the code.
> > - Remove unused select GENERIC_PHY.
> >
> > drivers/gpu/drm/mediatek/Kconfig | 6 +
> > drivers/gpu/drm/mediatek/Makefile | 2 +
> > drivers/gpu/drm/mediatek/mtk_dp.c | 2881 +++++++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_dp_reg.h | 580 +++++
> > 4 files changed, 3469 insertions(+)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h
> >
>
>
> > +
> > +static const struct drm_bridge_funcs mtk_dp_bridge_funcs = {
> > + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> > + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> > + .atomic_reset = drm_atomic_helper_bridge_reset,
> > + .attach = mtk_dp_bridge_attach,
> > + .detach = mtk_dp_bridge_detach,
> > + .pre_enable = mtk_dp_bridge_pre_enable,
> Use the atomic variant here as pre_enable is deprecated.
>
> > + .atomic_enable = mtk_dp_bridge_atomic_enable,
> > + .atomic_disable = mtk_dp_bridge_atomic_disable,
> > + .post_disable = mtk_dp_bridge_post_disable,
> Use the atomic variant here as .post_disable is deprecated.
Thanks, I got rid of both pre_enable and post_disable as well now.
>
> > + .get_edid = mtk_dp_get_edid,
> > + .detect = mtk_dp_bdg_detect,
> > +};
>
> Everything else I skimmed looked fine. But it was a quick skim so..
Thanks for taking the time to have a look.
Best,
Markus
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 1/6] dt-bindings: mediatek,dpi: Add mt8195 dpintf
2021-09-06 20:14 ` Sam Ravnborg
@ 2021-09-09 12:49 ` Markus Schneider-Pargmann
0 siblings, 0 replies; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-09 12:49 UTC (permalink / raw)
To: Sam Ravnborg
Cc: Chun-Kuang Hu, Philipp Zabel, dri-devel, linux-mediatek,
linux-arm-kernel
Hi Sam,
On Mon, Sep 06, 2021 at 10:14:05PM +0200, Sam Ravnborg wrote:
> Hi Markus,
>
> On Mon, Sep 06, 2021 at 09:35:24PM +0200, Markus Schneider-Pargmann wrote:
> > DP_INTF is similar to the actual dpi. They differ in some points
> > regarding registers and what needs to be set but the function blocks
> > itself are similar in design.
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
>
> I fail to see why they share the same dt-schema as the main content in
> the schema is the clocks and they differ.
>
> A new mediatek,dpintf schema seems more appropriate.
Good idea, I will do that. Thank you.
Best,
Markus
>
> I recall I though so when reading the RFC variant but failed to comment on it.
>
> Sam
>
> > ---
> > .../display/mediatek/mediatek,dpi.yaml | 43 ++++++++++++++++---
> > 1 file changed, 37 insertions(+), 6 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> > index dd2896a40ff0..1a158b719ce6 100644
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> > @@ -4,7 +4,7 @@
> > $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
> > $schema: http://devicetree.org/meta-schemas/core.yaml#
> >
> > -title: mediatek DPI Controller Device Tree Bindings
> > +title: mediatek DPI/DP_INTF Controller Device Tree Bindings
> >
> > maintainers:
> > - CK Hu <ck.hu@mediatek.com>
> > @@ -13,7 +13,8 @@ maintainers:
> > description: |
> > The Mediatek DPI function block is a sink of the display subsystem and
> > provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
> > - output bus.
> > + output bus. The Mediatek DP_INTF is a similar function block that is
> > + connected to the (embedded) display port function block.
> >
> > properties:
> > compatible:
> > @@ -23,6 +24,7 @@ properties:
> > - mediatek,mt8173-dpi
> > - mediatek,mt8183-dpi
> > - mediatek,mt8192-dpi
> > + - mediatek,mt8195-dpintf
> >
> > reg:
> > maxItems: 1
> > @@ -37,10 +39,11 @@ properties:
> > - description: DPI PLL
> >
> > clock-names:
> > - items:
> > - - const: pixel
> > - - const: engine
> > - - const: pll
> > + description:
> > + For dpi clocks pixel, engine and pll are required. For dpintf pixel,
> > + hf_fmm and hf_fdp are required.
> > + minItems: 3
> > + maxItems: 3
> >
> > pinctrl-0: true
> > pinctrl-1: true
> > @@ -64,6 +67,34 @@ required:
> > - clock-names
> > - port
> >
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - mediatek,mt8195-dpintf
> > + then:
> > + properties:
> > + clocks:
> > + minItems: 3
> > + maxItems: 3
> > + clock-names:
> > + items:
> > + - const: pixel
> > + - const: hf_fmm
> > + - const: hf_fdp
> > + else:
> > + properties:
> > + clocks:
> > + minItems: 3
> > + maxItems: 3
> > + clock-names:
> > + items:
> > + - const: pixel
> > + - const: engine
> > + - const: pll
> > +
> > additionalProperties: false
> >
> > examples:
> > --
> > 2.33.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver
2021-09-06 19:35 ` [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver Markus Schneider-Pargmann
2021-09-06 20:39 ` Sam Ravnborg
2021-09-07 8:47 ` Philipp Zabel
@ 2021-09-09 23:37 ` Chun-Kuang Hu
2021-09-10 5:36 ` Markus Schneider-Pargmann
2 siblings, 1 reply; 22+ messages in thread
From: Chun-Kuang Hu @ 2021-09-09 23:37 UTC (permalink / raw)
To: Markus Schneider-Pargmann
Cc: Chun-Kuang Hu, Philipp Zabel, Sam Ravnborg, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Markus:
Markus Schneider-Pargmann <msp@baylibre.com> 於 2021年9月7日 週二 上午3:37寫道：
>
> This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
>
> It supports both functional units on the mt8195, the embedded
> DisplayPort as well as the external DisplayPort units. It offers
> hot-plug-detection, audio up to 8 channels, and DisplayPort 1.4 with up
> to 4 lanes.
>
> This driver is based on an initial version by
> Jason-JH.Lin <jason-jh.lin@mediatek.com>.
>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
>
> Notes:
> Changes RFC -> v1:
> - Removed unused register definitions.
> - Replaced workqueue with threaded irq.
> - Removed connector code.
> - Move to atomic_* drm functions.
> - General cleanups of the code.
> - Remove unused select GENERIC_PHY.
>
> drivers/gpu/drm/mediatek/Kconfig | 6 +
> drivers/gpu/drm/mediatek/Makefile | 2 +
> drivers/gpu/drm/mediatek/mtk_dp.c | 2881 +++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_dp_reg.h | 580 +++++
> 4 files changed, 3469 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h
>
[snip]
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> new file mode 100644
> index 000000000000..26ed3b66da91
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> @@ -0,0 +1,580 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Copyright (c) 2021 BayLibre
> + */
> +#ifndef _MTK_DP_REG_H_
> +#define _MTK_DP_REG_H_
> +
> +#define MTK_DP_SIP_CONTROL_AARCH32 0x82000523
> +# define MTK_DP_SIP_ATF_VIDEO_UNMUTE 0x20
> +# define MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE 0x21
> +
> +#define TOP_OFFSET 0x2000
> +#define ENC0_OFFSET 0x3000
> +#define ENC1_OFFSET 0x3200
> +#define TRANS_OFFSET 0x3400
> +#define AUX_OFFSET 0x3600
> +#define SEC_OFFSET 0x4000
> +
> +#define MTK_DP_HPD_DISCONNECT BIT(1)
> +#define MTK_DP_HPD_CONNECT BIT(2)
> +#define MTK_DP_HPD_INTERRUPT BIT(3)
> +
> +#define MTK_DP_ENC0_P0_3000 (ENC0_OFFSET + 0x000)
> +# define LANE_NUM_DP_ENC0_P0_MASK 0x3
> +# define VIDEO_MUTE_SW_DP_ENC0_P0_MASK 0x4
> +# define VIDEO_MUTE_SW_DP_ENC0_P0_SHIFT 2
> +# define VIDEO_MUTE_SEL_DP_ENC0_P0_MASK 0x8
> +# define VIDEO_MUTE_SEL_DP_ENC0_P0_SHIFT 3
> +# define ENHANCED_FRAME_EN_DP_ENC0_P0_MASK 0x10
> +# define ENHANCED_FRAME_EN_DP_ENC0_P0_SHIFT 4
> +
> +#define MTK_DP_ENC0_P0_3004 (ENC0_OFFSET + 0x004)
> +# define VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK 0x100
> +# define VIDEO_M_CODE_SEL_DP_ENC0_P0_SHIFT 8
> +# define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0_MASK 0x200
> +# define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0_SHIFT 9
> +
> +#define MTK_DP_ENC0_P0_3008 (ENC0_OFFSET + 0x008)
> +# define VIDEO_M_CODE_SW_0_DP_ENC0_P0_MASK 0xffff
> +
> +#define MTK_DP_ENC0_P0_300C (ENC0_OFFSET + 0x00C)
> +# define VIDEO_M_CODE_SW_1_DP_ENC0_P0_MASK 0xff
> +
> +#define MTK_DP_ENC0_P0_3010 (ENC0_OFFSET + 0x010)
> +# define HTOTAL_SW_DP_ENC0_P0_MASK 0xffff
> +
> +#define MTK_DP_ENC0_P0_3014 (ENC0_OFFSET + 0x014)
> +# define VTOTAL_SW_DP_ENC0_P0_MASK 0xffff
> +
> +#define MTK_DP_ENC0_P0_3018 (ENC0_OFFSET + 0x018)
> +# define HSTART_SW_DP_ENC0_P0_MASK 0xffff
> +
> +#define MTK_DP_ENC0_P0_301C (ENC0_OFFSET + 0x01C)
> +# define VSTART_SW_DP_ENC0_P0_MASK 0xffff
> +
> +#define MTK_DP_ENC0_P0_3020 (ENC0_OFFSET + 0x020)
> +# define HWIDTH_SW_DP_ENC0_P0_MASK 0xffff
> +
> +#define MTK_DP_ENC0_P0_3024 (ENC0_OFFSET + 0x024)
> +# define VHEIGHT_SW_DP_ENC0_P0_MASK 0xffff
> +
> +#define MTK_DP_ENC0_P0_3028 (ENC0_OFFSET + 0x028)
> +# define HSW_SW_DP_ENC0_P0_MASK 0x7fff
> +# define HSW_SW_DP_ENC0_P0_SHIFT 0
> +# define HSP_SW_DP_ENC0_P0_MASK 0x8000
> +
> +#define MTK_DP_ENC0_P0_302C (ENC0_OFFSET + 0x02C)
> +# define VSW_SW_DP_ENC0_P0_MASK 0x7fff
> +# define VSW_SW_DP_ENC0_P0_SHIFT 0
> +# define VSP_SW_DP_ENC0_P0_MASK 0x8000
> +
> +#define MTK_DP_ENC0_P0_3030 (ENC0_OFFSET + 0x030)
> +# define HTOTAL_SEL_DP_ENC0_P0_SHIFT 0
> +# define VTOTAL_SEL_DP_ENC0_P0_SHIFT 1
> +# define HSTART_SEL_DP_ENC0_P0_SHIFT 2
> +# define VSTART_SEL_DP_ENC0_P0_SHIFT 3
> +# define HWIDTH_SEL_DP_ENC0_P0_SHIFT 4
> +# define VHEIGHT_SEL_DP_ENC0_P0_SHIFT 5
> +# define HSP_SEL_DP_ENC0_P0_SHIFT 6
> +# define HSW_SEL_DP_ENC0_P0_SHIFT 7
> +# define VSP_SEL_DP_ENC0_P0_SHIFT 8
> +# define VSW_SEL_DP_ENC0_P0_SHIFT 9
> +# define VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0_MASK 0x800
> +# define VBID_AUDIO_MUTE_SW_DP_ENC0_P0_SHIFT 11
> +# define VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0_MASK 0x1000
> +# define VBID_AUDIO_MUTE_SEL_DP_ENC0_P0_SHIFT 12
> +
> +#define MTK_DP_ENC0_P0_3034 (ENC0_OFFSET + 0x034)
> +
> +#define MTK_DP_ENC0_P0_3038 (ENC0_OFFSET + 0x038)
> +# define VIDEO_SOURCE_SEL_DP_ENC0_P0_MASK 0x800
> +# define VIDEO_SOURCE_SEL_DP_ENC0_P0_SHIFT 11
> +
> +#define MTK_DP_ENC0_P0_303C (ENC0_OFFSET + 0x03C)
> +# define SRAM_START_READ_THRD_DP_ENC0_P0_MASK 0x3f
> +# define SRAM_START_READ_THRD_DP_ENC0_P0_SHIFT 0
> +# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK 0x700
> +# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_SHIFT 8
> +# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_16BIT (0 << VIDEO_COLOR_DEPTH_DP_ENC0_P0_SHIFT)
> +# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_12BIT (1 << VIDEO_COLOR_DEPTH_DP_ENC0_P0_SHIFT)
> +# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_10BIT (2 << VIDEO_COLOR_DEPTH_DP_ENC0_P0_SHIFT)
> +# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_8BIT (3 << VIDEO_COLOR_DEPTH_DP_ENC0_P0_SHIFT)
> +# define VIDEO_COLOR_DEPTH_DP_ENC0_P0_6BIT (4 << VIDEO_COLOR_DEPTH_DP_ENC0_P0_SHIFT)
> +# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK 0x7000
> +# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_SHIFT 12
> +# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB (0 << PIXEL_ENCODE_FORMAT_DP_ENC0_P0_SHIFT)
> +# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422 (1 << PIXEL_ENCODE_FORMAT_DP_ENC0_P0_SHIFT)
> +# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR420 (2 << PIXEL_ENCODE_FORMAT_DP_ENC0_P0_SHIFT)
> +# define VIDEO_MN_GEN_EN_DP_ENC0_P0_MASK 0x8000
> +# define VIDEO_MN_GEN_EN_DP_ENC0_P0_SHIFT 15
> +
> +#define MTK_DP_ENC0_P0_3040 (ENC0_OFFSET + 0x040)
> +# define SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK 0xfff
> +# define SDP_DOWN_CNT_INIT_DP_ENC0_P0_SHIFT 0
> +
> +#define MTK_DP_ENC0_P0_3044 (ENC0_OFFSET + 0x044)
> +# define VIDEO_N_CODE_0_DP_ENC0_P0_MASK 0xffff
> +
> +#define MTK_DP_ENC0_P0_3048 (ENC0_OFFSET + 0x048)
> +# define VIDEO_N_CODE_1_DP_ENC0_P0_MASK 0xff
> +
> +#define MTK_DP_ENC0_P0_304C (ENC0_OFFSET + 0x04C)
> +# define VBID_VIDEO_MUTE_DP_ENC0_P0_MASK 0x4
> +# define SDP_VSYNC_RISING_MASK_DP_ENC0_P0_MASK 0x100
> +
> +#define MTK_DP_ENC0_P0_3050 (ENC0_OFFSET + 0x050)
> +# define VIDEO_N_CODE_MN_GEN_0_DP_ENC0_P0_MASK 0xffff
> +
> +#define MTK_DP_ENC0_P0_3054 (ENC0_OFFSET + 0x054)
> +# define VIDEO_N_CODE_MN_GEN_1_DP_ENC0_P0_MASK 0xff
> +
> +#define MTK_DP_ENC0_P0_3064 (ENC0_OFFSET + 0x064)
> +# define HDE_NUM_LAST_DP_ENC0_P0_MASK 0xffff
> +
> +#define MTK_DP_ENC0_P0_3088 (ENC0_OFFSET + 0x088)
> +# define AU_EN_DP_ENC0_P0_MASK 0x40
> +# define AU_EN_DP_ENC0_P0_SHIFT 6
> +# define AUDIO_8CH_EN_DP_ENC0_P0_MASK 0x80
> +# define AUDIO_8CH_SEL_DP_ENC0_P0_MASK 0x100
> +# define AUDIO_2CH_EN_DP_ENC0_P0_MASK 0x4000
> +# define AUDIO_2CH_SEL_DP_ENC0_P0_MASK 0x8000
> +
> +#define MTK_DP_ENC0_P0_308C (ENC0_OFFSET + 0x08C)
> +# define CH_STATUS_0_DP_ENC0_P0_MASK 0xffff
> +
> +#define MTK_DP_ENC0_P0_3090 (ENC0_OFFSET + 0x090)
> +# define CH_STATUS_1_DP_ENC0_P0_MASK 0xffff
> +
> +#define MTK_DP_ENC0_P0_3094 (ENC0_OFFSET + 0x094)
> +# define CH_STATUS_2_DP_ENC0_P0_MASK 0xff
> +
> +#define MTK_DP_ENC0_P0_30A0 (ENC0_OFFSET + 0x0A0)
> +
> +#define MTK_DP_ENC0_P0_30A4 (ENC0_OFFSET + 0x0A4)
> +# define AU_TS_CFG_DP_ENC0_P0_MASK 0xff
> +
> +#define MTK_DP_ENC0_P0_30A8 (ENC0_OFFSET + 0x0A8)
> +
> +#define MTK_DP_ENC0_P0_30AC (ENC0_OFFSET + 0x0AC)
> +
> +#define MTK_DP_ENC0_P0_30B0 (ENC0_OFFSET + 0x0B0)
> +
> +#define MTK_DP_ENC0_P0_30B4 (ENC0_OFFSET + 0x0B4)
> +# define ISRC_CFG_DP_ENC0_P0_MASK 0xff00
> +# define ISRC_CFG_DP_ENC0_P0_SHIFT 8
> +
> +#define MTK_DP_ENC0_P0_30B8 (ENC0_OFFSET + 0x0B8)
> +
> +#define MTK_DP_ENC0_P0_30BC (ENC0_OFFSET + 0x0BC)
> +# define ISRC_CONT_DP_ENC0_P0_MASK 0x1
> +# define ISRC_CONT_DP_ENC0_P0_SHIFT 0
> +# define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK 0x700
> +# define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT 8
> +
> +#define MTK_DP_ENC0_P0_30D8 (ENC0_OFFSET + 0x0D8)
> +
> +#define MTK_DP_ENC0_P0_312C (ENC0_OFFSET + 0x12C)
> +# define ASP_HB2_DP_ENC0_P0_MASK 0xff
> +# define ASP_HB3_DP_ENC0_P0_MASK 0xff00
> +# define ASP_HB3_DP_ENC0_P0_SHIFT 8
> +
> +#define MTK_DP_ENC0_P0_3130 (ENC0_OFFSET + 0x130)
> +
> +#define MTK_DP_ENC0_P0_3138 (ENC0_OFFSET + 0x138)
> +
> +#define MTK_DP_ENC0_P0_3154 (ENC0_OFFSET + 0x154)
> +# define PGEN_HTOTAL_DP_ENC0_P0_MASK 0x3fff
> +
> +#define MTK_DP_ENC0_P0_3158 (ENC0_OFFSET + 0x158)
> +# define PGEN_HSYNC_RISING_DP_ENC0_P0_MASK 0x3fff
> +
> +#define MTK_DP_ENC0_P0_315C (ENC0_OFFSET + 0x15C)
> +# define PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK 0x3fff
> +
> +#define MTK_DP_ENC0_P0_3160 (ENC0_OFFSET + 0x160)
> +# define PGEN_HFDE_START_DP_ENC0_P0_MASK 0x3fff
> +
> +#define MTK_DP_ENC0_P0_3164 (ENC0_OFFSET + 0x164)
> +# define PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK 0x3fff
> +
> +#define MTK_DP_ENC0_P0_3168 (ENC0_OFFSET + 0x168)
> +# define PGEN_VTOTAL_DP_ENC0_P0_MASK 0x1fff
> +
> +#define MTK_DP_ENC0_P0_316C (ENC0_OFFSET + 0x16C)
> +# define PGEN_VSYNC_RISING_DP_ENC0_P0_MASK 0x1fff
> +
> +#define MTK_DP_ENC0_P0_3170 (ENC0_OFFSET + 0x170)
> +# define PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK 0x1fff
> +
> +#define MTK_DP_ENC0_P0_3174 (ENC0_OFFSET + 0x174)
> +# define PGEN_VFDE_START_DP_ENC0_P0_MASK 0x1fff
> +
> +#define MTK_DP_ENC0_P0_3178 (ENC0_OFFSET + 0x178)
> +# define PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK 0x1fff
> +
> +#define MTK_DP_ENC0_P0_31B0 (ENC0_OFFSET + 0x1B0)
> +
> +#define MTK_DP_ENC0_P0_31C8 (ENC0_OFFSET + 0x1C8)
> +# define VSC_EXT_VESA_HB0_DP_ENC0_P0_MASK 0xff
> +# define VSC_EXT_VESA_HB1_DP_ENC0_P0_MASK 0xff00
> +# define VSC_EXT_VESA_HB1_DP_ENC0_P0_SHIFT 8
> +
> +#define MTK_DP_ENC0_P0_31CC (ENC0_OFFSET + 0x1CC)
> +# define VSC_EXT_VESA_HB2_DP_ENC0_P0_MASK 0xff
> +# define VSC_EXT_VESA_HB2_DP_ENC0_P0_SHIFT 0
> +# define VSC_EXT_VESA_HB3_DP_ENC0_P0_MASK 0xff00
> +
> +#define MTK_DP_ENC0_P0_31D0 (ENC0_OFFSET + 0x1D0)
> +# define VSC_EXT_CEA_HB0_DP_ENC0_P0_MASK 0xff
> +# define VSC_EXT_CEA_HB1_DP_ENC0_P0_MASK 0xff00
> +# define VSC_EXT_CEA_HB1_DP_ENC0_P0_SHIFT 8
> +
> +#define MTK_DP_ENC0_P0_31D4 (ENC0_OFFSET + 0x1D4)
> +# define VSC_EXT_CEA_HB2_DP_ENC0_P0_MASK 0xff
> +# define VSC_EXT_CEA_HB2_DP_ENC0_P0_SHIFT 0
> +# define VSC_EXT_CEA_HB3_DP_ENC0_P0_MASK 0xff00
> +
> +#define MTK_DP_ENC0_P0_31D8 (ENC0_OFFSET + 0x1D8)
> +# define VSC_EXT_VESA_NUM_DP_ENC0_P0_MASK 0x3f
> +# define VSC_EXT_VESA_NUM_DP_ENC0_P0_SHIFT 0
> +# define VSC_EXT_CEA_NUM_DP_ENC0_P0_MASK 0x3f00
> +# define VSC_EXT_CEA_NUM_DP_ENC0_P0_SHIFT 8
> +
> +#define MTK_DP_ENC0_P0_31DC (ENC0_OFFSET + 0x1DC)
> +# define HDR0_CFG_DP_ENC0_P0_MASK 0xff
> +# define HDR0_CFG_DP_ENC0_P0_SHIFT 0
> +
> +#define MTK_DP_ENC0_P0_31E8 (ENC0_OFFSET + 0x1E8)
> +
> +#define MTK_DP_ENC0_P0_31EC (ENC0_OFFSET + 0x1EC)
> +# define AUDIO_CH_SRC_SEL_DP_ENC0_P0_MASK 0x10
> +# define AUDIO_CH_SRC_SEL_DP_ENC0_P0_SHIFT 4
> +# define ISRC1_HB3_DP_ENC0_P0_MASK 0xff00
> +# define ISRC1_HB3_DP_ENC0_P0_SHIFT 8
> +
> +#define MTK_DP_ENC1_P0_3200 (ENC1_OFFSET + 0x000)
> +
> +#define MTK_DP_ENC1_P0_3280 (ENC1_OFFSET + 0x080)
> +# define SDP_PACKET_TYPE_DP_ENC1_P0_MASK 0x1f
> +# define SDP_PACKET_W_DP_ENC1_P0 0x20
> +# define SDP_PACKET_W_DP_ENC1_P0_MASK 0x20
> +# define SDP_PACKET_W_DP_ENC1_P0_SHIFT 5
> +
> +#define MTK_DP_ENC1_P0_328C (ENC1_OFFSET + 0x08C)
> +
> +#define MTK_DP_ENC1_P0_3290 (ENC1_OFFSET + 0x090)
> +
> +#define MTK_DP_ENC1_P0_32A0 (ENC1_OFFSET + 0x0A0)
> +
> +#define MTK_DP_ENC1_P0_32A4 (ENC1_OFFSET + 0x0A4)
> +
> +#define MTK_DP_ENC1_P0_3300 (ENC1_OFFSET + 0x100)
> +# define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK 0x300
> +# define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_SHIFT 8
> +
> +#define MTK_DP_ENC1_P0_3304 (ENC1_OFFSET + 0x104)
> +# define AU_PRTY_REGEN_DP_ENC1_P0_MASK 0x100
> +# define AU_CH_STS_REGEN_DP_ENC1_P0_MASK 0x200
> +# define AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK 0x1000
> +
> +#define MTK_DP_ENC1_P0_3324 (ENC1_OFFSET + 0x124)
> +# define AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK 0x300
> +# define AUDIO_SOURCE_MUX_DP_ENC1_P0_SHIFT 8
> +# define AUDIO_SOURCE_MUX_DP_ENC1_P0_DPRX (0 << AUDIO_SOURCE_MUX_DP_ENC1_P0_SHIFT)
> +
> +#define MTK_DP_ENC1_P0_3364 (ENC1_OFFSET + 0x164)
> +# define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK 0xfff
> +# define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_SHIFT 0
> +# define FIFO_READ_START_POINT_DP_ENC1_P0_MASK 0xf000
> +# define FIFO_READ_START_POINT_DP_ENC1_P0_SHIFT 12
> +
> +#define MTK_DP_ENC1_P0_3368 (ENC1_OFFSET + 0x168)
> +# define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0_SHIFT 0
> +# define VIDEO_STABLE_CNT_THRD_DP_ENC1_P0_SHIFT 4
> +# define SDP_DP13_EN_DP_ENC1_P0_SHIFT 8
> +# define BS2BS_MODE_DP_ENC1_P0_MASK 0x3000
> +# define BS2BS_MODE_DP_ENC1_P0_SHIFT 12
> +
> +#define MTK_DP_ENC1_P0_33F4 (ENC1_OFFSET + 0x1F4)
> +
> +#define MTK_DP_TRANS_P0_3400 (TRANS_OFFSET + 0x000)
> +# define PATTERN1_EN_DP_TRANS_P0_MASK 0x1000
> +# define PATTERN1_EN_DP_TRANS_P0_SHIFT 12
> +# define PATTERN2_EN_DP_TRANS_P0_MASK 0x2000
> +# define PATTERN3_EN_DP_TRANS_P0_MASK 0x4000
> +# define PATTERN4_EN_DP_TRANS_P0_MASK 0x8000
> +
> +#define MTK_DP_TRANS_P0_3404 (TRANS_OFFSET + 0x004)
> +# define DP_SCR_EN_DP_TRANS_P0_MASK 0x1
> +
> +#define MTK_DP_TRANS_P0_340C (TRANS_OFFSET + 0x00C)
> +# define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0_MASK 0x2000
> +# define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0_SHIFT 13
> +
> +#define MTK_DP_TRANS_P0_3410 (TRANS_OFFSET + 0x010)
> +# define HPD_DEB_THD_DP_TRANS_P0_MASK 0xf
> +# define HPD_DEB_THD_DP_TRANS_P0_SHIFT 0
> +# define HPD_INT_THD_DP_TRANS_P0_MASK 0xf0
> +# define HPD_INT_THD_DP_TRANS_P0_SHIFT 4
> +# define HPD_INT_THD_DP_TRANS_P0_LOWER_500US (2 << HPD_INT_THD_DP_TRANS_P0_SHIFT)
> +# define HPD_INT_THD_DP_TRANS_P0_UPPER_1100US (2 << (HPD_INT_THD_DP_TRANS_P0_SHIFT + 2))
> +# define HPD_DISC_THD_DP_TRANS_P0_MASK 0xf00
> +# define HPD_DISC_THD_DP_TRANS_P0_SHIFT 8
> +# define HPD_CONN_THD_DP_TRANS_P0_MASK 0xf000
> +# define HPD_CONN_THD_DP_TRANS_P0_SHIFT 12
> +
> +#define MTK_DP_TRANS_P0_3414 (TRANS_OFFSET + 0x014)
> +# define HPD_DB_DP_TRANS_P0_MASK 0x4
> +
> +#define MTK_DP_TRANS_P0_3418 (TRANS_OFFSET + 0x018)
> +# define IRQ_CLR_DP_TRANS_P0_MASK 0xf
> +# define IRQ_MASK_DP_TRANS_P0_MASK 0xf0
> +# define IRQ_MASK_DP_TRANS_P0_SHIFT 4
> +# define IRQ_MASK_DP_TRANS_P0_DISC_IRQ (BIT(1) << IRQ_MASK_DP_TRANS_P0_SHIFT)
> +# define IRQ_MASK_DP_TRANS_P0_CONN_IRQ (BIT(2) << IRQ_MASK_DP_TRANS_P0_SHIFT)
> +# define IRQ_MASK_DP_TRANS_P0_INT_IRQ (BIT(3) << IRQ_MASK_DP_TRANS_P0_SHIFT)
> +# define IRQ_STATUS_DP_TRANS_P0_MASK 0xf000
> +# define IRQ_STATUS_DP_TRANS_P0_SHIFT 12
> +
> +#define MTK_DP_TRANS_P0_342C (TRANS_OFFSET + 0x02C)
> +# define XTAL_FREQ_DP_TRANS_P0_DEFAULT 0x69
> +# define XTAL_FREQ_DP_TRANS_P0_MASK 0xff
> +
> +#define MTK_DP_TRANS_P0_3430 (TRANS_OFFSET + 0x030)
> +# define HPD_INT_THD_ECO_DP_TRANS_P0_MASK 0x3
> +# define HPD_INT_THD_ECO_DP_TRANS_P0_HIGH_BOUND_EXT BIT(1)
> +
> +#define MTK_DP_TRANS_P0_34A4 (TRANS_OFFSET + 0x0A4)
> +# define LANE_NUM_DP_TRANS_P0_MASK 0xc
> +# define LANE_NUM_DP_TRANS_P0_SHIFT 2
> +
> +#define MTK_DP_TRANS_P0_3540 (TRANS_OFFSET + 0x140)
> +# define FEC_EN_DP_TRANS_P0_MASK 0x1
> +# define FEC_EN_DP_TRANS_P0_SHIFT 0
> +# define FEC_CLOCK_EN_MODE_DP_TRANS_P0_MASK 0x8
> +# define FEC_CLOCK_EN_MODE_DP_TRANS_P0_SHIFT 3
> +
> +#define MTK_DP_TRANS_P0_3580 (TRANS_OFFSET + 0x180)
> +# define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_MASK 0x100
> +# define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_MASK 0x200
> +# define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_MASK 0x400
> +# define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_MASK 0x800
> +
> +#define MTK_DP_TRANS_P0_35C4 (TRANS_OFFSET + 0x1C4)
> +# define SW_IRQ_MASK_DP_TRANS_P0_MASK 0xffff
> +
> +#define MTK_DP_TRANS_P0_35C8 (TRANS_OFFSET + 0x1C8)
> +# define SW_IRQ_CLR_DP_TRANS_P0_MASK 0xffff
> +
> +# define SW_IRQ_STATUS_DP_TRANS_P0_MASK 0xffff
> +# define SW_IRQ_STATUS_DP_TRANS_P0_SHIFT 0
> +
> +#define MTK_DP_TRANS_P0_35D0 (TRANS_OFFSET + 0x1D0)
> +# define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK 0xffff
> +
> +#define MTK_DP_TRANS_P0_35F0 (TRANS_OFFSET + 0x1F0)
> +
> +#define MTK_DP_AUX_P0_360C (AUX_OFFSET + 0x00C)
> +# define AUX_TIMEOUT_THR_AUX_TX_P0_MASK 0x1fff
> +
> +#define MTK_DP_AUX_P0_3614 (AUX_OFFSET + 0x014)
> +# define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK 0x7f
> +# define AUX_RX_UI_CNT_THR_AUX_TX_P0_SHIFT 0
> +
> +#define MTK_DP_AUX_P0_3618 (AUX_OFFSET + 0x018)
> +# define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK 0x200
> +# define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK 0xf
> +
> +#define MTK_DP_AUX_P0_3620 (AUX_OFFSET + 0x020)
> +# define AUX_RD_MODE_AUX_TX_P0_MASK 0x200
> +# define AUX_RX_FIFO_READ_PULSE_TX_P0_MASK 0x100
> +# define AUX_RX_FIFO_R_PULSE_TX_P0_SHIFT 8
> +# define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_MASK 0xff
> +# define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_SHIFT 0
> +
> +#define MTK_DP_AUX_P0_3624 (AUX_OFFSET + 0x024)
> +# define AUX_RX_REPLY_COMMAND_AUX_TX_P0_MASK 0xf
> +
> +#define MTK_DP_AUX_P0_3628 (AUX_OFFSET + 0x028)
> +# define AUX_RX_PHY_STATE_AUX_TX_P0_MASK 0x3ff
> +# define AUX_RX_PHY_STATE_AUX_TX_P0_SHIFT 0
> +# define AUX_RX_PHY_STATE_AUX_TX_P0_RX_IDLE (BIT(1) << AUX_RX_PHY_STATE_AUX_TX_P0_SHIFT)
> +
> +#define MTK_DP_AUX_P0_362C (AUX_OFFSET + 0x02C)
> +# define AUX_NO_LENGTH_AUX_TX_P0_MASK 0x1
> +# define AUX_NO_LENGTH_AUX_TX_P0_SHIFT 0
> +# define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK 0x2
> +# define AUX_RESERVED_RW_0_AUX_TX_P0_MASK 0xfffc
> +
> +#define MTK_DP_AUX_P0_3630 (AUX_OFFSET + 0x030)
> +# define AUX_TX_REQUEST_READY_AUX_TX_P0_MASK 0x8
> +# define AUX_TX_REQUEST_READY_AUX_TX_P0_SHIFT 3
> +
> +#define MTK_DP_AUX_P0_3634 (AUX_OFFSET + 0x034)
> +# define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK 0xff00
> +# define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_SHIFT 8
> +
> +#define MTK_DP_AUX_P0_3640 (AUX_OFFSET + 0x040)
> +# define AUX_RX_RECV_COMPLETE_IRQ_TX_P0_MASK 0x40
> +# define AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0_SHIFT 6
> +# define AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0_SHIFT 5
> +# define AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0_SHIFT 4
> +# define AUX_RX_CMD_RECV_IRQ_AUX_TX_P0_SHIFT 3
> +# define AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0_SHIFT 2
> +# define AUX_RX_DATA_RECV_IRQ_AUX_TX_P0_SHIFT 1
> +# define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_MASK 0x1
> +# define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_SHIFT 0
> +
> +#define MTK_DP_AUX_P0_3644 (AUX_OFFSET + 0x044)
> +# define MCU_REQUEST_COMMAND_AUX_TX_P0_MASK 0xf
> +
> +#define MTK_DP_AUX_P0_3648 (AUX_OFFSET + 0x048)
> +# define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK 0xffff
> +
> +#define MTK_DP_AUX_P0_364C (AUX_OFFSET + 0x04C)
> +# define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_MASK 0xf
> +
> +#define MTK_DP_AUX_P0_3650 (AUX_OFFSET + 0x050)
> +# define MCU_REQ_DATA_NUM_AUX_TX_P0_MASK 0xf000
> +# define MCU_REQ_DATA_NUM_AUX_TX_P0_SHIFT 12
> +# define PHY_FIFO_RST_AUX_TX_P0_MASK 0x200
> +# define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_MASK 0x100
> +# define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_SHIFT 8
> +
> +#define MTK_DP_AUX_P0_3658 (AUX_OFFSET + 0x058)
> +# define AUX_TX_OV_EN_AUX_TX_P0_MASK 0x1
> +
> +#define MTK_DP_AUX_P0_3690 (AUX_OFFSET + 0x090)
> +# define RX_REPLY_COMPLETE_MODE_AUX_TX_P0_MASK 0x100
> +# define RX_REPLY_COMPLETE_MODE_AUX_TX_P0_SHIFT 8
> +
> +#define MTK_DP_AUX_P0_3704 (AUX_OFFSET + 0x104)
> +# define AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_MASK 0x2
> +# define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_MASK 0x4
> +# define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_SHIFT 2
> +
> +#define MTK_DP_AUX_P0_3708 (AUX_OFFSET + 0x108)
> +
> +#define MTK_DP_AUX_P0_37C8 (AUX_OFFSET + 0x1C8)
> +# define MTK_ATOP_EN_AUX_TX_P0_MASK 0x1
> +# define MTK_ATOP_EN_AUX_TX_P0_SHIFT 0
> +
> +#define MTK_DP_TOP_PWR_STATE (TOP_OFFSET + 0x00)
> +# define DP_PWR_STATE_MASK 0x3
> +# define DP_PWR_STATE_BANDGAP 1
> +# define DP_PWR_STATE_BANDGAP_TPLL 2
> +# define DP_PWR_STATE_BANDGAP_TPLL_LANE 3
> +
> +#define MTK_DP_TOP_SWING_EMP (TOP_OFFSET + 0x04)
> +# define DP_TX0_VOLT_SWING_MASK 0x3
> +# define DP_TX0_VOLT_SWING_SHIFT 0
> +# define DP_TX0_PRE_EMPH_MASK 0xc
> +# define DP_TX0_PRE_EMPH_SHIFT 2
> +# define DP_TX1_VOLT_SWING_MASK 0x300
> +# define DP_TX1_VOLT_SWING_SHIFT 8
> +# define DP_TX1_PRE_EMPH_MASK 0xc00
> +# define DP_TX2_VOLT_SWING_MASK 0x30000
> +# define DP_TX2_PRE_EMPH_MASK 0xc0000
> +# define DP_TX3_VOLT_SWING_MASK 0x3000000
> +# define DP_TX3_PRE_EMPH_MASK 0xc000000
> +
> +#define MTK_DP_TOP_RESET_AND_PROBE (TOP_OFFSET + 0x20)
> +# define SW_RST_B_SHIFT 0
> +# define SW_RST_B_PHYD (BIT(4) << SW_RST_B_SHIFT)
> +
> +#define MTK_DP_TOP_IRQ_STATUS (TOP_OFFSET + 0x28)
> +# define RGS_IRQ_STATUS_SHIFT 0
> +# define RGS_IRQ_STATUS_TRANSMITTER (BIT(1) << RGS_IRQ_STATUS_SHIFT)
> +
> +#define MTK_DP_TOP_IRQ_MASK (TOP_OFFSET + 0x2C)
> +# define IRQ_MASK_AUX_TOP_IRQ BIT(2)
> +
> +#define MTK_DP_TOP_MEM_PD (TOP_OFFSET + 0x38)
> +# define MEM_ISO_EN_SHIFT 0
> +# define FUSE_SEL_SHIFT 2
> +
> +#define DP_PHY_DIG_PLL_CTL_1 0x1014
> +# define TPLL_SSC_EN BIT(3)
It seems that register 0x1000 ~ 0x1fff is to control phy and 0x2000 ~
0x4fff is to control non-phy part. For mipi and hdmi, the phy part is
an independent device [1] and the phy driver is independent [2] , so I
would like this phy to be an independent device.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=v5.14
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/phy/mediatek?h=v5.14
Regards,
Chun-Kuang.
> +
> +#define DP_PHY_DIG_BIT_RATE 0x103C
> +# define BIT_RATE_RBR 0
> +# define BIT_RATE_HBR 1
> +# define BIT_RATE_HBR2 2
> +# define BIT_RATE_HBR3 3
> +
> +#define DP_PHY_DIG_SW_RST 0x1038
> +# define DP_GLB_SW_RST_PHYD BIT(0)
> +
> +#define MTK_DP_LANE0_DRIVING_PARAM_3 0x1138
> +#define MTK_DP_LANE1_DRIVING_PARAM_3 0x1238
> +#define MTK_DP_LANE2_DRIVING_PARAM_3 0x1338
> +#define MTK_DP_LANE3_DRIVING_PARAM_3 0x1438
> +# define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT 0x10
> +# define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (0x14 << 8)
> +# define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT (0x18 << 16)
> +# define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT (0x20 << 24)
> +# define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \
> + XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \
> + XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \
> + XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT)
> +
> +#define MTK_DP_LANE0_DRIVING_PARAM_4 0x113C
> +#define MTK_DP_LANE1_DRIVING_PARAM_4 0x123C
> +#define MTK_DP_LANE2_DRIVING_PARAM_4 0x133C
> +#define MTK_DP_LANE3_DRIVING_PARAM_4 0x143C
> +# define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT 0x18
> +# define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT (0x1e << 8)
> +# define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (0x24 << 16)
> +# define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT (0x20 << 24)
> +# define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \
> + XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \
> + XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \
> + XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT)
> +
> +#define MTK_DP_LANE0_DRIVING_PARAM_5 0x1140
> +#define MTK_DP_LANE1_DRIVING_PARAM_5 0x1240
> +#define MTK_DP_LANE2_DRIVING_PARAM_5 0x1340
> +#define MTK_DP_LANE3_DRIVING_PARAM_5 0x1440
> +# define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT 0x28
> +# define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT (0x30 << 8)
> +# define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \
> + XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT)
> +
> +#define MTK_DP_LANE0_DRIVING_PARAM_6 0x1144
> +#define MTK_DP_LANE1_DRIVING_PARAM_6 0x1244
> +#define MTK_DP_LANE2_DRIVING_PARAM_6 0x1344
> +#define MTK_DP_LANE3_DRIVING_PARAM_6 0x1444
> +# define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0x00
> +# define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT (0x04 << 8)
> +# define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT (0x08 << 16)
> +# define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT (0x10 << 24)
> +# define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \
> + XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \
> + XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \
> + XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT)
> +
> +#define MTK_DP_LANE0_DRIVING_PARAM_7 0x1148
> +#define MTK_DP_LANE1_DRIVING_PARAM_7 0x1248
> +#define MTK_DP_LANE2_DRIVING_PARAM_7 0x1348
> +#define MTK_DP_LANE3_DRIVING_PARAM_7 0x1448
> +# define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0x00
> +# define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT (0x06 << 8)
> +# define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT (0x0c << 16)
> +# define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT (0x00 << 24)
> +# define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \
> + XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \
> + XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \
> + XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT)
> +
> +#define MTK_DP_LANE0_DRIVING_PARAM_8 0x114C
> +#define MTK_DP_LANE1_DRIVING_PARAM_8 0x124C
> +#define MTK_DP_LANE2_DRIVING_PARAM_8 0x134C
> +#define MTK_DP_LANE3_DRIVING_PARAM_8 0x144C
> +# define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT 0x08
> +# define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT (0x00 << 8)
> +# define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
> + XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
> +
> +#endif /*_MTK_DP_REG_H_*/
> --
> 2.33.0
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver
2021-09-09 23:37 ` Chun-Kuang Hu
@ 2021-09-10 5:36 ` Markus Schneider-Pargmann
2021-09-13 23:25 ` Chun-Kuang Hu
0 siblings, 1 reply; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-10 5:36 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Philipp Zabel, Sam Ravnborg, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi Chun-Kuang,
On Fri, Sep 10, 2021 at 07:37:50AM +0800, Chun-Kuang Hu wrote:
> Hi, Markus:
>
> Markus Schneider-Pargmann <msp@baylibre.com> 於 2021年9月7日 週二 上午3:37寫道：
> >
> > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
> >
> > It supports both functional units on the mt8195, the embedded
> > DisplayPort as well as the external DisplayPort units. It offers
> > hot-plug-detection, audio up to 8 channels, and DisplayPort 1.4 with up
> > to 4 lanes.
> >
> > This driver is based on an initial version by
> > Jason-JH.Lin <jason-jh.lin@mediatek.com>.
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > ---
> >
> > Notes:
> > Changes RFC -> v1:
> > - Removed unused register definitions.
> > - Replaced workqueue with threaded irq.
> > - Removed connector code.
> > - Move to atomic_* drm functions.
> > - General cleanups of the code.
> > - Remove unused select GENERIC_PHY.
> >
> > drivers/gpu/drm/mediatek/Kconfig | 6 +
> > drivers/gpu/drm/mediatek/Makefile | 2 +
> > drivers/gpu/drm/mediatek/mtk_dp.c | 2881 +++++++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_dp_reg.h | 580 +++++
> > 4 files changed, 3469 insertions(+)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h
> >
...
> > +#define TOP_OFFSET 0x2000
> > +#define ENC0_OFFSET 0x3000
> > +#define ENC1_OFFSET 0x3200
> > +#define TRANS_OFFSET 0x3400
> > +#define AUX_OFFSET 0x3600
> > +#define SEC_OFFSET 0x4000
...
> > +
> > +#define DP_PHY_DIG_PLL_CTL_1 0x1014
> > +# define TPLL_SSC_EN BIT(3)
>
> It seems that register 0x1000 ~ 0x1fff is to control phy and 0x2000 ~
> 0x4fff is to control non-phy part. For mipi and hdmi, the phy part is
> an independent device [1] and the phy driver is independent [2] , so I
> would like this phy to be an independent device.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=v5.14
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/phy/mediatek?h=v5.14
Thanks for your feedback. I looked into both mipi and hdmi phy drivers
that you referenced. It looks like both are really separate units in
their SoCs having their own registerspaces located at a completely
different range than the units using the phy.
For this displayport driver, the phy registers are listed as part of the
(e)DP_TX unit in the datasheet. Next to the phy registers all the other
parts are listed as well in the same overall register ranges (see
above), e.g. TOP_OFFSET, ENC_OFFSET or SEC_OFFSET. Also I would like to
avoid splitting it up into a separate unit in the devicetree as the
datasheet handles it as a single unit (including the phy registers).
From a practical perspective there is also not much to these PHY
registers. The only things that would be done in the driver are:
- initializing the lane driving parameters with static values
- setup the bitrate
- enable/disable SSC
- do a reset
Exporting these four used functions over a driver boundary wouldn't help
clarity I think and the code probably can't be reused by any other
component anyways.
So I personally would prefer keeping it as part of the whole driver
because of the above mentioned reasons. What do you think?
Thanks,
Markus
>
> Regards,
> Chun-Kuang.
>
> > +
> > +#define DP_PHY_DIG_BIT_RATE 0x103C
> > +# define BIT_RATE_RBR 0
> > +# define BIT_RATE_HBR 1
> > +# define BIT_RATE_HBR2 2
> > +# define BIT_RATE_HBR3 3
> > +
> > +#define DP_PHY_DIG_SW_RST 0x1038
> > +# define DP_GLB_SW_RST_PHYD BIT(0)
> > +
> > +#define MTK_DP_LANE0_DRIVING_PARAM_3 0x1138
> > +#define MTK_DP_LANE1_DRIVING_PARAM_3 0x1238
> > +#define MTK_DP_LANE2_DRIVING_PARAM_3 0x1338
> > +#define MTK_DP_LANE3_DRIVING_PARAM_3 0x1438
> > +# define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT 0x10
> > +# define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (0x14 << 8)
> > +# define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT (0x18 << 16)
> > +# define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT (0x20 << 24)
> > +# define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \
> > + XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \
> > + XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \
> > + XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT)
> > +
> > +#define MTK_DP_LANE0_DRIVING_PARAM_4 0x113C
> > +#define MTK_DP_LANE1_DRIVING_PARAM_4 0x123C
> > +#define MTK_DP_LANE2_DRIVING_PARAM_4 0x133C
> > +#define MTK_DP_LANE3_DRIVING_PARAM_4 0x143C
> > +# define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT 0x18
> > +# define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT (0x1e << 8)
> > +# define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (0x24 << 16)
> > +# define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT (0x20 << 24)
> > +# define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \
> > + XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \
> > + XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \
> > + XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT)
> > +
> > +#define MTK_DP_LANE0_DRIVING_PARAM_5 0x1140
> > +#define MTK_DP_LANE1_DRIVING_PARAM_5 0x1240
> > +#define MTK_DP_LANE2_DRIVING_PARAM_5 0x1340
> > +#define MTK_DP_LANE3_DRIVING_PARAM_5 0x1440
> > +# define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT 0x28
> > +# define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT (0x30 << 8)
> > +# define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \
> > + XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT)
> > +
> > +#define MTK_DP_LANE0_DRIVING_PARAM_6 0x1144
> > +#define MTK_DP_LANE1_DRIVING_PARAM_6 0x1244
> > +#define MTK_DP_LANE2_DRIVING_PARAM_6 0x1344
> > +#define MTK_DP_LANE3_DRIVING_PARAM_6 0x1444
> > +# define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0x00
> > +# define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT (0x04 << 8)
> > +# define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT (0x08 << 16)
> > +# define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT (0x10 << 24)
> > +# define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \
> > + XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \
> > + XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \
> > + XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT)
> > +
> > +#define MTK_DP_LANE0_DRIVING_PARAM_7 0x1148
> > +#define MTK_DP_LANE1_DRIVING_PARAM_7 0x1248
> > +#define MTK_DP_LANE2_DRIVING_PARAM_7 0x1348
> > +#define MTK_DP_LANE3_DRIVING_PARAM_7 0x1448
> > +# define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0x00
> > +# define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT (0x06 << 8)
> > +# define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT (0x0c << 16)
> > +# define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT (0x00 << 24)
> > +# define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \
> > + XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \
> > + XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \
> > + XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT)
> > +
> > +#define MTK_DP_LANE0_DRIVING_PARAM_8 0x114C
> > +#define MTK_DP_LANE1_DRIVING_PARAM_8 0x124C
> > +#define MTK_DP_LANE2_DRIVING_PARAM_8 0x134C
> > +#define MTK_DP_LANE3_DRIVING_PARAM_8 0x144C
> > +# define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT 0x08
> > +# define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT (0x00 << 8)
> > +# define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
> > + XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
> > +
> > +#endif /*_MTK_DP_REG_H_*/
> > --
> > 2.33.0
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver
2021-09-10 5:36 ` Markus Schneider-Pargmann
@ 2021-09-13 23:25 ` Chun-Kuang Hu
2021-09-17 13:33 ` Markus Schneider-Pargmann
0 siblings, 1 reply; 22+ messages in thread
From: Chun-Kuang Hu @ 2021-09-13 23:25 UTC (permalink / raw)
To: Markus Schneider-Pargmann
Cc: Chun-Kuang Hu, Philipp Zabel, Sam Ravnborg, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Markus:
Markus Schneider-Pargmann <msp@baylibre.com> 於 2021年9月10日 週五 下午1:36寫道：
>
> Hi Chun-Kuang,
>
> On Fri, Sep 10, 2021 at 07:37:50AM +0800, Chun-Kuang Hu wrote:
> > Hi, Markus:
> >
> > Markus Schneider-Pargmann <msp@baylibre.com> 於 2021年9月7日 週二 上午3:37寫道：
> > >
> > > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
> > >
> > > It supports both functional units on the mt8195, the embedded
> > > DisplayPort as well as the external DisplayPort units. It offers
> > > hot-plug-detection, audio up to 8 channels, and DisplayPort 1.4 with up
> > > to 4 lanes.
> > >
> > > This driver is based on an initial version by
> > > Jason-JH.Lin <jason-jh.lin@mediatek.com>.
> > >
> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > > ---
> > >
> > > Notes:
> > > Changes RFC -> v1:
> > > - Removed unused register definitions.
> > > - Replaced workqueue with threaded irq.
> > > - Removed connector code.
> > > - Move to atomic_* drm functions.
> > > - General cleanups of the code.
> > > - Remove unused select GENERIC_PHY.
> > >
> > > drivers/gpu/drm/mediatek/Kconfig | 6 +
> > > drivers/gpu/drm/mediatek/Makefile | 2 +
> > > drivers/gpu/drm/mediatek/mtk_dp.c | 2881 +++++++++++++++++++++++++
> > > drivers/gpu/drm/mediatek/mtk_dp_reg.h | 580 +++++
> > > 4 files changed, 3469 insertions(+)
> > > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c
> > > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h
> > >
>
> ...
>
> > > +#define TOP_OFFSET 0x2000
> > > +#define ENC0_OFFSET 0x3000
> > > +#define ENC1_OFFSET 0x3200
> > > +#define TRANS_OFFSET 0x3400
> > > +#define AUX_OFFSET 0x3600
> > > +#define SEC_OFFSET 0x4000
>
> ...
>
> > > +
> > > +#define DP_PHY_DIG_PLL_CTL_1 0x1014
> > > +# define TPLL_SSC_EN BIT(3)
> >
> > It seems that register 0x1000 ~ 0x1fff is to control phy and 0x2000 ~
> > 0x4fff is to control non-phy part. For mipi and hdmi, the phy part is
> > an independent device [1] and the phy driver is independent [2] , so I
> > would like this phy to be an independent device.
> >
> > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=v5.14
> > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/phy/mediatek?h=v5.14
>
> Thanks for your feedback. I looked into both mipi and hdmi phy drivers
> that you referenced. It looks like both are really separate units in
> their SoCs having their own registerspaces located at a completely
> different range than the units using the phy.
>
> For this displayport driver, the phy registers are listed as part of the
> (e)DP_TX unit in the datasheet. Next to the phy registers all the other
> parts are listed as well in the same overall register ranges (see
> above), e.g. TOP_OFFSET, ENC_OFFSET or SEC_OFFSET. Also I would like to
> avoid splitting it up into a separate unit in the devicetree as the
> datasheet handles it as a single unit (including the phy registers).
OK, according to the datasheet, let it to be a single device.
>
> From a practical perspective there is also not much to these PHY
> registers. The only things that would be done in the driver are:
> - initializing the lane driving parameters with static values
> - setup the bitrate
> - enable/disable SSC
> - do a reset
> Exporting these four used functions over a driver boundary wouldn't help
> clarity I think and the code probably can't be reused by any other
> component anyways.
Use mmsys device [1] as an example. mmsys has both clock control
function and other function including routing function. The main
driver [2] is placed in soc folder, and the clock control part [3] is
separated to clk folder but the clock control part just simply control
clock gating.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=v5.15-rc1#n992
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/mediatek/mtk-mmsys.c?h=v5.15-rc1
[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8173-mm.c?h=v5.15-rc1
I think many phy driver could be used only by single device driver, so
we don't need to consider the reusability.
Regards,
Chun-Kuang.
>
> So I personally would prefer keeping it as part of the whole driver
> because of the above mentioned reasons. What do you think?
>
> Thanks,
> Markus
>
> >
> > Regards,
> > Chun-Kuang.
> >
> > > +
> > > +#define DP_PHY_DIG_BIT_RATE 0x103C
> > > +# define BIT_RATE_RBR 0
> > > +# define BIT_RATE_HBR 1
> > > +# define BIT_RATE_HBR2 2
> > > +# define BIT_RATE_HBR3 3
> > > +
> > > +#define DP_PHY_DIG_SW_RST 0x1038
> > > +# define DP_GLB_SW_RST_PHYD BIT(0)
> > > +
> > > +#define MTK_DP_LANE0_DRIVING_PARAM_3 0x1138
> > > +#define MTK_DP_LANE1_DRIVING_PARAM_3 0x1238
> > > +#define MTK_DP_LANE2_DRIVING_PARAM_3 0x1338
> > > +#define MTK_DP_LANE3_DRIVING_PARAM_3 0x1438
> > > +# define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT 0x10
> > > +# define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (0x14 << 8)
> > > +# define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT (0x18 << 16)
> > > +# define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT (0x20 << 24)
> > > +# define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \
> > > + XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \
> > > + XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \
> > > + XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT)
> > > +
> > > +#define MTK_DP_LANE0_DRIVING_PARAM_4 0x113C
> > > +#define MTK_DP_LANE1_DRIVING_PARAM_4 0x123C
> > > +#define MTK_DP_LANE2_DRIVING_PARAM_4 0x133C
> > > +#define MTK_DP_LANE3_DRIVING_PARAM_4 0x143C
> > > +# define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT 0x18
> > > +# define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT (0x1e << 8)
> > > +# define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (0x24 << 16)
> > > +# define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT (0x20 << 24)
> > > +# define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \
> > > + XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \
> > > + XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \
> > > + XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT)
> > > +
> > > +#define MTK_DP_LANE0_DRIVING_PARAM_5 0x1140
> > > +#define MTK_DP_LANE1_DRIVING_PARAM_5 0x1240
> > > +#define MTK_DP_LANE2_DRIVING_PARAM_5 0x1340
> > > +#define MTK_DP_LANE3_DRIVING_PARAM_5 0x1440
> > > +# define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT 0x28
> > > +# define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT (0x30 << 8)
> > > +# define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \
> > > + XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT)
> > > +
> > > +#define MTK_DP_LANE0_DRIVING_PARAM_6 0x1144
> > > +#define MTK_DP_LANE1_DRIVING_PARAM_6 0x1244
> > > +#define MTK_DP_LANE2_DRIVING_PARAM_6 0x1344
> > > +#define MTK_DP_LANE3_DRIVING_PARAM_6 0x1444
> > > +# define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0x00
> > > +# define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT (0x04 << 8)
> > > +# define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT (0x08 << 16)
> > > +# define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT (0x10 << 24)
> > > +# define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \
> > > + XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \
> > > + XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \
> > > + XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT)
> > > +
> > > +#define MTK_DP_LANE0_DRIVING_PARAM_7 0x1148
> > > +#define MTK_DP_LANE1_DRIVING_PARAM_7 0x1248
> > > +#define MTK_DP_LANE2_DRIVING_PARAM_7 0x1348
> > > +#define MTK_DP_LANE3_DRIVING_PARAM_7 0x1448
> > > +# define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0x00
> > > +# define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT (0x06 << 8)
> > > +# define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT (0x0c << 16)
> > > +# define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT (0x00 << 24)
> > > +# define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \
> > > + XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \
> > > + XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \
> > > + XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT)
> > > +
> > > +#define MTK_DP_LANE0_DRIVING_PARAM_8 0x114C
> > > +#define MTK_DP_LANE1_DRIVING_PARAM_8 0x124C
> > > +#define MTK_DP_LANE2_DRIVING_PARAM_8 0x134C
> > > +#define MTK_DP_LANE3_DRIVING_PARAM_8 0x144C
> > > +# define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT 0x08
> > > +# define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT (0x00 << 8)
> > > +# define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
> > > + XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
> > > +
> > > +#endif /*_MTK_DP_REG_H_*/
> > > --
> > > 2.33.0
> > >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver
2021-09-13 23:25 ` Chun-Kuang Hu
@ 2021-09-17 13:33 ` Markus Schneider-Pargmann
2021-09-17 14:36 ` Chun-Kuang Hu
0 siblings, 1 reply; 22+ messages in thread
From: Markus Schneider-Pargmann @ 2021-09-17 13:33 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Philipp Zabel, Sam Ravnborg, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi Chun-Kuang,
On Tue, Sep 14, 2021 at 07:25:48AM +0800, Chun-Kuang Hu wrote:
> Hi, Markus:
>
> Markus Schneider-Pargmann <msp@baylibre.com> 於 2021年9月10日 週五 下午1:36寫道：
> >
> > Hi Chun-Kuang,
> >
> > On Fri, Sep 10, 2021 at 07:37:50AM +0800, Chun-Kuang Hu wrote:
> > > Hi, Markus:
> > >
> > > Markus Schneider-Pargmann <msp@baylibre.com> 於 2021年9月7日 週二 上午3:37寫道：
> > > >
> > > > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
> > > >
> > > > It supports both functional units on the mt8195, the embedded
> > > > DisplayPort as well as the external DisplayPort units. It offers
> > > > hot-plug-detection, audio up to 8 channels, and DisplayPort 1.4 with up
> > > > to 4 lanes.
> > > >
> > > > This driver is based on an initial version by
> > > > Jason-JH.Lin <jason-jh.lin@mediatek.com>.
> > > >
> > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > > > ---
> > > >
> > > > Notes:
> > > > Changes RFC -> v1:
> > > > - Removed unused register definitions.
> > > > - Replaced workqueue with threaded irq.
> > > > - Removed connector code.
> > > > - Move to atomic_* drm functions.
> > > > - General cleanups of the code.
> > > > - Remove unused select GENERIC_PHY.
> > > >
> > > > drivers/gpu/drm/mediatek/Kconfig | 6 +
> > > > drivers/gpu/drm/mediatek/Makefile | 2 +
> > > > drivers/gpu/drm/mediatek/mtk_dp.c | 2881 +++++++++++++++++++++++++
> > > > drivers/gpu/drm/mediatek/mtk_dp_reg.h | 580 +++++
> > > > 4 files changed, 3469 insertions(+)
> > > > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c
> > > > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h
> > > >
> >
> > ...
> >
> > > > +#define TOP_OFFSET 0x2000
> > > > +#define ENC0_OFFSET 0x3000
> > > > +#define ENC1_OFFSET 0x3200
> > > > +#define TRANS_OFFSET 0x3400
> > > > +#define AUX_OFFSET 0x3600
> > > > +#define SEC_OFFSET 0x4000
> >
> > ...
> >
> > > > +
> > > > +#define DP_PHY_DIG_PLL_CTL_1 0x1014
> > > > +# define TPLL_SSC_EN BIT(3)
> > >
> > > It seems that register 0x1000 ~ 0x1fff is to control phy and 0x2000 ~
> > > 0x4fff is to control non-phy part. For mipi and hdmi, the phy part is
> > > an independent device [1] and the phy driver is independent [2] , so I
> > > would like this phy to be an independent device.
> > >
> > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=v5.14
> > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/phy/mediatek?h=v5.14
> >
> > Thanks for your feedback. I looked into both mipi and hdmi phy drivers
> > that you referenced. It looks like both are really separate units in
> > their SoCs having their own registerspaces located at a completely
> > different range than the units using the phy.
> >
> > For this displayport driver, the phy registers are listed as part of the
> > (e)DP_TX unit in the datasheet. Next to the phy registers all the other
> > parts are listed as well in the same overall register ranges (see
> > above), e.g. TOP_OFFSET, ENC_OFFSET or SEC_OFFSET. Also I would like to
> > avoid splitting it up into a separate unit in the devicetree as the
> > datasheet handles it as a single unit (including the phy registers).
>
> OK, according to the datasheet, let it to be a single device.
>
> >
> > From a practical perspective there is also not much to these PHY
> > registers. The only things that would be done in the driver are:
> > - initializing the lane driving parameters with static values
> > - setup the bitrate
> > - enable/disable SSC
> > - do a reset
> > Exporting these four used functions over a driver boundary wouldn't help
> > clarity I think and the code probably can't be reused by any other
> > component anyways.
>
> Use mmsys device [1] as an example. mmsys has both clock control
> function and other function including routing function. The main
> driver [2] is placed in soc folder, and the clock control part [3] is
> separated to clk folder but the clock control part just simply control
> clock gating.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=v5.15-rc1#n992
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/mediatek/mtk-mmsys.c?h=v5.15-rc1
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8173-mm.c?h=v5.15-rc1
>
> I think many phy driver could be used only by single device driver, so
> we don't need to consider the reusability.
Thank you, I have split of a display port phy similar to the patches you
cited. I will send the next version soon.
Another short question. This series has a functional dependency on the
rest of the video pipeline, so mostly the patch series vdosys0 and
vdosys1. So I suppose the theoretical order for merging (once this
series is ready for merge) is first vdosys0/1 and dependencies and then
this displayport series, is that correct?
Thanks,
Markus
>
> Regards,
> Chun-Kuang.
>
> >
> > So I personally would prefer keeping it as part of the whole driver
> > because of the above mentioned reasons. What do you think?
> >
> > Thanks,
> > Markus
> >
> > >
> > > Regards,
> > > Chun-Kuang.
> > >
> > > > +
> > > > +#define DP_PHY_DIG_BIT_RATE 0x103C
> > > > +# define BIT_RATE_RBR 0
> > > > +# define BIT_RATE_HBR 1
> > > > +# define BIT_RATE_HBR2 2
> > > > +# define BIT_RATE_HBR3 3
> > > > +
> > > > +#define DP_PHY_DIG_SW_RST 0x1038
> > > > +# define DP_GLB_SW_RST_PHYD BIT(0)
> > > > +
> > > > +#define MTK_DP_LANE0_DRIVING_PARAM_3 0x1138
> > > > +#define MTK_DP_LANE1_DRIVING_PARAM_3 0x1238
> > > > +#define MTK_DP_LANE2_DRIVING_PARAM_3 0x1338
> > > > +#define MTK_DP_LANE3_DRIVING_PARAM_3 0x1438
> > > > +# define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT 0x10
> > > > +# define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (0x14 << 8)
> > > > +# define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT (0x18 << 16)
> > > > +# define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT (0x20 << 24)
> > > > +# define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \
> > > > + XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \
> > > > + XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \
> > > > + XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT)
> > > > +
> > > > +#define MTK_DP_LANE0_DRIVING_PARAM_4 0x113C
> > > > +#define MTK_DP_LANE1_DRIVING_PARAM_4 0x123C
> > > > +#define MTK_DP_LANE2_DRIVING_PARAM_4 0x133C
> > > > +#define MTK_DP_LANE3_DRIVING_PARAM_4 0x143C
> > > > +# define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT 0x18
> > > > +# define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT (0x1e << 8)
> > > > +# define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (0x24 << 16)
> > > > +# define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT (0x20 << 24)
> > > > +# define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \
> > > > + XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \
> > > > + XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \
> > > > + XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT)
> > > > +
> > > > +#define MTK_DP_LANE0_DRIVING_PARAM_5 0x1140
> > > > +#define MTK_DP_LANE1_DRIVING_PARAM_5 0x1240
> > > > +#define MTK_DP_LANE2_DRIVING_PARAM_5 0x1340
> > > > +#define MTK_DP_LANE3_DRIVING_PARAM_5 0x1440
> > > > +# define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT 0x28
> > > > +# define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT (0x30 << 8)
> > > > +# define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \
> > > > + XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT)
> > > > +
> > > > +#define MTK_DP_LANE0_DRIVING_PARAM_6 0x1144
> > > > +#define MTK_DP_LANE1_DRIVING_PARAM_6 0x1244
> > > > +#define MTK_DP_LANE2_DRIVING_PARAM_6 0x1344
> > > > +#define MTK_DP_LANE3_DRIVING_PARAM_6 0x1444
> > > > +# define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0x00
> > > > +# define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT (0x04 << 8)
> > > > +# define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT (0x08 << 16)
> > > > +# define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT (0x10 << 24)
> > > > +# define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \
> > > > + XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \
> > > > + XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \
> > > > + XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT)
> > > > +
> > > > +#define MTK_DP_LANE0_DRIVING_PARAM_7 0x1148
> > > > +#define MTK_DP_LANE1_DRIVING_PARAM_7 0x1248
> > > > +#define MTK_DP_LANE2_DRIVING_PARAM_7 0x1348
> > > > +#define MTK_DP_LANE3_DRIVING_PARAM_7 0x1448
> > > > +# define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0x00
> > > > +# define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT (0x06 << 8)
> > > > +# define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT (0x0c << 16)
> > > > +# define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT (0x00 << 24)
> > > > +# define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \
> > > > + XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \
> > > > + XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \
> > > > + XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT)
> > > > +
> > > > +#define MTK_DP_LANE0_DRIVING_PARAM_8 0x114C
> > > > +#define MTK_DP_LANE1_DRIVING_PARAM_8 0x124C
> > > > +#define MTK_DP_LANE2_DRIVING_PARAM_8 0x134C
> > > > +#define MTK_DP_LANE3_DRIVING_PARAM_8 0x144C
> > > > +# define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT 0x08
> > > > +# define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT (0x00 << 8)
> > > > +# define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
> > > > + XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
> > > > +
> > > > +#endif /*_MTK_DP_REG_H_*/
> > > > --
> > > > 2.33.0
> > > >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver
2021-09-17 13:33 ` Markus Schneider-Pargmann
@ 2021-09-17 14:36 ` Chun-Kuang Hu
0 siblings, 0 replies; 22+ messages in thread
From: Chun-Kuang Hu @ 2021-09-17 14:36 UTC (permalink / raw)
To: Markus Schneider-Pargmann
Cc: Chun-Kuang Hu, Philipp Zabel, Sam Ravnborg, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Markus:
Markus Schneider-Pargmann <msp@baylibre.com> 於 2021年9月17日 週五 下午9:33寫道：
>
> Hi Chun-Kuang,
>
> On Tue, Sep 14, 2021 at 07:25:48AM +0800, Chun-Kuang Hu wrote:
> > Hi, Markus:
> >
> > Markus Schneider-Pargmann <msp@baylibre.com> 於 2021年9月10日 週五 下午1:36寫道：
> > >
> > > Hi Chun-Kuang,
> > >
> > > On Fri, Sep 10, 2021 at 07:37:50AM +0800, Chun-Kuang Hu wrote:
> > > > Hi, Markus:
> > > >
> > > > Markus Schneider-Pargmann <msp@baylibre.com> 於 2021年9月7日 週二 上午3:37寫道：
> > > > >
> > > > > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
> > > > >
> > > > > It supports both functional units on the mt8195, the embedded
> > > > > DisplayPort as well as the external DisplayPort units. It offers
> > > > > hot-plug-detection, audio up to 8 channels, and DisplayPort 1.4 with up
> > > > > to 4 lanes.
> > > > >
> > > > > This driver is based on an initial version by
> > > > > Jason-JH.Lin <jason-jh.lin@mediatek.com>.
> > > > >
> > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > > > > ---
> > > > >
> > > > > Notes:
> > > > > Changes RFC -> v1:
> > > > > - Removed unused register definitions.
> > > > > - Replaced workqueue with threaded irq.
> > > > > - Removed connector code.
> > > > > - Move to atomic_* drm functions.
> > > > > - General cleanups of the code.
> > > > > - Remove unused select GENERIC_PHY.
> > > > >
> > > > > drivers/gpu/drm/mediatek/Kconfig | 6 +
> > > > > drivers/gpu/drm/mediatek/Makefile | 2 +
> > > > > drivers/gpu/drm/mediatek/mtk_dp.c | 2881 +++++++++++++++++++++++++
> > > > > drivers/gpu/drm/mediatek/mtk_dp_reg.h | 580 +++++
> > > > > 4 files changed, 3469 insertions(+)
> > > > > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c
> > > > > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h
> > > > >
> > >
> > > ...
> > >
> > > > > +#define TOP_OFFSET 0x2000
> > > > > +#define ENC0_OFFSET 0x3000
> > > > > +#define ENC1_OFFSET 0x3200
> > > > > +#define TRANS_OFFSET 0x3400
> > > > > +#define AUX_OFFSET 0x3600
> > > > > +#define SEC_OFFSET 0x4000
> > >
> > > ...
> > >
> > > > > +
> > > > > +#define DP_PHY_DIG_PLL_CTL_1 0x1014
> > > > > +# define TPLL_SSC_EN BIT(3)
> > > >
> > > > It seems that register 0x1000 ~ 0x1fff is to control phy and 0x2000 ~
> > > > 0x4fff is to control non-phy part. For mipi and hdmi, the phy part is
> > > > an independent device [1] and the phy driver is independent [2] , so I
> > > > would like this phy to be an independent device.
> > > >
> > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=v5.14
> > > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/phy/mediatek?h=v5.14
> > >
> > > Thanks for your feedback. I looked into both mipi and hdmi phy drivers
> > > that you referenced. It looks like both are really separate units in
> > > their SoCs having their own registerspaces located at a completely
> > > different range than the units using the phy.
> > >
> > > For this displayport driver, the phy registers are listed as part of the
> > > (e)DP_TX unit in the datasheet. Next to the phy registers all the other
> > > parts are listed as well in the same overall register ranges (see
> > > above), e.g. TOP_OFFSET, ENC_OFFSET or SEC_OFFSET. Also I would like to
> > > avoid splitting it up into a separate unit in the devicetree as the
> > > datasheet handles it as a single unit (including the phy registers).
> >
> > OK, according to the datasheet, let it to be a single device.
> >
> > >
> > > From a practical perspective there is also not much to these PHY
> > > registers. The only things that would be done in the driver are:
> > > - initializing the lane driving parameters with static values
> > > - setup the bitrate
> > > - enable/disable SSC
> > > - do a reset
> > > Exporting these four used functions over a driver boundary wouldn't help
> > > clarity I think and the code probably can't be reused by any other
> > > component anyways.
> >
> > Use mmsys device [1] as an example. mmsys has both clock control
> > function and other function including routing function. The main
> > driver [2] is placed in soc folder, and the clock control part [3] is
> > separated to clk folder but the clock control part just simply control
> > clock gating.
> >
> > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=v5.15-rc1#n992
> > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/mediatek/mtk-mmsys.c?h=v5.15-rc1
> > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8173-mm.c?h=v5.15-rc1
> >
> > I think many phy driver could be used only by single device driver, so
> > we don't need to consider the reusability.
>
> Thank you, I have split of a display port phy similar to the patches you
> cited. I will send the next version soon.
>
> Another short question. This series has a functional dependency on the
> rest of the video pipeline, so mostly the patch series vdosys0 and
> vdosys1. So I suppose the theoretical order for merging (once this
> series is ready for merge) is first vdosys0/1 and dependencies and then
> this displayport series, is that correct?
Sometimes I would apply partial reviewed patches in a series. Even
though these partial patches would not functionally work without other
patches, they are so independent and I would like to apply them to
prevent conflicts in the future. But these patches should build pass
and not break other workable function.
Regards,
Chun-Kuang.
>
> Thanks,
> Markus
>
> >
> > Regards,
> > Chun-Kuang.
> >
> > >
> > > So I personally would prefer keeping it as part of the whole driver
> > > because of the above mentioned reasons. What do you think?
> > >
> > > Thanks,
> > > Markus
> > >
> > > >
> > > > Regards,
> > > > Chun-Kuang.
> > > >
> > > > > +
> > > > > +#define DP_PHY_DIG_BIT_RATE 0x103C
> > > > > +# define BIT_RATE_RBR 0
> > > > > +# define BIT_RATE_HBR 1
> > > > > +# define BIT_RATE_HBR2 2
> > > > > +# define BIT_RATE_HBR3 3
> > > > > +
> > > > > +#define DP_PHY_DIG_SW_RST 0x1038
> > > > > +# define DP_GLB_SW_RST_PHYD BIT(0)
> > > > > +
> > > > > +#define MTK_DP_LANE0_DRIVING_PARAM_3 0x1138
> > > > > +#define MTK_DP_LANE1_DRIVING_PARAM_3 0x1238
> > > > > +#define MTK_DP_LANE2_DRIVING_PARAM_3 0x1338
> > > > > +#define MTK_DP_LANE3_DRIVING_PARAM_3 0x1438
> > > > > +# define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT 0x10
> > > > > +# define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (0x14 << 8)
> > > > > +# define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT (0x18 << 16)
> > > > > +# define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT (0x20 << 24)
> > > > > +# define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT)
> > > > > +
> > > > > +#define MTK_DP_LANE0_DRIVING_PARAM_4 0x113C
> > > > > +#define MTK_DP_LANE1_DRIVING_PARAM_4 0x123C
> > > > > +#define MTK_DP_LANE2_DRIVING_PARAM_4 0x133C
> > > > > +#define MTK_DP_LANE3_DRIVING_PARAM_4 0x143C
> > > > > +# define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT 0x18
> > > > > +# define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT (0x1e << 8)
> > > > > +# define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (0x24 << 16)
> > > > > +# define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT (0x20 << 24)
> > > > > +# define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT)
> > > > > +
> > > > > +#define MTK_DP_LANE0_DRIVING_PARAM_5 0x1140
> > > > > +#define MTK_DP_LANE1_DRIVING_PARAM_5 0x1240
> > > > > +#define MTK_DP_LANE2_DRIVING_PARAM_5 0x1340
> > > > > +#define MTK_DP_LANE3_DRIVING_PARAM_5 0x1440
> > > > > +# define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT 0x28
> > > > > +# define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT (0x30 << 8)
> > > > > +# define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT)
> > > > > +
> > > > > +#define MTK_DP_LANE0_DRIVING_PARAM_6 0x1144
> > > > > +#define MTK_DP_LANE1_DRIVING_PARAM_6 0x1244
> > > > > +#define MTK_DP_LANE2_DRIVING_PARAM_6 0x1344
> > > > > +#define MTK_DP_LANE3_DRIVING_PARAM_6 0x1444
> > > > > +# define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0x00
> > > > > +# define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT (0x04 << 8)
> > > > > +# define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT (0x08 << 16)
> > > > > +# define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT (0x10 << 24)
> > > > > +# define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT)
> > > > > +
> > > > > +#define MTK_DP_LANE0_DRIVING_PARAM_7 0x1148
> > > > > +#define MTK_DP_LANE1_DRIVING_PARAM_7 0x1248
> > > > > +#define MTK_DP_LANE2_DRIVING_PARAM_7 0x1348
> > > > > +#define MTK_DP_LANE3_DRIVING_PARAM_7 0x1448
> > > > > +# define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0x00
> > > > > +# define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT (0x06 << 8)
> > > > > +# define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT (0x0c << 16)
> > > > > +# define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT (0x00 << 24)
> > > > > +# define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT)
> > > > > +
> > > > > +#define MTK_DP_LANE0_DRIVING_PARAM_8 0x114C
> > > > > +#define MTK_DP_LANE1_DRIVING_PARAM_8 0x124C
> > > > > +#define MTK_DP_LANE2_DRIVING_PARAM_8 0x134C
> > > > > +#define MTK_DP_LANE3_DRIVING_PARAM_8 0x144C
> > > > > +# define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT 0x08
> > > > > +# define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT (0x00 << 8)
> > > > > +# define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
> > > > > + XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
> > > > > +
> > > > > +#endif /*_MTK_DP_REG_H_*/
> > > > > --
> > > > > 2.33.0
> > > > >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2021-09-17 14:37 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-06 19:35 [PATCH v1 0/6] drm/mediatek: Add mt8195 DisplayPort driver Markus Schneider-Pargmann
2021-09-06 19:35 ` [PATCH v1 1/6] dt-bindings: mediatek,dpi: Add mt8195 dpintf Markus Schneider-Pargmann
2021-09-06 20:14 ` Sam Ravnborg
2021-09-09 12:49 ` Markus Schneider-Pargmann
2021-09-06 19:35 ` [PATCH v1 2/6] dt-bindings: mediatek,dp: Add Display Port binding Markus Schneider-Pargmann
2021-09-06 19:35 ` [PATCH v1 3/6] drm/edid: Add cea_sad helpers for freq/length Markus Schneider-Pargmann
2021-09-06 20:19 ` Sam Ravnborg
2021-09-07 7:38 ` Markus Schneider-Pargmann
2021-09-06 19:35 ` [PATCH v1 4/6] video/hdmi: Add audio_infoframe packing for DP Markus Schneider-Pargmann
2021-09-06 20:30 ` Sam Ravnborg
2021-09-07 8:59 ` Markus Schneider-Pargmann
2021-09-06 19:35 ` [PATCH v1 5/6] drm/mediatek: dpi: Add dpintf support Markus Schneider-Pargmann
2021-09-06 19:35 ` [PATCH v1 6/6] drm/mediatek: Add mt8195 DisplayPort driver Markus Schneider-Pargmann
2021-09-06 20:39 ` Sam Ravnborg
2021-09-09 12:45 ` Markus Schneider-Pargmann
2021-09-07 8:47 ` Philipp Zabel
2021-09-09 9:16 ` Markus Schneider-Pargmann
2021-09-09 23:37 ` Chun-Kuang Hu
2021-09-10 5:36 ` Markus Schneider-Pargmann
2021-09-13 23:25 ` Chun-Kuang Hu
2021-09-17 13:33 ` Markus Schneider-Pargmann
2021-09-17 14:36 ` Chun-Kuang Hu
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