From: jason-jh.lin <jason-jh.lin@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>
Cc: Enric Balletbo i Serra <enric.balletbo@collabora.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
<hsinyi@chromium.org>, <fshao@chromium.org>,
<jason-jh.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
<nancy.lin@mediatek.com>, <singo.chang@mediatek.com>,
<devicetree@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>
Subject: [PATCH v10 09/17] arm64: dts: mt8195: add display node for vdosys0
Date: Wed, 8 Sep 2021 14:03:04 +0800 [thread overview]
Message-ID: <20210908060312.24007-10-jason-jh.lin@mediatek.com> (raw)
In-Reply-To: <20210908060312.24007-1-jason-jh.lin@mediatek.com>
Add display node for vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is based on [1][2][3]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2]arm64: dts: mt8195: add IOMMU and smi nodes
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3]arm64: dts: mt8195: add gce node
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210831070903.8672-4-jason-jh.lin@mediatek.com/
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 111 +++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 47c44cb77da0..a90e39dbd860 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1153,9 +1153,120 @@
#clock-cells = <1>;
};
+ ovl0: disp_ovl@1c000000 {
+ compatible = "mediatek,mt8195-disp-ovl",
+ "mediatek,mt8183-disp-ovl";
+ reg = <0 0x1c000000 0 0x1000>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>;
+ };
+
+ rdma0: disp_rdma@1c002000 {
+ compatible = "mediatek,mt8195-disp-rdma";
+ reg = <0 0x1c002000 0 0x1000>;
+ interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>;
+ };
+
+ color0: disp_color@1c003000 {
+ compatible = "mediatek,mt8195-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x1c003000 0 0x1000>;
+ interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>;
+ };
+
+ ccorr0: disp_ccorr@1c004000 {
+ compatible = "mediatek,mt8195-disp-ccorr",
+ "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1c004000 0 0x1000>;
+ interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>;
+ };
+
+ aal0: disp_aal@1c005000 {
+ compatible = "mediatek,mt8195-disp-aal",
+ "mediatek,mt8173-disp-aal";
+ reg = <0 0x1c005000 0 0x1000>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>;
+ };
+
+ gamma0: disp_gamma@1c006000 {
+ compatible = "mediatek,mt8195-disp-gamma",
+ "mediatek,mt8173-disp-gamma";
+ reg = <0 0x1c006000 0 0x1000>;
+ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>;
+ };
+
+ dither0: disp_dither@1c007000 {
+ compatible = "mediatek,mt8195-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1c007000 0 0x1000>;
+ interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>;
+ };
+
+ dsc0: disp_dsc_wrap@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+
+ merge0: disp_vpp_merge0@1c014000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c014000 0 0x1000>;
+ interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>;
+ };
+
+ mutex: disp_mutex0@1c016000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c016000 0 0x1000>;
+ reg-names = "vdo0_mutex";
+ interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+ clock-names = "vdo0_mutex";
+ mediatek,gce-events =
+ <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+ };
+
vdosys0: syscon@1c01a000 {
compatible = "mediatek,mt8195-vdosys0", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
+ mboxes = <&gce1 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
};
--
2.18.0
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next prev parent reply other threads:[~2021-09-08 6:16 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-08 6:02 [PATCH v10 00/17] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2021-09-08 6:02 ` [PATCH v10 01/17] dt-bindings: arm: mediatek: mmsys: add power and gce properties jason-jh.lin
2021-09-08 8:32 ` Enric Balletbo i Serra
2021-09-08 10:13 ` Jason-JH Lin
2021-09-08 6:02 ` [PATCH v10 02/17] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding jason-jh.lin
2021-09-08 6:02 ` [PATCH v10 03/17] dt-bindings: display: mediatek: disp: split each block to individual yaml jason-jh.lin
2021-09-08 6:02 ` [PATCH v10 04/17] dt-bindings: arm: mediatek: mutex: move mutex binding from display folder jason-jh.lin
2021-09-08 6:03 ` [PATCH v10 05/17] dt-bindings: arm: mediatek: mutex: add mt8195 SoC binding jason-jh.lin
2021-09-08 6:03 ` [PATCH v10 06/17] dt-bindings: display: mediatek: dsc: add yaml for " jason-jh.lin
2021-09-08 6:03 ` [PATCH v10 07/17] dt-bindings: display: mediatek: merge: add additional prop for mt8195 jason-jh.lin
2021-09-08 6:39 ` Philipp Zabel
2021-09-08 7:24 ` Jason-JH Lin
2021-09-08 6:03 ` [PATCH v10 08/17] dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0 jason-jh.lin
2021-09-08 6:03 ` jason-jh.lin [this message]
2021-09-08 6:03 ` [PATCH v10 10/17] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
2021-09-08 6:03 ` [PATCH v10 11/17] soc: mediatek: add mtk-mutex " jason-jh.lin
2021-09-08 6:03 ` [PATCH v10 12/17] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c jason-jh.lin
2021-09-08 6:03 ` [PATCH v10 13/17] drm/mediatek: rename the define of register offset jason-jh.lin
2021-09-08 6:03 ` [PATCH v10 14/17] drm/mediatek: adjust to the alphabetic order for mediatek-drm jason-jh.lin
2021-09-08 6:03 ` [PATCH v10 15/17] drm/mediatek: add DSC support " jason-jh.lin
2021-09-08 6:03 ` [PATCH v10 16/17] drm/mediatek: add MERGE " jason-jh.lin
2021-09-08 6:03 ` [PATCH v10 17/17] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin
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