From: Chun-Jie Chen <chun-jie.chen@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <srv_heupstream@mediatek.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>
Subject: [v3 08/24] clk: mediatek: Add MT8195 peripheral clock support
Date: Tue, 14 Sep 2021 10:16:17 +0800 [thread overview]
Message-ID: <20210914021633.26377-9-chun-jie.chen@mediatek.com> (raw)
In-Reply-To: <20210914021633.26377-1-chun-jie.chen@mediatek.com>
Add MT8195 peripheral clock controller which provides clock
gate control for ethernet/flashif/pcie/ssusb.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8195-peri_ao.c | 62 +++++++++++++++++++++++
2 files changed, 64 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8195-peri_ao.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a142342a0cea..0dbf4ddf4a09 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -80,6 +80,7 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o
obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o
obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
-obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o
+obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o \
+ clk-mt8195-peri_ao.o
obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-peri_ao.c b/drivers/clk/mediatek/clk-mt8195-peri_ao.c
new file mode 100644
index 000000000000..907a92b22de8
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-peri_ao.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+static const struct mtk_gate_regs peri_ao_cg_regs = {
+ .set_ofs = 0x10,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x18,
+};
+
+#define GATE_PERI_AO(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &peri_ao_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate peri_ao_clks[] = {
+ GATE_PERI_AO(CLK_PERI_AO_ETHERNET, "peri_ao_ethernet", "top_axi", 0),
+ GATE_PERI_AO(CLK_PERI_AO_ETHERNET_BUS, "peri_ao_ethernet_bus", "top_axi", 1),
+ GATE_PERI_AO(CLK_PERI_AO_FLASHIF_BUS, "peri_ao_flashif_bus", "top_axi", 3),
+ GATE_PERI_AO(CLK_PERI_AO_FLASHIF_FLASH, "peri_ao_flashif_flash", "top_spinor", 5),
+ GATE_PERI_AO(CLK_PERI_AO_SSUSB_1P_BUS, "peri_ao_ssusb_1p_bus", "top_usb_top_1p", 7),
+ GATE_PERI_AO(CLK_PERI_AO_SSUSB_1P_XHCI, "peri_ao_ssusb_1p_xhci", "top_ssusb_xhci_1p", 8),
+ GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_BUS, "peri_ao_ssusb_2p_bus", "top_usb_top_2p", 9),
+ GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_XHCI, "peri_ao_ssusb_2p_xhci", "top_ssusb_xhci_2p", 10),
+ GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_BUS, "peri_ao_ssusb_3p_bus", "top_usb_top_3p", 11),
+ GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_XHCI, "peri_ao_ssusb_3p_xhci", "top_ssusb_xhci_3p", 12),
+ GATE_PERI_AO(CLK_PERI_AO_SPINFI, "peri_ao_spinfi", "top_spinfi_bclk", 15),
+ GATE_PERI_AO(CLK_PERI_AO_ETHERNET_MAC, "peri_ao_ethernet_mac", "top_snps_eth_250m", 16),
+ GATE_PERI_AO(CLK_PERI_AO_NFI_H, "peri_ao_nfi_h", "top_axi", 19),
+ GATE_PERI_AO(CLK_PERI_AO_FNFI1X, "peri_ao_fnfi1x", "top_nfi1x", 20),
+ GATE_PERI_AO(CLK_PERI_AO_PCIE_P0_MEM, "peri_ao_pcie_p0_mem", "mem_466m", 24),
+ GATE_PERI_AO(CLK_PERI_AO_PCIE_P1_MEM, "peri_ao_pcie_p1_mem", "mem_466m", 25),
+};
+
+static const struct mtk_clk_desc peri_ao_desc = {
+ .clks = peri_ao_clks,
+ .num_clks = ARRAY_SIZE(peri_ao_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_peri_ao[] = {
+ {
+ .compatible = "mediatek,mt8195-pericfg_ao",
+ .data = &peri_ao_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver clk_mt8195_peri_ao_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8195-peri_ao",
+ .of_match_table = of_match_clk_mt8195_peri_ao,
+ },
+};
+builtin_platform_driver(clk_mt8195_peri_ao_drv);
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
next prev parent reply other threads:[~2021-09-14 2:28 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-14 2:16 [v3 00/24] Mediatek MT8195 clock support Chun-Jie Chen
2021-09-14 2:16 ` [v3 01/24] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
2021-09-14 22:17 ` Stephen Boyd
2021-09-14 2:16 ` [v3 02/24] clk: mediatek: Add dt-bindings of MT8195 clocks Chun-Jie Chen
2021-09-14 22:17 ` Stephen Boyd
2021-09-14 2:16 ` [v3 03/24] clk: mediatek: Fix corner case of tuner_en_reg Chun-Jie Chen
2021-09-14 22:18 ` Stephen Boyd
2021-09-14 2:16 ` [v3 04/24] clk: mediatek: Add API for clock resource recycle Chun-Jie Chen
2021-09-14 22:18 ` Stephen Boyd
2021-09-14 2:16 ` [v3 05/24] clk: mediatek: Fix resource leak in mtk_clk_simple_probe Chun-Jie Chen
2021-09-14 22:18 ` Stephen Boyd
2021-09-14 2:16 ` [v3 06/24] clk: mediatek: Add MT8195 apmixedsys clock support Chun-Jie Chen
2021-09-14 22:18 ` Stephen Boyd
2021-09-14 2:16 ` [v3 07/24] clk: mediatek: Add MT8195 topckgen " Chun-Jie Chen
2021-09-14 3:54 ` Chen-Yu Tsai
2021-09-14 22:18 ` Stephen Boyd
2021-09-14 2:16 ` Chun-Jie Chen [this message]
2021-09-14 22:18 ` [v3 08/24] clk: mediatek: Add MT8195 peripheral " Stephen Boyd
2021-09-14 2:16 ` [v3 09/24] clk: mediatek: Add MT8195 infrastructure " Chun-Jie Chen
2021-09-14 3:57 ` Chen-Yu Tsai
2021-09-14 22:18 ` Stephen Boyd
2021-09-14 2:16 ` [v3 10/24] clk: mediatek: Add MT8195 camsys " Chun-Jie Chen
2021-09-14 22:18 ` Stephen Boyd
2021-09-14 2:16 ` [v3 11/24] clk: mediatek: Add MT8195 ccusys " Chun-Jie Chen
2021-09-14 22:18 ` Stephen Boyd
2021-09-14 2:16 ` [v3 12/24] clk: mediatek: Add MT8195 imgsys " Chun-Jie Chen
2021-09-14 22:19 ` Stephen Boyd
2021-09-14 2:16 ` [v3 13/24] clk: mediatek: Add MT8195 ipesys " Chun-Jie Chen
2021-09-14 3:58 ` Chen-Yu Tsai
2021-09-14 22:19 ` Stephen Boyd
2021-09-14 2:16 ` [v3 14/24] clk: mediatek: Add MT8195 mfgcfg " Chun-Jie Chen
2021-09-14 3:59 ` Chen-Yu Tsai
2021-09-14 22:19 ` Stephen Boyd
2021-09-14 2:16 ` [v3 15/24] clk: mediatek: Add MT8195 scp adsp " Chun-Jie Chen
2021-09-14 22:19 ` Stephen Boyd
2021-09-14 2:16 ` [v3 16/24] clk: mediatek: Add MT8195 vdecsys " Chun-Jie Chen
2021-09-14 22:19 ` Stephen Boyd
2021-09-14 2:16 ` [v3 17/24] clk: mediatek: Add MT8195 vdosys0 " Chun-Jie Chen
2021-09-14 4:00 ` Chen-Yu Tsai
2021-09-14 22:19 ` Stephen Boyd
2021-09-14 2:16 ` [v3 18/24] clk: mediatek: Add MT8195 vdosys1 " Chun-Jie Chen
2021-09-14 4:00 ` Chen-Yu Tsai
2021-09-14 22:19 ` Stephen Boyd
2021-09-14 2:16 ` [v3 19/24] clk: mediatek: Add MT8195 vencsys " Chun-Jie Chen
2021-09-14 22:19 ` Stephen Boyd
2021-09-14 2:16 ` [v3 20/24] clk: mediatek: Add MT8195 vppsys0 " Chun-Jie Chen
2021-09-14 22:19 ` Stephen Boyd
2021-09-14 2:16 ` [v3 21/24] clk: mediatek: Add MT8195 vppsys1 " Chun-Jie Chen
2021-09-14 22:19 ` Stephen Boyd
2021-09-14 2:16 ` [v3 22/24] clk: mediatek: Add MT8195 wpesys " Chun-Jie Chen
2021-09-14 22:20 ` Stephen Boyd
2021-09-14 2:16 ` [v3 23/24] clk: mediatek: Add MT8195 imp i2c wrapper " Chun-Jie Chen
2021-09-14 22:20 ` Stephen Boyd
2021-09-14 2:16 ` [v3 24/24] clk: mediatek: Add MT8195 apusys " Chun-Jie Chen
2021-09-14 22:20 ` Stephen Boyd
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210914021633.26377-9-chun-jie.chen@mediatek.com \
--to=chun-jie.chen@mediatek.com \
--cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=drinkcat@chromium.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=srv_heupstream@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).