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From: Nancy.Lin <nancy.lin@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	"jason-jh . lin" <jason-jh.lin@mediatek.com>,
	"Nancy . Lin" <nancy.lin@mediatek.com>,
	Yongqiang Niu <yongqiang.niu@mediatek.com>,
	<dri-devel@lists.freedesktop.org>,
	<linux-mediatek@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<singo.chang@mediatek.com>, <srv_heupstream@mediatek.com>
Subject: [PATCH v6 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
Date: Mon, 4 Oct 2021 14:21:33 +0800	[thread overview]
Message-ID: <20211004062140.29803-10-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20211004062140.29803-1-nancy.lin@mediatek.com>

MT8195 vdosys1 has more than 32 reset bits and a different reset base
than other chips. Modify mmsys for support 64 bit and different reset
base.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
 drivers/soc/mediatek/mt8195-mmsys.h |  1 +
 drivers/soc/mediatek/mtk-mmsys.c    | 21 ++++++++++++++++-----
 drivers/soc/mediatek/mtk-mmsys.h    |  2 ++
 3 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 648baaec112b..f67801c42fd9 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -123,6 +123,7 @@
 #define MT8195_VDO1_MIXER_SOUT_SEL_IN				0xf68
 #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER		(0 << 0)
 
+#define MT8195_VDO1_SW0_RST_B           0x1d0
 #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD	0xe30
 #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD	0xe40
 #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD	0xe50
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 7802c2239874..8a6556892e60 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -19,6 +19,8 @@
 #include "mt8192-mmsys.h"
 #include "mt8195-mmsys.h"
 
+#define MMSYS_SW_RESET_PER_REG 32
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.clk_driver = "clk-mt2701-mm",
 	.routes = mmsys_default_routing_table,
@@ -49,12 +51,16 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.clk_driver = "clk-mt8173-mm",
 	.routes = mmsys_default_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
+	.sw_reset_start = MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.clk_driver = "clk-mt8183-mm",
 	.routes = mmsys_mt8183_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+	.sw_reset_start = MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -75,6 +81,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
 	.config = mmsys_mt8195_config_table,
 	.num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
+	.sw_reset_start = MT8195_VDO1_SW0_RST_B,
+	.num_resets = 64,
 };
 
 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
@@ -133,19 +141,23 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
 {
 	struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
 	unsigned long flags;
+	u32 offset;
 	u32 reg;
 	int i;
 
+	offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+	id = id % MMSYS_SW_RESET_PER_REG;
+
 	spin_lock_irqsave(&mmsys->lock, flags);
 
-	reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
+	reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
 
 	if (assert)
 		reg &= ~BIT(id);
 	else
 		reg |= BIT(id);
 
-	writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
+	writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
 
 	spin_unlock_irqrestore(&mmsys->lock, flags);
 
@@ -241,10 +253,11 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	mmsys->data = of_device_get_match_data(&pdev->dev);
 	spin_lock_init(&mmsys->lock);
 
 	mmsys->rcdev.owner = THIS_MODULE;
-	mmsys->rcdev.nr_resets = 32;
+	mmsys->rcdev.nr_resets = mmsys->data->num_resets;
 	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
 	mmsys->rcdev.of_node = pdev->dev.of_node;
 	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
@@ -253,8 +266,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	mmsys->data = of_device_get_match_data(&pdev->dev);
-
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
 	if (ret)
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 2694021435d2..4842102cd451 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -102,6 +102,8 @@ struct mtk_mmsys_driver_data {
 	const unsigned int num_routes;
 	const struct mtk_mmsys_config *config;
 	const unsigned int num_configs;
+	u32 sw_reset_start;
+	u32 num_resets;
 };
 
 /*
-- 
2.18.0


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  parent reply	other threads:[~2021-10-04  6:33 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-04  6:21 [PATCH v6 00/16] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2021-10-04  6:21 ` [PATCH v6 01/16] dt-bindings: mediatek: add vdosys1 RDMA definition " Nancy.Lin
2021-10-04  6:21 ` [PATCH v6 02/16] dt-bindings: mediatek: add vdosys1 MERGE property " Nancy.Lin
2021-10-15  8:08   ` AngeloGioacchino Del Regno
2021-10-15 16:21   ` Chun-Kuang Hu
2021-10-04  6:21 ` [PATCH v6 03/16] dt-bindings: mediatek: add ethdr definition " Nancy.Lin
2021-10-15 23:37   ` Chun-Kuang Hu
2021-10-22  7:18     ` Nancy.Lin
2021-10-04  6:21 ` [PATCH v6 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2021-10-15 23:41   ` Chun-Kuang Hu
2021-10-04  6:21 ` [PATCH v6 05/16] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2021-10-04  6:21 ` [PATCH v6 06/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2021-10-14 14:52   ` AngeloGioacchino Del Regno
2021-10-04  6:21 ` [PATCH v6 07/16] soc: mediatek: add mtk-mmsys config API " Nancy.Lin
2021-10-04  6:21 ` [PATCH v6 08/16] soc: mediatek: add cmdq support of " Nancy.Lin
2021-10-04  6:21 ` Nancy.Lin [this message]
2021-10-14 14:56   ` [PATCH v6 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1 AngeloGioacchino Del Regno
2021-10-22  7:05     ` Nancy.Lin
2021-10-04  6:21 ` [PATCH v6 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2021-10-14 15:01   ` AngeloGioacchino Del Regno
2021-10-22  7:33     ` Nancy.Lin
2021-10-04  6:21 ` [PATCH v6 11/16] drm/mediatek: add display MDP RDMA support for MT8195 Nancy.Lin
2021-10-19 16:38   ` Chun-Kuang Hu
2021-10-25  1:48     ` Nancy.Lin
2021-10-04  6:21 ` [PATCH v6 12/16] drm/mediatek: add display merge api " Nancy.Lin
2021-10-21 15:02   ` Chun-Kuang Hu
2021-10-25  2:10     ` Nancy.Lin
2021-10-04  6:21 ` [PATCH v6 13/16] drm/mediatek: add ETHDR " Nancy.Lin
2021-10-21 15:44   ` Chun-Kuang Hu
2021-10-25  2:24     ` Nancy.Lin
2021-10-04  6:21 ` [PATCH v6 14/16] drm/mediatek: add ovl_adaptor " Nancy.Lin
2021-10-15  7:49   ` AngeloGioacchino Del Regno
2021-10-25  2:42     ` Nancy.Lin
2021-10-25 23:11   ` Chun-Kuang Hu
2021-10-26  7:53     ` Nancy.Lin
2021-10-04  6:21 ` [PATCH v6 15/16] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Nancy.Lin
2021-10-04  6:21 ` [PATCH v6 16/16] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 Nancy.Lin

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