From: Conor Dooley <conor@kernel.org>
To: Daniel Golle <daniel@makrotopia.org>
Cc: "David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Felix Fietkau <nbd@nbd.name>, John Crispin <john@phrozen.org>,
Sean Wang <sean.wang@mediatek.com>,
Mark Lee <Mark-MC.Lee@mediatek.com>,
Lorenzo Bianconi <lorenzo@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
Alexander Couzens <lynxis@fe80.eu>,
Qingfang Deng <dqfext@gmail.com>,
SkyLake Huang <SkyLake.Huang@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
linux-phy@lists.infradead.org
Subject: Re: [RFC PATCH net-next v3 7/8] dt-bindings: net: mediatek,net: fix and complete mt7988-eth binding
Date: Tue, 12 Dec 2023 16:34:32 +0000 [thread overview]
Message-ID: <20231212-unlinked-audio-94132ec03663@spud> (raw)
In-Reply-To: <ac6a7277fc534f610386bc51b2ff87beade03be8.1702352117.git.daniel@makrotopia.org>
[-- Attachment #1: Type: text/plain, Size: 8235 bytes --]
On Tue, Dec 12, 2023 at 03:51:01AM +0000, Daniel Golle wrote:
> Complete support for MT7988 which comes with 3 MACs, SRAM for DMA
> descriptors and uses a dedicated PCS for the SerDes units.
The commit message here seems a bit incomplete, mostly a lack of an
explanation for why the model was initially incorrect.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
>
> Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding")
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> ---
> .../devicetree/bindings/net/mediatek,net.yaml | 148 +++++++++++++++++-
> 1 file changed, 146 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
> index 030d106bc7d3f..ca0667c51c1c2 100644
> --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
> +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
> @@ -28,7 +28,10 @@ properties:
> - ralink,rt5350-eth
>
> reg:
> - maxItems: 1
> + minItems: 1
> + items:
> + - description: Base of registers used to program the ethernet controller
> + - description: SRAM region used for DMA descriptors
>
> clocks: true
> clock-names: true
> @@ -115,6 +118,9 @@ allOf:
> - mediatek,mt7623-eth
> then:
> properties:
> + reg:
> + maxItems: 1
> +
> interrupts:
> maxItems: 3
>
> @@ -149,6 +155,9 @@ allOf:
> - mediatek,mt7621-eth
> then:
> properties:
> + reg:
> + maxItems: 1
> +
> interrupts:
> maxItems: 1
>
> @@ -174,6 +183,9 @@ allOf:
> const: mediatek,mt7622-eth
> then:
> properties:
> + reg:
> + maxItems: 1
> +
> interrupts:
> maxItems: 3
>
> @@ -215,6 +227,9 @@ allOf:
> const: mediatek,mt7629-eth
> then:
> properties:
> + reg:
> + maxItems: 1
> +
> interrupts:
> maxItems: 3
>
> @@ -257,6 +272,9 @@ allOf:
> const: mediatek,mt7981-eth
> then:
> properties:
> + reg:
> + maxItems: 1
> +
> interrupts:
> minItems: 4
>
> @@ -295,6 +313,9 @@ allOf:
> const: mediatek,mt7986-eth
> then:
> properties:
> + reg:
> + maxItems: 1
> +
> interrupts:
> minItems: 4
>
> @@ -333,8 +354,12 @@ allOf:
> const: mediatek,mt7988-eth
> then:
> properties:
> + reg:
> + minItems: 2
> +
> interrupts:
> minItems: 4
> + maxItems: 4
>
> clocks:
> minItems: 24
> @@ -368,7 +393,7 @@ allOf:
> - const: top_netsys_warp_sel
>
> patternProperties:
> - "^mac@[0-1]$":
> + "^mac@[0-2]$":
> type: object
> unevaluatedProperties: false
> allOf:
> @@ -382,6 +407,9 @@ patternProperties:
> reg:
> maxItems: 1
>
> + phys:
> + maxItems: 1
> +
> required:
> - reg
> - compatible
> @@ -559,3 +587,118 @@ examples:
> };
> };
> };
> +
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/mediatek,mt7988-clk.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + ethernet@15100000 {
> + compatible = "mediatek,mt7988-eth";
> + reg = <0 0x15100000 0 0x80000>, <0 0x15400000 0 0x380000>;
> + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <ðsys CLK_ETHDMA_XGP1_EN>,
> + <ðsys CLK_ETHDMA_XGP2_EN>,
> + <ðsys CLK_ETHDMA_XGP3_EN>,
> + <ðsys CLK_ETHDMA_FE_EN>,
> + <ðsys CLK_ETHDMA_GP2_EN>,
> + <ðsys CLK_ETHDMA_GP1_EN>,
> + <ðsys CLK_ETHDMA_GP3_EN>,
> + <ðsys CLK_ETHDMA_ESW_EN>,
> + <ðsys CLK_ETHDMA_CRYPT0_EN>,
> + <ðwarp CLK_ETHWARP_WOCPU2_EN>,
> + <ðwarp CLK_ETHWARP_WOCPU1_EN>,
> + <ðwarp CLK_ETHWARP_WOCPU0_EN>,
> + <&topckgen CLK_TOP_ETH_GMII_SEL>,
> + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
> + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
> + <&topckgen CLK_TOP_ETH_SYS_SEL>,
> + <&topckgen CLK_TOP_ETH_XGMII_SEL>,
> + <&topckgen CLK_TOP_ETH_MII_SEL>,
> + <&topckgen CLK_TOP_NETSYS_SEL>,
> + <&topckgen CLK_TOP_NETSYS_500M_SEL>,
> + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
> + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
> + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
> + <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
> +
> + clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
> + "gp3", "esw", "crypto",
> + "ethwarp_wocpu2", "ethwarp_wocpu1",
> + "ethwarp_wocpu0", "top_eth_gmii_sel",
> + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
> + "top_eth_sys_sel", "top_eth_xgmii_sel",
> + "top_eth_mii_sel", "top_netsys_sel",
> + "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
> + "top_netsys_sync_250m_sel",
> + "top_netsys_ppefb_250m_sel",
> + "top_netsys_warp_sel";
> + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
> + <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
> + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
> + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
> + <&topckgen CLK_TOP_SGM_0_SEL>,
> + <&topckgen CLK_TOP_SGM_1_SEL>;
> + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
> + <&topckgen CLK_TOP_NET1PLL_D4>,
> + <&topckgen CLK_TOP_NET1PLL_D8_D4>,
> + <&topckgen CLK_TOP_NET1PLL_D8_D4>,
> + <&apmixedsys CLK_APMIXED_SGMPLL>,
> + <&apmixedsys CLK_APMIXED_SGMPLL>;
> + mediatek,ethsys = <ðsys>;
> + mediatek,infracfg = <&topmisc>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mac@0 {
> + compatible = "mediatek,eth-mac";
> + reg = <0>;
> + phy-mode = "internal"; /* CPU port of built-in 1GE switch */
> +
> + fixed-link {
> + speed = <10000>;
> + full-duplex;
> + pause;
> + };
> + };
> +
> + mac@1 {
> + compatible = "mediatek,eth-mac";
> + reg = <1>;
> + phy-handle = <&int_2p5g_phy>;
> + };
> +
> + mac@2 {
> + compatible = "mediatek,eth-mac";
> + reg = <2>;
> + pcs-handle = <&usxgmiisys0>, <&sgmii0>;
> + phys = <&pextp0>;
> + };
> +
> + mdio_bus: mdio-bus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* external PHY */
> + phy0: ethernet-phy@0 {
> + reg = <0>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + /* internal 2.5G PHY */
> + int_2p5g_phy: ethernet-phy@15 {
> + reg = <15>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + phy-mode = "internal";
> + };
> + };
> + };
> + };
> --
> 2.43.0
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
next prev parent reply other threads:[~2023-12-12 16:34 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-12 3:45 [RFC PATCH net-next v3 0/8] Add support for 10G Ethernet SerDes on MT7988 Daniel Golle
2023-12-12 3:46 ` [RFC PATCH net-next v3 1/8] dt-bindings: phy: mediatek,xfi-pextp: add new bindings Daniel Golle
2023-12-12 5:43 ` Rob Herring
2023-12-12 16:21 ` Conor Dooley
2023-12-12 16:42 ` Daniel Golle
2023-12-13 9:46 ` Conor Dooley
2023-12-13 13:20 ` Andrew Lunn
2023-12-16 1:16 ` Daniel Golle
2023-12-12 3:46 ` [RFC PATCH net-next v3 2/8] phy: add driver for MediaTek pextp 10GE SerDes PHY Daniel Golle
2023-12-12 10:41 ` AngeloGioacchino Del Regno
2023-12-13 2:13 ` Chunfeng Yun (云春峰)
2023-12-21 16:48 ` Vinod Koul
2023-12-12 3:47 ` [RFC PATCH net-next v3 3/8] net: pcs: pcs-mtk-lynxi: add platform driver for MT7988 Daniel Golle
2023-12-13 16:04 ` Russell King (Oracle)
2024-02-07 1:29 ` Daniel Golle
2024-04-22 16:23 ` Daniel Golle
2023-12-12 3:47 ` [RFC PATCH net-next v3 4/8] dt-bindings: net: pcs: add bindings for MediaTek USXGMII PCS Daniel Golle
2023-12-12 5:43 ` Rob Herring
2023-12-12 16:24 ` Conor Dooley
2023-12-12 3:47 ` [RFC PATCH net-next v3 5/8] net: pcs: add driver " Daniel Golle
2023-12-12 9:29 ` Simon Horman
2023-12-12 3:48 ` [RFC PATCH net-next v3 6/8] dt-bindings: net: mediatek: remove wrongly added clocks and SerDes Daniel Golle
2023-12-12 5:43 ` Rob Herring
2023-12-12 16:29 ` Conor Dooley
2023-12-12 3:51 ` [RFC PATCH net-next v3 7/8] dt-bindings: net: mediatek,net: fix and complete mt7988-eth binding Daniel Golle
2023-12-12 5:43 ` Rob Herring
2023-12-12 16:34 ` Conor Dooley [this message]
2023-12-13 6:58 ` Krzysztof Kozlowski
2023-12-12 3:51 ` [RFC PATCH net-next v3 8/8] net: ethernet: mtk_eth_soc: add paths and SerDes modes for MT7988 Daniel Golle
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231212-unlinked-audio-94132ec03663@spud \
--to=conor@kernel.org \
--cc=Mark-MC.Lee@mediatek.com \
--cc=SkyLake.Huang@mediatek.com \
--cc=andrew@lunn.ch \
--cc=angelogioacchino.delregno@collabora.com \
--cc=chunfeng.yun@mediatek.com \
--cc=conor+dt@kernel.org \
--cc=daniel@makrotopia.org \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=dqfext@gmail.com \
--cc=edumazet@google.com \
--cc=hkallweit1@gmail.com \
--cc=john@phrozen.org \
--cc=kishon@kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kuba@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=linux-phy@lists.infradead.org \
--cc=linux@armlinux.org.uk \
--cc=lorenzo@kernel.org \
--cc=lynxis@fe80.eu \
--cc=matthias.bgg@gmail.com \
--cc=nbd@nbd.name \
--cc=netdev@vger.kernel.org \
--cc=p.zabel@pengutronix.de \
--cc=pabeni@redhat.com \
--cc=robh+dt@kernel.org \
--cc=sean.wang@mediatek.com \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).