From: Marc Zyngier <maz@kernel.org>
To: Sam Shih <sam.shih@mediatek.com>
Cc: matthias.bgg@gmail.com, Ryder.Lee@mediatek.com,
devicetree@vger.kernel.org, enric.balletbo@collabora.com,
fparent@baylibre.com, gregkh@linuxfoundation.org,
herbert@gondor.apana.org.au, hsinyi@chromium.org,
john@phrozen.org, linus.walleij@linaro.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
linux-crypto@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-serial@vger.kernel.org, linux-watchdog@vger.kernel.org,
linux@roeck-us.net, mpm@selenic.com, mturquette@baylibre.com,
robh+dt@kernel.org, sboyd@kernel.org, sean.wang@kernel.org,
seiya.wang@mediatek.com, wim@linux-watchdog.org
Subject: Re: [v4,9/9] arm64: dts: mediatek: add mt7986b support
Date: Mon, 04 Oct 2021 11:09:16 +0100 [thread overview]
Message-ID: <39193058d8c206e616d7b179762a7829@kernel.org> (raw)
In-Reply-To: <20211004091617.31436-1-sam.shih@mediatek.com>
On 2021-10-04 10:16, Sam Shih wrote:
> Add basic chip support for Mediatek mt7986b, include
> uart nodes with correct clocks, rng node with correct clock,
> and watchdog node and mt7986b pinctrl node.
>
> Add cpu node, timer node, gic node, psci and reserved-memory node
> for ARM Trusted Firmware,
>
> Add clock controller nodes, include 40M clock source, topckgen,
> infracfg,
> apmixedsys and ethernet subsystem.
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
> ---
> v4: added missing gic register bases, and fixed range of GICR
> v3: used the stdout-path instead of console=ttyS0
> v2: modified clock and uart node due to clock driver updated
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 26 +++
> arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 230 +++++++++++++++++++
> 3 files changed, 257 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt7986b.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> b/arch/arm64/boot/dts/mediatek/Makefile
> index e6c3a73b9e4a..d555e43d1ccc 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
> b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
> new file mode 100644
> index 000000000000..95a202505bb2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
> @@ -0,0 +1,26 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2021 MediaTek Inc.
> + * Author: Sam.Shih <sam.shih@mediatek.com>
> + */
> +
> +/dts-v1/;
> +#include "mt7986b.dtsi"
> +
> +/ {
> + model = "MediaTek MT7986b RFB";
> + compatible = "mediatek,mt7986b-rfb";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
> b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
> new file mode 100644
> index 000000000000..06c3381a5170
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
> @@ -0,0 +1,230 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2021 MediaTek Inc.
> + * Author: Sam.Shih <sam.shih@mediatek.com>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/mt7986-clk.h>
> +
> +/ {
> + compatible = "mediatek,mt7986b";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clk40m: oscillator@0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <40000000>;
> + clock-output-names = "clkxtal";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x0>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x1>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x2>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + enable-method = "psci";
> + compatible = "arm,cortex-a53";
> + reg = <0x3>;
> + #cooling-cells = <2>;
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
> + secmon_reserved: secmon@43000000 {
> + reg = <0 0x43000000 0 0x30000>;
> + no-map;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + clock-frequency = <13000000>;
As previously mentioned, please fix your firmware and drop this.
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x40000>, /* GICD */
This is not a valid value for GICD.
Thanks,
M.
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next prev parent reply other threads:[~2021-10-04 10:09 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-14 8:51 [v3,0/9] Add basic SoC support for mediatek mt7986 Sam Shih
2021-09-14 8:51 ` [v3, 1/9] dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC Sam Shih
2021-09-14 8:51 ` [v3,2/9] clk: mediatek: add mt7986 clock IDs Sam Shih
2021-09-14 8:51 ` [RESEND,v2,3/9] clk: mediatek: add mt7986 clock support Sam Shih
2021-09-14 8:51 ` [RESEND, v3, 4/9] pinctrl: mediatek: moore: check if pin_desc is valid before use Sam Shih
2021-09-16 10:07 ` [RESEND,v3,4/9] " Linus Walleij
2021-09-14 8:51 ` [v3,5/9] dt-bindings: pinctrl: update bindings for MT7986 SoC Sam Shih
2021-09-14 18:00 ` Matthias Brugger
2021-09-24 11:44 ` [v4,5/9] " Sam Shih
2021-09-24 13:59 ` Rob Herring
2021-09-27 2:34 ` [v5,5/9] " Sam Shih
2021-09-27 12:23 ` Rob Herring
2021-10-04 9:41 ` [v6,5/9] " Sam Shih
2021-10-12 1:26 ` Rob Herring
2021-09-14 8:51 ` [v4,6/9] pinctrl: mediatek: add support " Sam Shih
2021-09-14 8:51 ` [RESEND,v2,7/9] dt-bindings: arm64: dts: mediatek: Add mt7986 series Sam Shih
2021-09-14 18:00 ` Matthias Brugger
2021-09-24 11:40 ` [v3,7/9] " Sam Shih
2021-10-08 13:53 ` Matthias Brugger
2021-10-12 10:29 ` Sam Shih
2021-10-13 16:08 ` Matthias Brugger
2021-09-14 8:51 ` [RESEND,v2,8/9] arm64: dts: mediatek: add mt7986a support Sam Shih
2021-09-14 17:55 ` Matthias Brugger
2021-09-24 11:20 ` [v3,8/9] " Sam Shih
2021-09-27 12:41 ` Marc Zyngier
2021-10-04 9:12 ` [v4,8/9] " Sam Shih
2021-10-04 10:00 ` Marc Zyngier
2021-10-04 10:07 ` Marc Zyngier
2021-10-04 12:41 ` [v5,8/9] " Sam Shih
2021-09-14 8:51 ` [RESEND,v2,9/9] arm64: dts: mediatek: add mt7986b support Sam Shih
2021-09-24 11:27 ` [v3,9/9] " Sam Shih
2021-10-04 9:16 ` [v4,9/9] " Sam Shih
2021-10-04 10:09 ` Marc Zyngier [this message]
2021-10-04 12:42 ` [v5,9/9] " Sam Shih
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