From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tomasz Figa Subject: Re: [RFC, v3 9/9] media: platform: Add Mediatek ISP P1 shared memory device Date: Fri, 26 Jul 2019 23:04:42 +0900 Message-ID: References: <20190611035344.29814-1-jungo.lin@mediatek.com> <20190611035344.29814-10-jungo.lin@mediatek.com> <20190701072532.GB137710@chromium.org> <1562297618.1212.46.camel@mtksdccf07> <1562313579.1212.73.camel@mtksdccf07> <1563870117.1212.455.camel@mtksdccf07> <20190726074116.GA19745@infradead.org> <4460bc91-352a-7f3a-cbed-1b95e743ca8c@arm.com> <1564142386.1212.621.camel@mtksdccf07> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1564142386.1212.621.camel@mtksdccf07> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Jungo Lin , Robin Murphy Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, =?UTF-8?B?U2VhbiBDaGVuZyAo6YSt5piH5byYKQ==?= , =?UTF-8?B?RnJlZGVyaWMgQ2hlbiAo6Zmz5L+K5YWDKQ==?= , =?UTF-8?B?UnlubiBXdSAo5ZCz6IKy5oGpKQ==?= , srv_heupstream , Rob Herring , =?UTF-8?B?UnlhbiBZdSAo5L2Z5a2f5L+uKQ==?= , =?UTF-8?B?RnJhbmtpZSBDaGl1ICjpgrHmloflh7Ep?= , "list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS" , Matthias Brugger , Sj Huang , "moderated list:ARM/Mediatek SoC support" , Laurent Pinchart , Hans Verkuil , ddavenport-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, Mauro Carvalho Chehab , list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS wrote: > > Hi Robin: > > On Fri, 2019-07-26 at 12:04 +0100, Robin Murphy wrote: > > On 26/07/2019 08:42, Tomasz Figa wrote: > > > On Fri, Jul 26, 2019 at 4:41 PM Christoph Hellwig wrote: > > >> > > >> On Fri, Jul 26, 2019 at 02:15:14PM +0900, Tomasz Figa wrote: > > >>> Could you try dma_get_sgtable() with the SCP struct device and then > > >>> dma_map_sg() with the P1 struct device? > > >> > > >> Please don't do that. dma_get_sgtable is a pretty broken API (see > > >> the common near the arm implementation) and we should not add more > > >> users of it. If you want a piece of memory that can be mapped to > > >> multiple devices allocate it using alloc_pages and then just map > > >> it to each device. > > > > > > Thanks for taking a look at this thread. > > > > > > Unfortunately that wouldn't work. We have a specific reserved memory > > > pool that is the only memory area accessible to one of the devices. > > > Any idea how to handle this? > > > > If it's reserved in the sense of being outside struct-page-backed > > "kernel memory", then provided you have a consistent CPU physical > > address it might be reasonable for other devices to access it via > > dma_map_resource(). > > > > Robin. > > Thank you for your suggestion. > > After revising to use dma_map_resource(), it is worked. Below is the > current implementation. Pleas kindly help us to check if there is any > misunderstanding. > > #define MTK_ISP_COMPOSER_MEM_SIZE 0x200000 > > /* > * Allocate coherent reserved memory for SCP firmware usage. > * The size of SCP composer's memory is fixed to 0x200000 > * for the requirement of firmware. > */ > ptr = dma_alloc_coherent(p1_dev->cam_dev.smem_dev, > MTK_ISP_COMPOSER_MEM_SIZE, &addr, GFP_KERNEL); > if (!ptr) { > dev_err(dev, "failed to allocate compose memory\n"); > return -ENOMEM; > } > p1_dev->composer_scp_addr = addr; > p1_dev->composer_virt_addr = ptr; > dev_dbg(dev, "scp addr:%pad va:%pK\n", &addr, ptr); > > /* > * This reserved memory is also be used by ISP P1 HW. > * Need to get iova address for ISP P1 DMA. > */ > addr = dma_map_resource(dev, addr, MTK_ISP_COMPOSER_MEM_SIZE, > DMA_BIDIRECTIONAL, DMA_ATTR_SKIP_CPU_SYNC); This is still incorrect, because addr is a DMA address, but the second argument to dma_map_resource() is a physical address. > if (dma_mapping_error(dev, addr)) { > dev_err(dev, "Failed to map scp iova\n"); > ret = -ENOMEM; > goto fail_free_mem; > } > p1_dev->composer_iova = addr; > dev_info(dev, "scp iova addr:%pad\n", &addr); > > Moreover, appropriate Tomasz & Christoph's help on this issue. Robin, the memory is specified using the reserved-memory DT binding and managed by the coherent DMA pool framework. We can allocate from it using dma_alloc_coherent(), which gives us a DMA address, not CPU physial address (although in practice on this platform they are equal numerically). Best regards, Tomasz