From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
To: "jason-jh.lin" <jason-jh.lin@mediatek.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Enric Balletbo i Serra <enric.balletbo@collabora.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Hsin-Yi Wang <hsinyi@chromium.org>,
fshao@chromium.org, Moudy Ho <moudy.ho@mediatek.com>,
roy-cw.yeh@mediatek.com, Fabien Parent <fparent@baylibre.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
Nancy Lin <nancy.lin@mediatek.com>,
singo.chang@mediatek.com, DTML <devicetree@vger.kernel.org>,
linux-stm32@st-md-mailman.stormreply.com,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
DRI Development <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH v11 12/16] drm/mediatek: rename the define of register offset
Date: Wed, 29 Sep 2021 22:59:24 +0800 [thread overview]
Message-ID: <CAAOTY_-0=B5GN2evtJcJMguGYnFw5LtEk-LJ=_o_Fb3m840g5w@mail.gmail.com> (raw)
In-Reply-To: <20210921155218.10387-13-jason-jh.lin@mediatek.com>
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年9月21日 週二 下午11:52寫道：
>
> Add DISP_REG prefix for the define of register offset to
> make the difference from the define of register value.
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> rebase on series [1]
>
> [1] drm/mediatek: add support for mediatek SOC MT8192
> - https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 61 +++++++++++----------
> 1 file changed, 31 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 839ffae3019c..b46bc0f5d1a5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -20,32 +20,32 @@
> #include "mtk_drm_ddp_comp.h"
> #include "mtk_drm_crtc.h"
>
> -#define DISP_OD_EN 0x0000
> -#define DISP_OD_CFG 0x0020
> -#define DISP_OD_SIZE 0x0030
> -#define DISP_DITHER_5 0x0114
> -#define DISP_DITHER_7 0x011c
> -#define DISP_DITHER_15 0x013c
> -#define DISP_DITHER_16 0x0140
> +#define DISP_REG_OD_EN 0x0000
> +#define DISP_REG_OD_CFG 0x0020
> +#define DISP_REG_OD_SIZE 0x0030
> +#define DISP_REG_DITHER_5 0x0114
> +#define DISP_REG_DITHER_7 0x011c
> +#define DISP_REG_DITHER_15 0x013c
> +#define DISP_REG_DITHER_16 0x0140
>
> #define DISP_REG_UFO_START 0x0000
>
> -#define DISP_DITHER_EN 0x0000
> +#define DISP_REG_DITHER_EN 0x0000
> #define DITHER_EN BIT(0)
> -#define DISP_DITHER_CFG 0x0020
> +#define DISP_REG_DITHER_CFG 0x0020
> #define DITHER_RELAY_MODE BIT(0)
> #define DITHER_ENGINE_EN BIT(1)
> -#define DISP_DITHER_SIZE 0x0030
> +#define DISP_REG_DITHER_SIZE 0x0030
>
> #define OD_RELAYMODE BIT(0)
>
> #define UFO_BYPASS BIT(2)
>
> -#define DISP_POSTMASK_EN 0x0000
> +#define DISP_REG_POSTMASK_EN 0x0000
> #define POSTMASK_EN BIT(0)
> -#define DISP_POSTMASK_CFG 0x0020
> +#define DISP_REG_POSTMASK_CFG 0x0020
> #define POSTMASK_RELAY_MODE BIT(0)
> -#define DISP_POSTMASK_SIZE 0x0030
> +#define DISP_REG_POSTMASK_SIZE 0x0030
>
> #define DISP_DITHERING BIT(2)
> #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
> @@ -130,19 +130,19 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
> return;
>
> if (bpc >= MTK_MIN_BPC) {
> - mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> - mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_NEW_BIT_MODE,
> - cmdq_reg, regs, DISP_DITHER_15);
> + cmdq_reg, regs, DISP_REG_DITHER_15);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> - cmdq_reg, regs, DISP_DITHER_16);
> + cmdq_reg, regs, DISP_REG_DITHER_16);
> mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
> }
> }
> @@ -162,16 +162,16 @@ static void mtk_od_config(struct device *dev, unsigned int w,
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE);
> - mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG);
> - mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
> + mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
> + mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> }
>
> static void mtk_od_start(struct device *dev)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - writel(1, priv->regs + DISP_OD_EN);
> + writel(1, priv->regs + DISP_REG_OD_EN);
> }
>
> static void mtk_ufoe_start(struct device *dev)
> @@ -188,23 +188,23 @@ static void mtk_postmask_config(struct device *dev, unsigned int w,
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
> - DISP_POSTMASK_SIZE);
> + DISP_REG_POSTMASK_SIZE);
> mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
> - priv->regs, DISP_POSTMASK_CFG);
> + priv->regs, DISP_REG_POSTMASK_CFG);
> }
>
> static void mtk_postmask_start(struct device *dev)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);
> + writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN);
> }
>
> static void mtk_postmask_stop(struct device *dev)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);
> + writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
> }
>
> static void mtk_dither_config(struct device *dev, unsigned int w,
> @@ -213,9 +213,10 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
> - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> - mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG,
> + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
> + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
> + DISP_REG_DITHER_CFG);
> + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
> DITHER_ENGINE_EN, cmdq_pkt);
> }
>
> @@ -223,14 +224,14 @@ static void mtk_dither_start(struct device *dev)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
> + writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
> }
>
> static void mtk_dither_stop(struct device *dev)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
> + writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
> }
>
> static const struct mtk_ddp_comp_funcs ddp_aal = {
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
next prev parent reply other threads:[~2021-09-29 15:01 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-21 15:52 [PATCH v11 00/16] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2021-09-21 15:52 ` [PATCH v11 01/16] dt-bindings: arm: mediatek: mmsys: add power and gce properties jason-jh.lin
2021-09-21 15:52 ` [PATCH v11 02/16] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding jason-jh.lin
2021-09-21 15:52 ` [PATCH v11 03/16] dt-bindings: display: mediatek: disp: split each block to individual yaml jason-jh.lin
2021-09-24 23:41 ` Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 04/16] dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding jason-jh.lin
2021-09-25 2:11 ` Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 05/16] dt-bindings: display: mediatek: merge: add additional prop for mt8195 jason-jh.lin
2021-09-25 2:17 ` Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 06/16] dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0 jason-jh.lin
2021-09-25 2:20 ` Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 07/16] dt-bindings: arm: mediatek: move common module from display folder jason-jh.lin
2021-09-25 2:22 ` Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 08/16] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
2021-09-21 15:52 ` [PATCH v11 09/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
2021-10-14 14:05 ` AngeloGioacchino Del Regno
2021-10-22 10:13 ` Jason-JH Lin
2021-10-25 5:05 ` Fei Shao
2021-10-25 5:33 ` Jason-JH Lin
2021-09-21 15:52 ` [PATCH v11 10/16] soc: mediatek: add mtk-mutex " jason-jh.lin
2021-09-21 15:52 ` [PATCH v11 11/16] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c jason-jh.lin
2021-09-21 15:52 ` [PATCH v11 12/16] drm/mediatek: rename the define of register offset jason-jh.lin
2021-09-29 14:59 ` Chun-Kuang Hu [this message]
2021-09-21 15:52 ` [PATCH v11 13/16] drm/mediatek: adjust to the alphabetic order for mediatek-drm jason-jh.lin
2021-09-29 14:59 ` Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 14/16] drm/mediatek: add DSC support " jason-jh.lin
2021-09-29 15:00 ` Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 15/16] drm/mediatek: add MERGE " jason-jh.lin
2021-10-14 14:27 ` AngeloGioacchino Del Regno
2021-10-22 10:30 ` Jason-JH Lin
2021-09-21 15:52 ` [PATCH v11 16/16] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAAOTY_-0=B5GN2evtJcJMguGYnFw5LtEk-LJ=_o_Fb3m840g5w@mail.gmail.com' \
--to=chunkuang.hu@kernel.org \
--cc=airlied@linux.ie \
--cc=alexandre.torgue@foss.st.com \
--cc=daniel@ffwll.ch \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=enric.balletbo@collabora.com \
--cc=fparent@baylibre.com \
--cc=fshao@chromium.org \
--cc=hsinyi@chromium.org \
--cc=jason-jh.lin@mediatek.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=linux-stm32@st-md-mailman.stormreply.com \
--cc=matthias.bgg@gmail.com \
--cc=mcoquelin.stm32@gmail.com \
--cc=moudy.ho@mediatek.com \
--cc=nancy.lin@mediatek.com \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=roy-cw.yeh@mediatek.com \
--cc=singo.chang@mediatek.com \
--cc=yongqiang.niu@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).