From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
To: Yongqiang Niu <yongqiang.niu@mediatek.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
DTML <devicetree@vger.kernel.org>,
Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@linux.ie>,
linux-kernel <linux-kernel@vger.kernel.org>,
DRI Development <dri-devel@lists.freedesktop.org>,
Project_Global_Chrome_Upstream_Group@mediatek.com,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Hsin-Yi Wang <hsinyi@chromium.org>, CK Hu <ck.hu@mediatek.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3, 03/15] arm64: dts: mt8192: add display node
Date: Tue, 12 Jan 2021 07:41:21 +0800 [thread overview]
Message-ID: <CAAOTY_823uf3sNkzPnH_22MO716ibJMPC7uRzBk=PfkMStvYzQ@mail.gmail.com> (raw)
In-Reply-To: <1610351031-21133-4-git-send-email-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月11日 週一 下午3:48寫道：
>
> add display node
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 +++++++++++++++++++++++++++++++
> 1 file changed, 134 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index e12e024..dcf9fdf 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -15,6 +15,11 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + ovl2-2l2 = &ovl_2l2;
> + rdma4 = &rdma4;
> + };
> +
> clk26m: oscillator0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -508,5 +513,134 @@
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + mmsys: syscon@14000000 {
> + compatible = "mediatek,mt8192-mmsys", "syscon";
> + reg = <0 0x14000000 0 0x1000>;
> + //mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> + // <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mutex: mutex@14001000 {
> + compatible = "mediatek,mt8192-disp-mutex";
> + reg = <0 0x14001000 0 0x1000>;
> + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> + //clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + //mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> + // <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
> + };
> +
> + ovl0: ovl@14005000 {
> + compatible = "mediatek,mt8192-disp-ovl";
> + reg = <0 0x14005000 0 0x1000>;
> + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> + //clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + //iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
I think you should not mark these property.
Regards,
Chun-Kuang.
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> + };
> +
> + ovl_2l0: ovl@14006000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14006000 0 0x1000>;
> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> + };
> +
> + rdma0: rdma@14007000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14007000 0 0x1000>;
> + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> + //clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> + //iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> + //mediatek,larb = <&larb0>;
> + //mediatek,rdma-fifo-size = <5120>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
> + };
> +
> + color0: color@14009000 {
> + compatible = "mediatek,mt8192-disp-color",
> + "mediatek,mt8173-disp-color";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> + };
> +
> + ccorr0: ccorr@1400a000 {
> + compatible = "mediatek,mt8192-disp-ccorr";
> + reg = <0 0x1400a000 0 0x1000>;
> + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> + };
> +
> + aal0: aal@1400b000 {
> + compatible = "mediatek,mt8192-disp-aal";
> + reg = <0 0x1400b000 0 0x1000>;
> + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> + };
> +
> + gamma0: gamma@1400c000 {
> + compatible = "mediatek,mt8183-disp-gamma",
> + "mediatek,mt8192-disp-gamma";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> + };
> +
> + postmask0: postmask@1400d000 {
> + compatible = "mediatek,mt8192-disp-postmask";
> + reg = <0 0x1400d000 0 0x1000>;
> + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> + };
> +
> + dither0: dither@1400e000 {
> + compatible = "mediatek,mt8192-disp-dither",
> + "mediatek,mt8183-disp-dither";
> + reg = <0 0x1400e000 0 0x1000>;
> + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> + };
> +
> + ovl_2l2: ovl@14014000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14014000 0 0x1000>;
> + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> + //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> + // <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> + };
> +
> + rdma4: rdma@14015000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14015000 0 0x1000>;
> + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> + //iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> + //mediatek,rdma-fifo-size = <2048>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> + };
> };
> };
> --
> 1.8.1.1.dirty
> _______________________________________________
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next prev parent reply other threads:[~2021-01-11 23:41 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-11 7:43 [PATCH v3, 00/15] drm/mediatek: add support for mediatek SOC MT8192 Yongqiang Niu
2021-01-11 7:43 ` [PATCH v3, 01/15] dt-bindings: mediatek: add description for postmask Yongqiang Niu
2021-01-11 23:30 ` Chun-Kuang Hu
2021-01-14 19:11 ` Rob Herring
2021-01-14 22:29 ` Chun-Kuang Hu
2021-01-11 7:43 ` [PATCH v3, 02/15] dt-bindings: mediatek: add description for mt8192 display Yongqiang Niu
2021-01-11 23:39 ` Chun-Kuang Hu
2021-01-11 7:43 ` [PATCH v3, 03/15] arm64: dts: mt8192: add display node Yongqiang Niu
2021-01-11 23:41 ` Chun-Kuang Hu [this message]
2021-01-11 7:43 ` [PATCH v3, 04/15] drm/mediatek: add component OVL_2L2 Yongqiang Niu
2021-01-11 23:45 ` Chun-Kuang Hu
2021-01-11 7:43 ` [PATCH v3, 05/15] drm/mediatek: add component POSTMASK Yongqiang Niu
2021-01-11 23:49 ` Chun-Kuang Hu
2021-01-26 7:41 ` Hsin-Yi Wang
2021-01-11 7:43 ` [PATCH v3, 06/15] drm/mediatek: add component RDMA4 Yongqiang Niu
2021-01-11 23:50 ` Chun-Kuang Hu
2021-01-11 7:43 ` [PATCH v3, 07/15] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase Yongqiang Niu
2021-01-11 23:59 ` Chun-Kuang Hu
2021-01-28 0:43 ` Yongqiang Niu
2021-01-11 7:43 ` [PATCH v3, 08/15] drm/mediatek: check if fb is null Yongqiang Niu
2021-01-12 0:20 ` Chun-Kuang Hu
2021-01-11 7:43 ` [PATCH v3, 09/15] drm/mediatek: Add pm runtime support for gamma Yongqiang Niu
2021-01-12 23:09 ` Chun-Kuang Hu
2021-01-11 7:43 ` [PATCH v3, 10/15] drm/mediatek: Add pm runtime support for color Yongqiang Niu
2021-01-11 7:43 ` [PATCH v3, 11/15] drm/mediatek: fix aal size config Yongqiang Niu
2021-01-14 22:55 ` Chun-Kuang Hu
2021-01-11 7:43 ` [PATCH v3, 12/15] drm/mediatek: separate ccorr module Yongqiang Niu
2021-01-12 23:15 ` Chun-Kuang Hu
2021-01-11 7:43 ` [PATCH v3, 13/15] drm/mediatek: add matrix bits private data for ccorr Yongqiang Niu
2021-01-11 7:43 ` [PATCH v3, 14/15] drm/mediatek: add DDP support for MT8192 Yongqiang Niu
2021-01-11 7:43 ` [PATCH v3, 15/15] drm/mediatek: add support for mediatek SOC MT8192 Yongqiang Niu
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