From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
To: "jason-jh.lin" <jason-jh.lin@mediatek.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Enric Balletbo i Serra <enric.balletbo@collabora.com>,
Frank Wunderlich <frank-w@public-files.de>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Fabien Parent <fparent@baylibre.com>,
Hsin-Yi Wang <hsinyi@chromium.org>,
fshao@chromium.org, Yongqiang Niu <yongqiang.niu@mediatek.com>,
Jitao shi <jitao.shi@mediatek.com>,
Nancy Lin <nancy.lin@mediatek.com>,
singo.chang@mediatek.com, DTML <devicetree@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
DRI Development <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH v9 12/14] drm/mediatek: add DSC support for mediatek-drm
Date: Sun, 5 Sep 2021 12:28:19 +0800 [thread overview]
Message-ID: <CAAOTY_8EZKJ48Oq6g9uL_cakyuaMmT7h0VqG=QORYVOxqzYriw@mail.gmail.com> (raw)
In-Reply-To: <20210825144833.7757-13-jason-jh.lin@mediatek.com>
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月25日 週三 下午10:48寫道:
>
> DSC is designed for real-time systems with real-time compression,
> transmission, decompression and display.
> The DSC standard is a specification of the algorithms used for
> compressing and decompressing image display streams, including
> the specification of the syntax and semantics of the compressed
> video bit stream.
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> rebase on [1] series
> [1] drm/mediatek: Separate aal module
> - https://patchwork.kernel.org/project/linux-mediatek/list/?series=516463
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> 2 files changed, 48 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index ef0d2066fae1..0e3ecf97a6fb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -40,6 +40,12 @@
> #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
> #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
>
> +#define DISP_REG_DSC_CON 0x0000
> +#define DSC_EN BIT(0)
> +#define DSC_DUAL_INOUT BIT(2)
> +#define DSC_BYPASS BIT(4)
> +#define DSC_UFOE_SEL BIT(16)
> +
> #define DISP_REG_OD_EN 0x0000
> #define DISP_REG_OD_CFG 0x0020
> #define OD_RELAYMODE BIT(0)
> @@ -175,6 +181,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
> DISP_DITHERING, cmdq_pkt);
> }
>
> +static void mtk_dsc_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + /* dsc bypass mode */
> + mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
> + DISP_REG_DSC_CON, DSC_BYPASS);
> + mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
> + DISP_REG_DSC_CON, DSC_UFOE_SEL);
> + mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
> + DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> +}
> +
> +static void mtk_dsc_start(struct device *dev)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + /* write with mask to reserve the value set in mtk_dsc_config */
> + mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
> +}
> +
> +static void mtk_dsc_stop(struct device *dev)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
> +}
> +
> static void mtk_od_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -238,6 +274,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
> .stop = mtk_dpi_stop,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> + .clk_enable = mtk_ddp_clk_enable,
> + .clk_disable = mtk_ddp_clk_disable,
> + .config = mtk_dsc_config,
> + .start = mtk_dsc_start,
> + .stop = mtk_dsc_stop,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_dsi = {
> .start = mtk_dsi_ddp_start,
> .stop = mtk_dsi_ddp_stop,
> @@ -299,6 +343,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_CCORR] = "ccorr",
> [MTK_DISP_COLOR] = "color",
> [MTK_DISP_DITHER] = "dither",
> + [MTK_DISP_DSC] = "dsc",
> [MTK_DISP_GAMMA] = "gamma",
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> @@ -328,6 +373,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
> [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
> [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
> + [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
> + [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
> [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
> [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index d317b944df66..560be6bc9d0e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_CCORR,
> MTK_DISP_COLOR,
> MTK_DISP_DITHER,
> + MTK_DISP_DSC,
> MTK_DISP_GAMMA,
> MTK_DISP_MUTEX,
> MTK_DISP_OD,
> --
> 2.18.0
>
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next prev parent reply other threads:[~2021-09-05 4:28 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-25 14:48 [PATCH v9 00/14] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2021-08-25 14:48 ` [PATCH v9 01/14] dt-bindings: arm: mediatek: mmsys: add power and gce properties jason-jh.lin
2021-08-25 14:48 ` [PATCH v9 02/14] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding jason-jh.lin
2021-08-25 14:48 ` [PATCH v9 03/14] dt-bindings: mediatek: display: split each block to individual yaml jason-jh.lin
2021-09-03 23:08 ` Chun-Kuang Hu
2021-09-05 4:08 ` Chun-Kuang Hu
2021-08-25 14:48 ` [PATCH v9 04/14] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding jason-jh.lin
2021-09-05 4:11 ` Chun-Kuang Hu
2021-08-25 14:48 ` [PATCH v9 05/14] dt-bindings: mediatek: display: add " jason-jh.lin
2021-09-05 4:16 ` Chun-Kuang Hu
2021-08-25 14:48 ` [PATCH v9 06/14] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
2021-08-25 14:48 ` [PATCH v9 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
2021-08-25 14:48 ` [PATCH v9 08/14] soc: mediatek: add mtk-mutex " jason-jh.lin
2021-08-25 14:48 ` [PATCH v9 09/14] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c jason-jh.lin
2021-09-05 4:18 ` Chun-Kuang Hu
2021-08-25 14:48 ` [PATCH v9 10/14] drm/mediatek: rename the define of register offset jason-jh.lin
2021-09-05 4:20 ` Chun-Kuang Hu
2021-08-25 14:48 ` [PATCH v9 11/14] drm/mediatek: adjust to the alphabetic order for mediatek-drm jason-jh.lin
2021-09-05 4:23 ` Chun-Kuang Hu
2021-08-25 14:48 ` [PATCH v9 12/14] drm/mediatek: add DSC support " jason-jh.lin
2021-09-05 4:28 ` Chun-Kuang Hu [this message]
2021-08-25 14:48 ` [PATCH v9 13/14] drm/mediatek: add MERGE " jason-jh.lin
2021-08-25 14:48 ` [PATCH v9 14/14] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin
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