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From: Hsin-Yi Wang <hsinyi@chromium.org>
To: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Nicolas Boichat <drinkcat@chromium.org>,
	weiyi.lu@mediatek.com, lkml <linux-kernel@vger.kernel.org>,
	Fabien Parent <fparent@baylibre.com>,
	Matthias Brugger <mbrugger@suse.com>,
	"moderated list:ARM/Mediatek SoC support"
	<linux-mediatek@lists.infradead.org>,
	Enric Balletbo i Serra <enric.balletbo@collabora.com>,
	Collabora Kernel ML <kernel@collabora.com>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 11/12] soc: mediatek: pm-domains: Add support for mt8183
Date: Fri, 25 Sep 2020 15:37:34 +0800
Message-ID: <CAJMQK-jFwToRxBdVgtHT3wJ970M0NYGu3kLtkGRBDKMMNOHkJw@mail.gmail.com> (raw)
In-Reply-To: <5e1510f4-b0c4-2cff-b3f8-b6715d228149@gmail.com>

On Wed, Sep 16, 2020 at 8:19 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
>
>
>
> On 16/09/2020 11:46, Matthias Brugger wrote:
> >
> >
> > On 10/09/2020 19:28, Enric Balletbo i Serra wrote:
> >> From: Matthias Brugger <mbrugger@suse.com>
> >>
> >> Add the needed board data to support mt8183 SoC.
> >>
> >> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
> >> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> >> ---
> >>
> >>   drivers/soc/mediatek/mtk-pm-domains.c | 162 ++++++++++++++++++++++++++
> >>   include/linux/soc/mediatek/infracfg.h |  28 +++++
> >>   2 files changed, 190 insertions(+)
> >>
> >> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c
> >> b/drivers/soc/mediatek/mtk-pm-domains.c
> >> index 29e88adc8ea6..aa434f616fee 100644
> >> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> >> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> > [...]
> >> +/*
> >> + * MT8183 power domain support
> >> + */
> >> +static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
> >> +    [MT8183_POWER_DOMAIN_AUDIO] = {
> >> +        .sta_mask = PWR_STATUS_AUDIO,
> >> +        .ctl_offs = 0x0314,
> >> +        .sram_pdn_bits = GENMASK(11, 8),
> >> +        .sram_pdn_ack_bits = GENMASK(15, 12),
> >> +    },
> >> +    [MT8183_POWER_DOMAIN_CONN] = {
> >> +        .sta_mask = PWR_STATUS_CONN,
> >> +        .ctl_offs = 0x032c,
> >> +        .sram_pdn_bits = 0,
> >> +        .sram_pdn_ack_bits = 0,
> >> +        .bp_infracfg = {
> >> +            BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, 0x2a0, 0x2a4, 0x228),
> >
> > We have repeating values triplets for set, clear and status register in infracfg
> > and SMI.
> >
> > Weiyi can you help to get names to this registers? I wasn't able to find
> > anything in the datasheet.
>
> I think for the infracfg part I figured it out:
>
> #define INFRA_TOPAXI_PROTECTEN_SET      0x2a0
> #define INFRA_TOPAXI_PROTECTEN_CLR      0x2a4
> #define INFRA_TOPAXI_PROTECTEN_STA1     0x228
>
> #define INFRA_TOPAXI_PROTECTEN_1_SET    0x2a8
> #define INFRA_TOPAXI_PROTECTEN_1_CLR    0x2ac
> #define INFRA_TOPAXI_PROTECTEN_STA1_1   0x258
>
> #define INFRA_TOPAXI_PROTECTEN_MCU_SET  0x2d4
> #define INFRA_TOPAXI_PROTECTEN_MCU_CLR  0x2d8
> #define INFRA_TOPAXI_PROTECTEN_MM_STA1  0x2ec
>
> Weiyi, can you still provide the register names for the SMI?
>
> Thanks in advance!
> Matthias
>
Hi Matthias,

SMI names are
#define SMI_COMMON_CLAMP_EN 0x3c0
#define SMI_COMMON_CLAMP_EN_SET 0x3c4
#define SMI_COMMON_CLAMP_EN_CLR 0x3c8

Thanks

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Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-10 17:28 [PATCH 00/12] soc: mediatek: pm-domains: Add new driver for SCPSYS power domains controller Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 01/12] dt-bindings: power: Add bindings for the Mediatek " Enric Balletbo i Serra
2020-09-11 23:02   ` Rob Herring
2020-09-14  8:59     ` Matthias Brugger
2020-09-14  9:49       ` Enric Balletbo i Serra
2020-09-22 22:36       ` Rob Herring
2020-09-23 16:12         ` Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 02/12] soc: mediatek: Add MediaTek SCPSYS power domains Enric Balletbo i Serra
2020-09-25 10:25   ` Weiyi Lu
2020-09-25 10:43     ` Matthias Brugger
2020-09-10 17:28 ` [PATCH 03/12] arm64: dts: mediatek: Add mt8173 power domain controller Enric Balletbo i Serra
2020-09-18 20:20   ` Fabien Parent
2020-09-18 20:50     ` Enric Balletbo Serra
2020-09-10 17:28 ` [PATCH 04/12] soc: mediatek: pm-domains: Add bus protection protocol Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 05/12] soc: mediatek: pm_domains: Make bus protection generic Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 06/12] soc: mediatek: pm-domains: Add SMI block as bus protection block Enric Balletbo i Serra
2020-09-25 10:45   ` Weiyi Lu
2020-09-25 11:01     ` Matthias Brugger
2020-09-10 17:28 ` [PATCH 07/12] soc: mediatek: pm-domains: Add extra sram control Enric Balletbo i Serra
2020-09-10 18:27   ` Matthias Brugger
2020-10-26 15:16     ` Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 08/12] soc: mediatek: pm-domains: Add subsystem clocks Enric Balletbo i Serra
2020-09-25 10:55   ` Weiyi Lu
2020-09-25 12:20     ` Matthias Brugger
2020-09-10 17:28 ` [PATCH 09/12] soc: mediatek: pm-domains: Allow bus protection to ignore clear ack Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 10/12] dt-bindings: power: Add MT8183 power domains Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 11/12] soc: mediatek: pm-domains: Add support for mt8183 Enric Balletbo i Serra
2020-09-16  9:46   ` Matthias Brugger
2020-09-16 12:19     ` Matthias Brugger
2020-09-25  7:37       ` Hsin-Yi Wang [this message]
2020-09-25  8:21         ` Enric Balletbo i Serra
2020-09-25  9:07           ` Matthias Brugger
2020-09-10 17:28 ` [PATCH 12/12] arm64: dts: mediatek: Add mt8183 power domains controller Enric Balletbo i Serra
2020-09-25 10:06 ` [PATCH 00/12] soc: mediatek: pm-domains: Add new driver for SCPSYS " Weiyi Lu
2020-09-25 14:04   ` Matthias Brugger
2020-10-06  6:53     ` Weiyi Lu
2020-10-09 12:50       ` Matthias Brugger
2020-10-09 13:57         ` Enric Balletbo i Serra

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