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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wJ2UCTOdHZ1mWOou8w5B04IVAeeeJIqBvX9nSk3ClqQ=; b=4Bc3O4HoF4APpihCZfPc9YzklUsw/wiJjC9iJ8y/fUZ+RlWfOJoGVfsUpGTqe9+773 sYNEXYenHljimJH10Ft5YG7rJqjTVouns6VI3vQwpsRmb7FgRRhrV01X+pOivLzKwa4c y2pkwtZ7EWqnJfbeMvnj+c2fsEF+vDWfEvg73C8xh75vCpx2Z/aTTWdbYg8wwUS6JIyr WTm/MBriZMIuAqOuVV4xk8rStRPsnlw8yOQKiRaBGNO+R9uITXxvqmvW1GDJ1nrgzPtp hhcqCWbQ1wdGoLdyfzNYYCTqXg22HVFCyhUUW9lIm/wH8wPluvJ9+mnJu4UCoS6r8Yjw Uttw== X-Gm-Message-State: AOAM533rkJne+euTZlOrUMBZ/Zi6swbbi+8a3OUACCuAWcQo2fgR6VBP lnCbzLC64CAJAon/LmcBdInEAIlAUw8A4VVSFHcPHw== X-Google-Smtp-Source: ABdhPJzYWvZcshY2MB9EFYsPiJxSD+LRfRy9Mzdvq2XmNz9OcxVwVMzoyqJJK4f3ZhxQaPfqf4O+91KOCSHNNQYSs/Q= X-Received: by 2002:a19:5019:: with SMTP id e25mr20271955lfb.254.1640710698232; Tue, 28 Dec 2021 08:58:18 -0800 (PST) MIME-Version: 1.0 References: <20211216125748.179602-1-angelogioacchino.delregno@collabora.com> <20211216125748.179602-5-angelogioacchino.delregno@collabora.com> In-Reply-To: <20211216125748.179602-5-angelogioacchino.delregno@collabora.com> From: Ulf Hansson Date: Tue, 28 Dec 2021 17:57:41 +0100 Message-ID: Subject: Re: [PATCH 5/5] mmc: mtk-sd: Assign src_clk parent to src_clk_cg for legacy DTs To: AngeloGioacchino Del Regno Cc: chaotian.jing@mediatek.com, matthias.bgg@gmail.com, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211228_085820_559403_DCEF367D X-CRM114-Status: GOOD ( 22.08 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, 16 Dec 2021 at 13:57, AngeloGioacchino Del Regno wrote: > > In commit 3c1a88443698 ("mmc: mediatek: add support of source_cg clock") > an independent cg was introduced to avoid a hardware hang issue during > clock mode switches (subsequent commits will set that clock as optional). > > When this clock is not present in device-tree, any operation is being > done on src_clk's parent (calling clk_get_parent()): to simplify this > and avoid checking for src_clk_cg presence everytime, just assign the > parent clock to src_clk_cg and remove the now useless checks. > > Signed-off-by: AngeloGioacchino Del Regno The series applied for next, thanks! Kind regards Uffe > --- > drivers/mmc/host/mtk-sd.c | 28 ++++++++++++++++------------ > 1 file changed, 16 insertions(+), 12 deletions(-) > > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c > index 59d7decc3051..65037e1d7723 100644 > --- a/drivers/mmc/host/mtk-sd.c > +++ b/drivers/mmc/host/mtk-sd.c > @@ -901,14 +901,8 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) > } > } > sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); > - /* > - * As src_clk/HCLK use the same bit to gate/ungate, > - * So if want to only gate src_clk, need gate its parent(mux). > - */ > - if (host->src_clk_cg) > - clk_disable_unprepare(host->src_clk_cg); > - else > - clk_disable_unprepare(clk_get_parent(host->src_clk)); > + > + clk_disable_unprepare(host->src_clk_cg); > if (host->dev_comp->clk_div_bits == 8) > sdr_set_field(host->base + MSDC_CFG, > MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, > @@ -917,11 +911,8 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) > sdr_set_field(host->base + MSDC_CFG, > MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, > (mode << 12) | div); > - if (host->src_clk_cg) > - clk_prepare_enable(host->src_clk_cg); > - else > - clk_prepare_enable(clk_get_parent(host->src_clk)); > > + clk_prepare_enable(host->src_clk_cg); > readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); > sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); > mmc->actual_clock = sclk; > @@ -2530,6 +2521,19 @@ static int msdc_of_clock_parse(struct platform_device *pdev, > if (IS_ERR(host->src_clk_cg)) > return PTR_ERR(host->src_clk_cg); > > + /* > + * Fallback for legacy device-trees: src_clk and HCLK use the same > + * bit to control gating but they are parented to a different mux, > + * hence if our intention is to gate only the source, required > + * during a clk mode switch to avoid hw hangs, we need to gate > + * its parent (specified as a different clock only on new DTs). > + */ > + if (!host->src_clk_cg) { > + host->src_clk_cg = clk_get_parent(host->src_clk); > + if (IS_ERR(host->src_clk_cg)) > + return PTR_ERR(host->src_clk_cg); > + } > + > host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg"); > if (IS_ERR(host->sys_clk_cg)) > host->sys_clk_cg = NULL; > -- > 2.33.1 > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek