From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Daniel Golle <daniel@makrotopia.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Sabrina Dubroca <sd@queasysnail.net>,
Jianhui Zhao <zhaojh329@gmail.com>,
Chen-Yu Tsai <wenst@chromium.org>,
"Garmin.Chang" <Garmin.Chang@mediatek.com>,
Edward-JW Yang <edward-jw.yang@mediatek.com>,
Johnson Wang <johnson.wang@mediatek.com>,
Sam Shih <sam.shih@mediatek.com>,
Frank Wunderlich <frank-w@public-files.de>,
Dan Carpenter <dan.carpenter@linaro.org>,
James Liao <jamesjj.liao@mediatek.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
netdev@vger.kernel.org
Subject: Re: [PATCH v2 2/4] dt-bindings: clock: mediatek: add clock controllers of MT7988
Date: Tue, 21 Nov 2023 08:39:53 +0100 [thread overview]
Message-ID: <c6e1461a-fd75-4525-8888-0ffef626b77e@linaro.org> (raw)
In-Reply-To: <8a30ae45b55842bc04f57714c8e0a962f3288a67.1700498124.git.daniel@makrotopia.org>
On 20/11/2023 18:18, Daniel Golle wrote:
> Add various clock controllers found in the MT7988 SoC to existing
> bindings (if applicable) and add files for the new ethwarp, mcusys
> and xfi-pll clock controllers not previously present in any SoC.
>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> ---
> v2:
> * dropped unused labels
> * add 'type: object' declaration for reset-controller found in new
> ethwarp controller and represented as ti,syscon-reset
> * rebase on top of
> "dt-bindings: arm: mediatek: move ethsys controller & convert to DT schema"
>
> .../arm/mediatek/mediatek,infracfg.yaml | 1 +
> .../arm/mediatek/mediatek,mt7988-ethwarp.yaml | 61 +++++++++++++++++++
> .../arm/mediatek/mediatek,mt7988-mcusys.yaml | 46 ++++++++++++++
> .../arm/mediatek/mediatek,mt7988-xfi-pll.yaml | 49 +++++++++++++++
> .../bindings/clock/mediatek,apmixedsys.yaml | 1 +
> .../bindings/clock/mediatek,ethsys.yaml | 1 +
> .../bindings/clock/mediatek,topckgen.yaml | 1 +
> .../bindings/net/pcs/mediatek,sgmiisys.yaml | 2 +
> 8 files changed, 162 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-ethwarp.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-mcusys.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-xfi-pll.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
> index ea98043c6ba3d..230b5188a88db 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
> @@ -30,6 +30,7 @@ properties:
> - mediatek,mt7629-infracfg
> - mediatek,mt7981-infracfg
> - mediatek,mt7986-infracfg
> + - mediatek,mt7988-infracfg
> - mediatek,mt8135-infracfg
> - mediatek,mt8167-infracfg
> - mediatek,mt8173-infracfg
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-ethwarp.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-ethwarp.yaml
> new file mode 100644
> index 0000000000000..5b988efe0cb74
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-ethwarp.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7988-ethwarp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT7988 ethwarp Controller
> +
> +maintainers:
> + - Daniel Golle <daniel@makrotopia.org>
> +
> +description:
> + The Mediatek MT7988 ethwarp controller provides clocks and resets for the
> + Ethernet related subsystems found the MT7988 SoC.
Clock controller bindings should be placed in clocks. Definitely not in arm.
> + The reset-controller can be represented using the ti,syscon-reset bindings.
? Why do you rely on TI properties? How is this relevant? Describe here
hardware, not bindings.
> + The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
> +
> +properties:
> + compatible:
> + items:
> + - const: mediatek,mt7988-ethwarp
> + - const: syscon
> + - const: simple-mfd
> +
> + reg:
> + maxItems: 1
> +
> + reset-controller:
> + type: object
Need $ref.
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/reset/ti-syscon.h>
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clock-controller@15031000 {
> + compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
> + reg = <0 0x15031000 0 0x1000>;
> + #clock-cells = <1>;
> +
> + reset-controller {
> + compatible = "ti,syscon-reset";
??? You do not have TI.
> + #reset-cells = <1>;
> + ti,reset-bits = <
> + 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
> + >;
> + };
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-mcusys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-mcusys.yaml
> new file mode 100644
> index 0000000000000..b30bd13616875
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-mcusys.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7988-mcusys.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT7988 MCU System Clock Controller
> +
> +maintainers:
> + - Daniel Golle <daniel@makrotopia.org>
> +
> +description:
> + The Mediatek mcusys controller provides ARM and bus clocks to the system.
> + The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
This binding looks like several other Mediatek bindings. Add it to some
existing binding instead.
> +
> +properties:
> + compatible:
> + items:
> + - const: mediatek,mt7988-mcusys
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
...
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #define MT7988_TOPRGU_XFI_PLL_GRST 16
If you do not have header, use number directly.
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + clock-controller@11f40000 {
> + compatible = "mediatek,mt7988-xfi-pll";
> + reg = <0 0x11f40000 0 0x1000>;
> + resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
> + #clock-cells = <1>;
> + };
> + };
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-11-21 7:40 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-20 17:18 [PATCH v2 1/4] dt-bindings: clock: mediatek: add MT7988 clock IDs Daniel Golle
2023-11-20 17:18 ` [PATCH v2 2/4] dt-bindings: clock: mediatek: add clock controllers of MT7988 Daniel Golle
2023-11-21 7:39 ` Krzysztof Kozlowski [this message]
2023-11-20 17:19 ` [PATCH v2 3/4] clk: mediatek: Add pcw_chg_shift control Daniel Golle
2023-11-20 17:19 ` [PATCH v2 4/4] clk: mediatek: add drivers for MT7988 SoC Daniel Golle
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