From: Matthias Brugger <matthias.bgg@gmail.com>
To: Chao Hao <chao.hao@mediatek.com>, Joerg Roedel <joro@8bytes.org>,
Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
Evan Green <evgreen@chromium.org>,
iommu@lists.linux-foundation.org,
linux-mediatek@lists.infradead.org,
Yong Wu <yong.wu@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 08/10] iommu/mediatek: Extend protect pa alignment value
Date: Mon, 29 Jun 2020 12:17:18 +0200 [thread overview]
Message-ID: <ce29ba24-f89b-4e1e-f98e-fd3497d08e05@gmail.com> (raw)
In-Reply-To: <20200629071310.1557-9-chao.hao@mediatek.com>
On 29/06/2020 09:13, Chao Hao wrote:
> Starting with mt6779, iommu needs to extend to 256 bytes from 128
> bytes which can send the max number of data for memory protection
> pa alignment. So we can use a separate patch to modify it.
>
> Suggested-by: Matthias Brugger <matthias.bgg@gmail.com>
> Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> drivers/iommu/mtk_iommu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 92316c4175a9..8299a3299090 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -98,7 +98,7 @@
> #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
> #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
>
> -#define MTK_PROTECT_PA_ALIGN 128
> +#define MTK_PROTECT_PA_ALIGN 256
>
> /*
> * Get the local arbiter ID and the portid within the larb arbiter
>
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next prev parent reply other threads:[~2020-06-29 10:17 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-29 7:13 [PATCH v5 00/10] MT6779 IOMMU SUPPORT Chao Hao
2020-06-29 7:13 ` [PATCH v5 01/10] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-06-29 7:13 ` [PATCH v5 02/10] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL Chao Hao
2020-07-01 2:17 ` Yong Wu
2020-07-03 2:36 ` chao hao
2020-06-29 7:13 ` [PATCH v5 03/10] iommu/mediatek: Modify the usage of mtk_iommu_plat_data structure Chao Hao
2020-06-29 9:11 ` Matthias Brugger
2020-06-30 10:56 ` Yong Wu
2020-06-30 11:55 ` chao hao
2020-06-29 7:13 ` [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register Chao Hao
2020-06-29 9:28 ` Matthias Brugger
2020-06-30 10:53 ` chao hao
2020-07-01 14:58 ` Matthias Brugger
2020-07-03 2:38 ` chao hao
2020-06-29 7:13 ` [PATCH v5 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data Chao Hao
2020-06-29 7:13 ` [PATCH v5 06/10] iommu/mediatek: Add sub_comm id in translation fault Chao Hao
2020-06-30 10:55 ` Yong Wu
2020-06-30 11:07 ` chao hao
2020-06-29 7:13 ` [PATCH v5 07/10] iommu/mediatek: Add REG_MMU_WR_LEN register definition Chao Hao
2020-06-29 10:16 ` Matthias Brugger
2020-06-30 10:59 ` chao hao
2020-07-01 15:00 ` Matthias Brugger
2020-06-29 7:13 ` [PATCH v5 08/10] iommu/mediatek: Extend protect pa alignment value Chao Hao
2020-06-29 10:17 ` Matthias Brugger [this message]
2020-06-29 7:13 ` [PATCH v5 09/10] iommu/mediatek: Modify MMU_CTRL register setting Chao Hao
2020-06-29 10:28 ` Matthias Brugger
2020-06-30 11:02 ` chao hao
2020-06-29 7:13 ` [PATCH v5 10/10] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-06-29 10:29 ` Matthias Brugger
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