[PATCH v8, 0/4] mailbox: mtk-cmdq: add MT8186 support

[PATCH v8, 0/4] mailbox: mtk-cmdq: add MT8186 support

[Yongqiang Niu]

base linux-next/master
change since v7:
1. instead magic number with marco define
2. adjust gce ddr enable control flow


Yongqiang Niu (4):
  mailbox: mtk-cmdq: add gce software ddr enable private data
  mailbox: mtk-cmdq: instead magic number with GCE_CTRL_BY_SW
  mailbox: mtk-cmdq: add gce ddr enable support flow
  mailbox: mtk-cmdq: add MT8186 support

 drivers/mailbox/mtk-cmdq-mailbox.c | 42 +++++++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

-- 
2.25.1

[PATCH v8, 1/4] mailbox: mtk-cmdq: add gce software ddr enable private data

[Yongqiang Niu]

if gce work control by software, we need set software enable
for MT8186 Soc

there is a handshake flow between gce and ddr hardware,
if not set ddr enable flag of gce, ddr will fall into idle
mode, then gce instructions will not process done.
we need set this flag of gce to tell ddr when gce is idle or busy
controlled by software flow.

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 9465f9081515..88db6b4642db 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -38,6 +38,8 @@
 #define CMDQ_THR_PRIORITY		0x40
 
 #define GCE_GCTL_VALUE			0x48
+#define GCE_CTRL_BY_SW				GENMASK(2, 0)
+#define GCE_DDR_EN				GENMASK(18, 16)
 
 #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
 #define CMDQ_THR_ENABLED		0x1
@@ -80,6 +82,7 @@ struct cmdq {
 	bool			suspended;
 	u8			shift_pa;
 	bool			control_by_sw;
+	bool			sw_ddr_en;
 	u32			gce_num;
 };
 
@@ -87,6 +90,7 @@ struct gce_plat {
 	u32 thread_nr;
 	u8 shift;
 	bool control_by_sw;
+	bool sw_ddr_en;
 	u32 gce_num;
 };
 
@@ -130,6 +134,10 @@ static void cmdq_init(struct cmdq *cmdq)
 	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
 	if (cmdq->control_by_sw)
 		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
+
+	if (cmdq->sw_ddr_en)
+		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+
 	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
 	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
 		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
@@ -543,6 +551,7 @@ static int cmdq_probe(struct platform_device *pdev)
 	cmdq->thread_nr = plat_data->thread_nr;
 	cmdq->shift_pa = plat_data->shift;
 	cmdq->control_by_sw = plat_data->control_by_sw;
+	cmdq->sw_ddr_en = plat_data->sw_ddr_en;
 	cmdq->gce_num = plat_data->gce_num;
 	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
 	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
-- 
2.25.1

[PATCH v8, 2/4] mailbox: mtk-cmdq: instead magic number with GCE_CTRL_BY_SW

[Yongqiang Niu]

instead magic number with GCE_CTRL_BY_SW

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 88db6b4642db..04eb44d89119 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -133,7 +133,7 @@ static void cmdq_init(struct cmdq *cmdq)
 
 	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
 	if (cmdq->control_by_sw)
-		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
+		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
 
 	if (cmdq->sw_ddr_en)
 		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
-- 
2.25.1

[PATCH v8, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow

[Yongqiang Niu]

add gce ddr enable control flow when gce suspend/resume

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 04eb44d89119..2db82ff838ed 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -94,6 +94,18 @@ struct gce_plat {
 	u32 gce_num;
 };
 
+static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
+{
+	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
+
+	if (enable)
+		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+	else
+		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+
+	clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
+}
+
 u8 cmdq_get_shift_pa(struct mbox_chan *chan)
 {
 	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
@@ -319,6 +331,9 @@ static int cmdq_suspend(struct device *dev)
 	if (task_running)
 		dev_warn(dev, "exist running task(s) in suspend\n");
 
+	if (cmdq->sw_ddr_en)
+		cmdq_sw_ddr_enable(cmdq, false);
+
 	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
 
 	return 0;
@@ -330,6 +345,10 @@ static int cmdq_resume(struct device *dev)
 
 	WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
 	cmdq->suspended = false;
+
+	if (cmdq->sw_ddr_en)
+		cmdq_sw_ddr_enable(cmdq, true);
+
 	return 0;
 }
 
@@ -337,6 +356,9 @@ static int cmdq_remove(struct platform_device *pdev)
 {
 	struct cmdq *cmdq = platform_get_drvdata(pdev);
 
+	if (cmdq->sw_ddr_en)
+		cmdq_sw_ddr_enable(cmdq, false);
+
 	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
 	return 0;
 }
-- 
2.25.1

[PATCH v8, 4/4] mailbox: mtk-cmdq: add MT8186 support

[Yongqiang Niu]

add MT8186 cmdq support

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 2db82ff838ed..98eed8d22688 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -691,9 +691,18 @@ static const struct gce_plat gce_plat_v6 = {
 	.gce_num = 2
 };
 
+static const struct gce_plat gce_plat_v7 = {
+	.thread_nr = 24,
+	.shift = 3,
+	.control_by_sw = true,
+	.sw_ddr_en = true,
+	.gce_num = 1
+};
+
 static const struct of_device_id cmdq_of_ids[] = {
 	{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
 	{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
+	{.compatible = "mediatek,mt8186-gce", .data = (void *)&gce_plat_v7},
 	{.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
 	{.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5},
 	{.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v6},
-- 
2.25.1

Re: [PATCH v8, 2/4] mailbox: mtk-cmdq: instead magic number with GCE_CTRL_BY_SW

[CK Hu (胡俊光)]

Hi, Yongqiang:

On Sat, 2022-10-01 at 00:06 +0800, Yongqiang Niu wrote:
> instead magic number with GCE_CTRL_BY_SW

This is a cleanup patch and I would like the cleanup patch to be the
first patch of this series because the cleanup patch could be applied
independently.

Regards,
CK

> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/mailbox/mtk-cmdq-mailbox.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 88db6b4642db..04eb44d89119 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -133,7 +133,7 @@ static void cmdq_init(struct cmdq *cmdq)
>  
>  	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
>  	if (cmdq->control_by_sw)
> -		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
> +		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
>  
>  	if (cmdq->sw_ddr_en)
>  		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> GCE_GCTL_VALUE);

Re: [PATCH v8, 1/4] mailbox: mtk-cmdq: add gce software ddr enable private data

[CK Hu (胡俊光)]

Hi, Yongqiang:

On Sat, 2022-10-01 at 00:06 +0800, Yongqiang Niu wrote:
> if gce work control by software, we need set software enable
> for MT8186 Soc
> 
> there is a handshake flow between gce and ddr hardware,
> if not set ddr enable flag of gce, ddr will fall into idle
> mode, then gce instructions will not process done.
> we need set this flag of gce to tell ddr when gce is idle or busy
> controlled by software flow.
> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 9465f9081515..88db6b4642db 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -38,6 +38,8 @@
>  #define CMDQ_THR_PRIORITY		0x40
>  
>  #define GCE_GCTL_VALUE			0x48
> +#define GCE_CTRL_BY_SW				GENMASK(2, 0)
> +#define GCE_DDR_EN				GENMASK(18, 16)
>  
>  #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
>  #define CMDQ_THR_ENABLED		0x1
> @@ -80,6 +82,7 @@ struct cmdq {
>  	bool			suspended;
>  	u8			shift_pa;
>  	bool			control_by_sw;
> +	bool			sw_ddr_en;
>  	u32			gce_num;
>  };
>  
> @@ -87,6 +90,7 @@ struct gce_plat {
>  	u32 thread_nr;
>  	u8 shift;
>  	bool control_by_sw;
> +	bool sw_ddr_en;
>  	u32 gce_num;
>  };
>  
> @@ -130,6 +134,10 @@ static void cmdq_init(struct cmdq *cmdq)
>  	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
>  	if (cmdq->control_by_sw)
>  		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
> +
> +	if (cmdq->sw_ddr_en)
> +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> GCE_GCTL_VALUE);

I think 0x48[18:16] and 0x48[2:0] control different things and fix
different problem. So for this patch, you should just control
0x48[18:16] and the code would be:

if (cmdq->sw_ddr_en) {
	reg = readl(cmdq->base + GCE_GCTL_VALUE);
	reg |= GCE_DDR_EN;
	writel(reg, cmdq->base + GCE_GCTL_VALUE);
}

Regards,
CK

> +
>  	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base +
> CMDQ_THR_SLOT_CYCLES);
>  	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
>  		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
> @@ -543,6 +551,7 @@ static int cmdq_probe(struct platform_device
> *pdev)
>  	cmdq->thread_nr = plat_data->thread_nr;
>  	cmdq->shift_pa = plat_data->shift;
>  	cmdq->control_by_sw = plat_data->control_by_sw;
> +	cmdq->sw_ddr_en = plat_data->sw_ddr_en;
>  	cmdq->gce_num = plat_data->gce_num;
>  	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
>  	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler,
> IRQF_SHARED,

Re: [PATCH v8, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow

[CK Hu (胡俊光)]

Hi, Yongqiang:

On Sat, 2022-10-01 at 00:06 +0800, Yongqiang Niu wrote:
> add gce ddr enable control flow when gce suspend/resume
> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 04eb44d89119..2db82ff838ed 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -94,6 +94,18 @@ struct gce_plat {
>  	u32 gce_num;
>  };
>  
> +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
> +{
> +	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> +
> +	if (enable)
> +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> GCE_GCTL_VALUE);
> +	else
> +		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
> +
> +	clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
> +}
> +
>  u8 cmdq_get_shift_pa(struct mbox_chan *chan)
>  {
>  	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq,
> mbox);
> @@ -319,6 +331,9 @@ static int cmdq_suspend(struct device *dev)
>  	if (task_running)
>  		dev_warn(dev, "exist running task(s) in suspend\n");
>  
> +	if (cmdq->sw_ddr_en)
> +		cmdq_sw_ddr_enable(cmdq, false);

Why do you disable sw ddr function when suspend? Would the problem
happen when you disable sw ddr function. 

Regards,
CK

> +
>  	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
>  
>  	return 0;
> @@ -330,6 +345,10 @@ static int cmdq_resume(struct device *dev)
>  
>  	WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
>  	cmdq->suspended = false;
> +
> +	if (cmdq->sw_ddr_en)
> +		cmdq_sw_ddr_enable(cmdq, true);
> +
>  	return 0;
>  }
>  
> @@ -337,6 +356,9 @@ static int cmdq_remove(struct platform_device
> *pdev)
>  {
>  	struct cmdq *cmdq = platform_get_drvdata(pdev);
>  
> +	if (cmdq->sw_ddr_en)
> +		cmdq_sw_ddr_enable(cmdq, false);
> +
>  	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
>  	return 0;
>  }

Re: [PATCH v8, 2/4] mailbox: mtk-cmdq: instead magic number with GCE_CTRL_BY_SW

[AngeloGioacchino Del Regno]

Il 30/09/22 18:06, Yongqiang Niu ha scritto:
> instead magic number with GCE_CTRL_BY_SW
> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>

Please fix the commit title and description... an idea:

mailbox: mtk-cmdq: Use GCE_CTRL_BY_SW definition instead of number

P.S.: I agree with CK, please send this as a separate commit.

Regards,
Angelo

Re: [PATCH v8, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow

[AngeloGioacchino Del Regno]

Il 30/09/22 18:06, Yongqiang Niu ha scritto:
> add gce ddr enable control flow when gce suspend/resume
> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>   drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 04eb44d89119..2db82ff838ed 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -94,6 +94,18 @@ struct gce_plat {
>   	u32 gce_num;
>   };
>   
> +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
> +{
> +	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> +
> +	if (enable)
> +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);

My only concern here is about the previous value stored in the GCE_GCTL_VALUE
register, as you're overwriting it in its entirety with
GCE_DDR_EN | GCE_CTRL_BY_SW.

Can you guarantee that this register is not pre-initialized with some value,
and that these are the only bits to be `1` in this register?

Otherwise, you will have to readl and modify the bits instead... by the way,
if this register doesn't get any changes during runtime, you may cache it
at probe time to avoid reading it for every suspend/resume operation.

Regards,
Angelo

Re: [PATCH v8, 2/4] mailbox: mtk-cmdq: instead magic number with GCE_CTRL_BY_SW

[yongqiang.niu]

On Mon, 2022-10-03 at 16:49 +0200, AngeloGioacchino Del Regno wrote:
> Il 30/09/22 18:06, Yongqiang Niu ha scritto:
> > instead magic number with GCE_CTRL_BY_SW
> > 
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> 
> Please fix the commit title and description... an idea:
> 
> mailbox: mtk-cmdq: Use GCE_CTRL_BY_SW definition instead of number
> 
> P.S.: I agree with CK, please send this as a separate commit.
> 
> Regards,
> Angelo
> 
> 


this clean up patch will be moved as the first patch and fix commit
title in next version

Re: [PATCH v8, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow

[yongqiang.niu]

On Mon, 2022-10-03 at 13:04 +0800, CK Hu (胡俊光) wrote:
> Hi, Yongqiang:
> 
> On Sat, 2022-10-01 at 00:06 +0800, Yongqiang Niu wrote:
> > add gce ddr enable control flow when gce suspend/resume
> > 
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> >  drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> > 
> > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> > b/drivers/mailbox/mtk-cmdq-mailbox.c
> > index 04eb44d89119..2db82ff838ed 100644
> > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > @@ -94,6 +94,18 @@ struct gce_plat {
> >  	u32 gce_num;
> >  };
> >  
> > +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
> > +{
> > +	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> > +
> > +	if (enable)
> > +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> > GCE_GCTL_VALUE);
> > +	else
> > +		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
> > +
> > +	clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
> > +}
> > +
> >  u8 cmdq_get_shift_pa(struct mbox_chan *chan)
> >  {
> >  	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq,
> > mbox);
> > @@ -319,6 +331,9 @@ static int cmdq_suspend(struct device *dev)
> >  	if (task_running)
> >  		dev_warn(dev, "exist running task(s) in suspend\n");
> >  
> > +	if (cmdq->sw_ddr_en)
> > +		cmdq_sw_ddr_enable(cmdq, false);
> 
> Why do you disable sw ddr function when suspend? Would the problem
> happen when you disable sw ddr function. 
> 
> Regards,
> CK

when all cmdq instruction task has been processed done,
we need set this gce ddr enable to disable status to tell
cmdq hardware gce there is none task need process, and the hardware
can go into idle mode and no access ddr anymore, then the spm can go
into suspend.

the original issue is gce still access ddr when cmdq suspend function
call, but there is no task run.
so, we need control gce access ddr with this flow.
when cmdq suspend function, there is no task need process, we can
disable gce access ddr, to make sure system go into suspend success.


> 
> > +
> >  	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
> >  
> >  	return 0;
> > @@ -330,6 +345,10 @@ static int cmdq_resume(struct device *dev)
> >  
> >  	WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
> >  	cmdq->suspended = false;
> > +
> > +	if (cmdq->sw_ddr_en)
> > +		cmdq_sw_ddr_enable(cmdq, true);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -337,6 +356,9 @@ static int cmdq_remove(struct platform_device
> > *pdev)
> >  {
> >  	struct cmdq *cmdq = platform_get_drvdata(pdev);
> >  
> > +	if (cmdq->sw_ddr_en)
> > +		cmdq_sw_ddr_enable(cmdq, false);
> > +
> >  	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
> >  	return 0;
> >  }

Re: [PATCH v8, 1/4] mailbox: mtk-cmdq: add gce software ddr enable private data

[yongqiang.niu]

On Mon, 2022-10-03 at 12:00 +0800, CK Hu (胡俊光) wrote:
> Hi, Yongqiang:
> 
> On Sat, 2022-10-01 at 00:06 +0800, Yongqiang Niu wrote:
> > if gce work control by software, we need set software enable
> > for MT8186 Soc
> > 
> > there is a handshake flow between gce and ddr hardware,
> > if not set ddr enable flag of gce, ddr will fall into idle
> > mode, then gce instructions will not process done.
> > we need set this flag of gce to tell ddr when gce is idle or busy
> > controlled by software flow.
> > 
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> >  drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> > b/drivers/mailbox/mtk-cmdq-mailbox.c
> > index 9465f9081515..88db6b4642db 100644
> > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > @@ -38,6 +38,8 @@
> >  #define CMDQ_THR_PRIORITY		0x40
> >  
> >  #define GCE_GCTL_VALUE			0x48
> > +#define GCE_CTRL_BY_SW				GENMASK(2, 0)
> > +#define GCE_DDR_EN				GENMASK(18, 16)
> >  
> >  #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
> >  #define CMDQ_THR_ENABLED		0x1
> > @@ -80,6 +82,7 @@ struct cmdq {
> >  	bool			suspended;
> >  	u8			shift_pa;
> >  	bool			control_by_sw;
> > +	bool			sw_ddr_en;
> >  	u32			gce_num;
> >  };
> >  
> > @@ -87,6 +90,7 @@ struct gce_plat {
> >  	u32 thread_nr;
> >  	u8 shift;
> >  	bool control_by_sw;
> > +	bool sw_ddr_en;
> >  	u32 gce_num;
> >  };
> >  
> > @@ -130,6 +134,10 @@ static void cmdq_init(struct cmdq *cmdq)
> >  	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> >  	if (cmdq->control_by_sw)
> >  		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
> > +
> > +	if (cmdq->sw_ddr_en)
> > +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> > GCE_GCTL_VALUE);
> 
> I think 0x48[18:16]0x48[2:0] and 0x48[2:0] control different things
> and fix
> different problem. So for this patch, you should just control
> 0x48[18:16] and the code would be:
> 
> if (cmdq->sw_ddr_en) {
> 	reg = readl(cmdq->base + GCE_GCTL_VALUE);
> 	reg |= GCE_DDR_EN;
> 	writel(reg, cmdq->base + GCE_GCTL_VALUE);
> }
> 
> Regards,
> CK

0x48[2:0] means control by software
0x48[18:16] means ddr enable 
0x48[2:0] is pre-condition of 0x48[18:16].
if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same
time.


> 
> > +
> >  	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base +
> > CMDQ_THR_SLOT_CYCLES);
> >  	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
> >  		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
> > @@ -543,6 +551,7 @@ static int cmdq_probe(struct platform_device
> > *pdev)
> >  	cmdq->thread_nr = plat_data->thread_nr;
> >  	cmdq->shift_pa = plat_data->shift;
> >  	cmdq->control_by_sw = plat_data->control_by_sw;
> > +	cmdq->sw_ddr_en = plat_data->sw_ddr_en;
> >  	cmdq->gce_num = plat_data->gce_num;
> >  	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
> >  	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler,
> > IRQF_SHARED,

Re: [PATCH v8, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow

[yongqiang.niu]

On Mon, 2022-10-03 at 16:54 +0200, AngeloGioacchino Del Regno wrote:
> Il 30/09/22 18:06, Yongqiang Niu ha scritto:
> > add gce ddr enable control flow when gce suspend/resume
> > 
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> >   drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
> >   1 file changed, 22 insertions(+)
> > 
> > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> > b/drivers/mailbox/mtk-cmdq-mailbox.c
> > index 04eb44d89119..2db82ff838ed 100644
> > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > @@ -94,6 +94,18 @@ struct gce_plat {
> >   	u32 gce_num;
> >   };
> >   
> > +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
> > +{
> > +	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> > +
> > +	if (enable)
> > +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> > GCE_GCTL_VALUE);
> 
> My only concern here is about the previous value stored in the
> GCE_GCTL_VALUE
> register, as you're overwriting it in its entirety with
> GCE_DDR_EN | GCE_CTRL_BY_SW.
> 
> Can you guarantee that this register is not pre-initialized with some
> value,
> and that these are the only bits to be `1` in this register?
> 
> Otherwise, you will have to readl and modify the bits instead... by
> the way,
> if this register doesn't get any changes during runtime, you may
> cache it
> at probe time to avoid reading it for every suspend/resume operation.
> 
> Regards,
> Angelo
> 
> 

0x48[2:0] means control by software
0x48[18:16] means ddr enable 
0x48[2:0] is pre-condition of 0x48[18:16].
if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same
time.
and only these bits is useful, other bits is useless bits

we need set 0x48[18:16] to 0 disable gce access ddr when suspend.
and  set 0x48[18:16] to 0x7 enable gce access ddr when resume, there
will be cmdq client send task to process.
this control flow should controlled in suspend/resume flow.

Re: [PATCH v8, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow

[CK Hu (胡俊光)]

Hi, Yongqiang:

On Tue, 2022-10-04 at 17:30 +0800, yongqiang.niu wrote:
> On Mon, 2022-10-03 at 13:04 +0800, CK Hu (胡俊光) wrote:
> > Hi, Yongqiang:
> > 
> > On Sat, 2022-10-01 at 00:06 +0800, Yongqiang Niu wrote:
> > > add gce ddr enable control flow when gce suspend/resume
> > > 
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > >  drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
> > >  1 file changed, 22 insertions(+)
> > > 
> > > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> > > b/drivers/mailbox/mtk-cmdq-mailbox.c
> > > index 04eb44d89119..2db82ff838ed 100644
> > > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > > @@ -94,6 +94,18 @@ struct gce_plat {
> > >  	u32 gce_num;
> > >  };
> > >  
> > > +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
> > > +{
> > > +	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> > > +
> > > +	if (enable)
> > > +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> > > GCE_GCTL_VALUE);
> > > +	else
> > > +		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
> > > +
> > > +	clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
> > > +}
> > > +
> > >  u8 cmdq_get_shift_pa(struct mbox_chan *chan)
> > >  {
> > >  	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq,
> > > mbox);
> > > @@ -319,6 +331,9 @@ static int cmdq_suspend(struct device *dev)
> > >  	if (task_running)
> > >  		dev_warn(dev, "exist running task(s) in suspend\n");
> > >  
> > > +	if (cmdq->sw_ddr_en)
> > > +		cmdq_sw_ddr_enable(cmdq, false);
> > 
> > Why do you disable sw ddr function when suspend? Would the problem
> > happen when you disable sw ddr function. 
> > 
> > Regards,
> > CK
> 
> when all cmdq instruction task has been processed done,
> we need set this gce ddr enable to disable status to tell
> cmdq hardware gce there is none task need process, and the hardware
> can go into idle mode and no access ddr anymore, then the spm can go
> into suspend.
> 
> the original issue is gce still access ddr when cmdq suspend function
> call, but there is no task run.
> so, we need control gce access ddr with this flow.
> when cmdq suspend function, there is no task need process, we can
> disable gce access ddr, to make sure system go into suspend success.
> 

OK, and add these explanation to commit message.

> 
> > 
> > > +
> > >  	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
> > >  
> > >  	return 0;
> > > @@ -330,6 +345,10 @@ static int cmdq_resume(struct device *dev)
> > >  
> > >  	WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
> > >  	cmdq->suspended = false;
> > > +
> > > +	if (cmdq->sw_ddr_en)
> > > +		cmdq_sw_ddr_enable(cmdq, true);
> > > +
> > >  	return 0;
> > >  }
> > >  
> > > @@ -337,6 +356,9 @@ static int cmdq_remove(struct platform_device
> > > *pdev)
> > >  {
> > >  	struct cmdq *cmdq = platform_get_drvdata(pdev);
> > >  
> > > +	if (cmdq->sw_ddr_en)
> > > +		cmdq_sw_ddr_enable(cmdq, false);
> > > +
> > >  	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
> > >  	return 0;
> > >  }
> 
> 

Re: [PATCH v8, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow

[AngeloGioacchino Del Regno]

Il 04/10/22 11:39, yongqiang.niu ha scritto:
> On Mon, 2022-10-03 at 16:54 +0200, AngeloGioacchino Del Regno wrote:
>> Il 30/09/22 18:06, Yongqiang Niu ha scritto:
>>> add gce ddr enable control flow when gce suspend/resume
>>>
>>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>>> ---
>>>    drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
>>>    1 file changed, 22 insertions(+)
>>>
>>> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
>>> b/drivers/mailbox/mtk-cmdq-mailbox.c
>>> index 04eb44d89119..2db82ff838ed 100644
>>> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
>>> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
>>> @@ -94,6 +94,18 @@ struct gce_plat {
>>>    	u32 gce_num;
>>>    };
>>>    
>>> +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
>>> +{
>>> +	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
>>> +
>>> +	if (enable)
>>> +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
>>> GCE_GCTL_VALUE);
>>
>> My only concern here is about the previous value stored in the
>> GCE_GCTL_VALUE
>> register, as you're overwriting it in its entirety with
>> GCE_DDR_EN | GCE_CTRL_BY_SW.
>>
>> Can you guarantee that this register is not pre-initialized with some
>> value,
>> and that these are the only bits to be `1` in this register?
>>
>> Otherwise, you will have to readl and modify the bits instead... by
>> the way,
>> if this register doesn't get any changes during runtime, you may
>> cache it
>> at probe time to avoid reading it for every suspend/resume operation.
>>
>> Regards,
>> Angelo
>>
>>
> 
> 0x48[2:0] means control by software
> 0x48[18:16] means ddr enable
> 0x48[2:0] is pre-condition of 0x48[18:16].
> if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same
> time.
> and only these bits is useful, other bits is useless bits
> 
> we need set 0x48[18:16] to 0 disable gce access ddr when suspend.
> and  set 0x48[18:16] to 0x7 enable gce access ddr when resume, there
> will be cmdq client send task to process.
> this control flow should controlled in suspend/resume flow.
> 
> 

That's perfect. Thanks for the explanation.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH v8, 1/4] mailbox: mtk-cmdq: add gce software ddr enable private data

[CK Hu (胡俊光)]

Hi, Yongqiang:

On Tue, 2022-10-04 at 17:35 +0800, yongqiang.niu wrote:
> On Mon, 2022-10-03 at 12:00 +0800, CK Hu (胡俊光) wrote:
> > Hi, Yongqiang:
> > 
> > On Sat, 2022-10-01 at 00:06 +0800, Yongqiang Niu wrote:
> > > if gce work control by software, we need set software enable
> > > for MT8186 Soc
> > > 
> > > there is a handshake flow between gce and ddr hardware,
> > > if not set ddr enable flag of gce, ddr will fall into idle
> > > mode, then gce instructions will not process done.
> > > we need set this flag of gce to tell ddr when gce is idle or busy
> > > controlled by software flow.
> > > 
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > >  drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > > 
> > > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> > > b/drivers/mailbox/mtk-cmdq-mailbox.c
> > > index 9465f9081515..88db6b4642db 100644
> > > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > > @@ -38,6 +38,8 @@
> > >  #define CMDQ_THR_PRIORITY		0x40
> > >  
> > >  #define GCE_GCTL_VALUE			0x48
> > > +#define GCE_CTRL_BY_SW				GENMASK(2, 0)
> > > +#define GCE_DDR_EN				GENMASK(18, 16)
> > >  
> > >  #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
> > >  #define CMDQ_THR_ENABLED		0x1
> > > @@ -80,6 +82,7 @@ struct cmdq {
> > >  	bool			suspended;
> > >  	u8			shift_pa;
> > >  	bool			control_by_sw;
> > > +	bool			sw_ddr_en;
> > >  	u32			gce_num;
> > >  };
> > >  
> > > @@ -87,6 +90,7 @@ struct gce_plat {
> > >  	u32 thread_nr;
> > >  	u8 shift;
> > >  	bool control_by_sw;
> > > +	bool sw_ddr_en;
> > >  	u32 gce_num;
> > >  };
> > >  
> > > @@ -130,6 +134,10 @@ static void cmdq_init(struct cmdq *cmdq)
> > >  	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> > >  	if (cmdq->control_by_sw)
> > >  		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
> > > +
> > > +	if (cmdq->sw_ddr_en)
> > > +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> > > GCE_GCTL_VALUE);
> > 
> > I think 0x48[18:16]0x48[2:0] and 0x48[2:0] control different things
> > and fix
> > different problem. So for this patch, you should just control
> > 0x48[18:16] and the code would be:
> > 
> > if (cmdq->sw_ddr_en) {
> > 	reg = readl(cmdq->base + GCE_GCTL_VALUE);
> > 	reg |= GCE_DDR_EN;
> > 	writel(reg, cmdq->base + GCE_GCTL_VALUE);
> > }
> > 
> > Regards,
> > CK
> 
> 0x48[2:0] means control by software
> 0x48[18:16] means ddr enable 
> 0x48[2:0] is pre-condition of 0x48[18:16].
> if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same
> time.

OK, add comment for this.

> 
> 
> > 
> > > +
> > >  	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base +
> > > CMDQ_THR_SLOT_CYCLES);
> > >  	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
> > >  		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
> > > @@ -543,6 +551,7 @@ static int cmdq_probe(struct platform_device
> > > *pdev)
> > >  	cmdq->thread_nr = plat_data->thread_nr;
> > >  	cmdq->shift_pa = plat_data->shift;
> > >  	cmdq->control_by_sw = plat_data->control_by_sw;
> > > +	cmdq->sw_ddr_en = plat_data->sw_ddr_en;
> > >  	cmdq->gce_num = plat_data->gce_num;
> > >  	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
> > >  	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler,
> > > IRQF_SHARED,
> 
>