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Tue, 04 Oct 2022 03:30:46 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 4 Oct 2022 17:30:09 +0800 Received: from mhfsdcap04 (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 4 Oct 2022 17:30:09 +0800 Message-ID: Subject: Re: [PATCH v8, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow From: yongqiang.niu To: CK Hu =?UTF-8?Q?=28=E8=83=A1=E4=BF=8A=E5=85=89=29?= , "chunkuang.hu@kernel.org" CC: "jassisinghbrar@gmail.com" , "matthias.bgg@gmail.com" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-mediatek@lists.infradead.org" , Project_Global_Chrome_Upstream_Group , "hsinyi@chromium.org" Date: Tue, 4 Oct 2022 17:30:08 +0800 In-Reply-To: <31b60ef83260b7f3d0761462c127d3fb34d4f8ac.camel@mediatek.com> References: <20220930160638.7588-1-yongqiang.niu@mediatek.com> <20220930160638.7588-4-yongqiang.niu@mediatek.com> <31b60ef83260b7f3d0761462c127d3fb34d4f8ac.camel@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221004_033051_357668_5C5C0044 X-CRM114-Status: GOOD ( 20.96 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Mon, 2022-10-03 at 13:04 +0800, CK Hu (胡俊光) wrote: > Hi, Yongqiang: > > On Sat, 2022-10-01 at 00:06 +0800, Yongqiang Niu wrote: > > add gce ddr enable control flow when gce suspend/resume > > > > Signed-off-by: Yongqiang Niu > > --- > > drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++ > > 1 file changed, 22 insertions(+) > > > > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c > > b/drivers/mailbox/mtk-cmdq-mailbox.c > > index 04eb44d89119..2db82ff838ed 100644 > > --- a/drivers/mailbox/mtk-cmdq-mailbox.c > > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c > > @@ -94,6 +94,18 @@ struct gce_plat { > > u32 gce_num; > > }; > > > > +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable) > > +{ > > + WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); > > + > > + if (enable) > > + writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + > > GCE_GCTL_VALUE); > > + else > > + writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); > > + > > + clk_bulk_disable(cmdq->gce_num, cmdq->clocks); > > +} > > + > > u8 cmdq_get_shift_pa(struct mbox_chan *chan) > > { > > struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, > > mbox); > > @@ -319,6 +331,9 @@ static int cmdq_suspend(struct device *dev) > > if (task_running) > > dev_warn(dev, "exist running task(s) in suspend\n"); > > > > + if (cmdq->sw_ddr_en) > > + cmdq_sw_ddr_enable(cmdq, false); > > Why do you disable sw ddr function when suspend? Would the problem > happen when you disable sw ddr function. > > Regards, > CK when all cmdq instruction task has been processed done, we need set this gce ddr enable to disable status to tell cmdq hardware gce there is none task need process, and the hardware can go into idle mode and no access ddr anymore, then the spm can go into suspend. the original issue is gce still access ddr when cmdq suspend function call, but there is no task run. so, we need control gce access ddr with this flow. when cmdq suspend function, there is no task need process, we can disable gce access ddr, to make sure system go into suspend success. > > > + > > clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks); > > > > return 0; > > @@ -330,6 +345,10 @@ static int cmdq_resume(struct device *dev) > > > > WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks)); > > cmdq->suspended = false; > > + > > + if (cmdq->sw_ddr_en) > > + cmdq_sw_ddr_enable(cmdq, true); > > + > > return 0; > > } > > > > @@ -337,6 +356,9 @@ static int cmdq_remove(struct platform_device > > *pdev) > > { > > struct cmdq *cmdq = platform_get_drvdata(pdev); > > > > + if (cmdq->sw_ddr_en) > > + cmdq_sw_ddr_enable(cmdq, false); > > + > > clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks); > > return 0; > > }