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* [PATCH V2 1/2] MIPS: Loongson: Rename LOONGSON1 to LOONGSON32
@ 2019-11-04  6:11 Huacai Chen
  2019-11-04  6:11 ` [PATCH V2 2/2] MIPS: Loongson: Unify LOONGSON3/LOONGSON64 Kconfig usage Huacai Chen
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Huacai Chen @ 2019-11-04  6:11 UTC (permalink / raw)
  To: Ralf Baechle, James Hogan
  Cc: Paul Burton, Paul Burton, linux-mips, linux-mips, Fuxin Zhang,
	Zhangjin Wu, Huacai Chen, Huacai Chen

Now old Loongson-2E/2F use LOONGSON2EF and will be removed in future,
newer Loongson-2/3 use LOONGSON64. So rename LOONGSON1 to LOONGSON32
will make the naming style more unified.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/Kconfig                    | 6 +++---
 arch/mips/include/asm/cpu-type.h     | 2 +-
 arch/mips/include/asm/cpu.h          | 2 +-
 arch/mips/include/asm/irqflags.h     | 2 +-
 arch/mips/include/asm/module.h       | 4 ++--
 arch/mips/kernel/cpu-probe.c         | 2 +-
 arch/mips/kernel/idle.c              | 2 +-
 arch/mips/kernel/perf_event_mipsxx.c | 2 +-
 arch/mips/kernel/traps.c             | 2 +-
 arch/mips/loongson32/Kconfig         | 2 +-
 arch/mips/loongson32/Platform        | 4 ++--
 arch/mips/oprofile/common.c          | 2 +-
 arch/mips/oprofile/op_model_mipsxx.c | 2 +-
 13 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7cb8947..02b869d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1511,7 +1511,7 @@ config CPU_LOONGSON2F
 config CPU_LOONGSON1B
 	bool "Loongson 1B"
 	depends on SYS_HAS_CPU_LOONGSON1B
-	select CPU_LOONGSON1
+	select CPU_LOONGSON32
 	select LEDS_GPIO_REGISTER
 	help
 	  The Loongson 1B is a 32-bit SoC, which implements the MIPS32
@@ -1521,7 +1521,7 @@ config CPU_LOONGSON1B
 config CPU_LOONGSON1C
 	bool "Loongson 1C"
 	depends on SYS_HAS_CPU_LOONGSON1C
-	select CPU_LOONGSON1
+	select CPU_LOONGSON32
 	select LEDS_GPIO_REGISTER
 	help
 	  The Loongson 1C is a 32-bit SoC, which implements the MIPS32
@@ -1920,7 +1920,7 @@ config CPU_LOONGSON2EF
 	select ARCH_HAS_PHYS_TO_DMA
 	select CPU_HAS_LOAD_STORE_LR
 
-config CPU_LOONGSON1
+config CPU_LOONGSON32
 	bool
 	select CPU_MIPS32
 	select CPU_MIPSR2
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 5117e91..c46c59b 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -25,7 +25,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
 
 #if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \
     defined(CONFIG_SYS_HAS_CPU_LOONGSON1C)
-	case CPU_LOONGSON1:
+	case CPU_LOONGSON32:
 #endif
 
 #ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 0e3a8d4..ea83078 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -312,7 +312,7 @@ enum cpu_type_enum {
 	 */
 	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
 	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
-	CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON1, CPU_M14KC,
+	CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON32, CPU_M14KC,
 	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
 	CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
 
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index 4d742ac..881754d 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -41,7 +41,7 @@ static inline unsigned long arch_local_irq_save(void)
 	"	.set	push						\n"
 	"	.set	reorder						\n"
 	"	.set	noat						\n"
-#if defined(CONFIG_CPU_LOONGSON64) || defined (CONFIG_CPU_LOONGSON1)
+#if defined(CONFIG_CPU_LOONGSON64) || defined (CONFIG_CPU_LOONGSON32)
 	"	mfc0	%[flags], $12					\n"
 	"	di							\n"
 #else
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 9fe9515..9846047 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -119,8 +119,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "RM7000 "
 #elif defined CONFIG_CPU_SB1
 #define MODULE_PROC_FAMILY "SB1 "
-#elif defined CONFIG_CPU_LOONGSON1
-#define MODULE_PROC_FAMILY "LOONGSON1 "
+#elif defined CONFIG_CPU_LOONGSON32
+#define MODULE_PROC_FAMILY "LOONGSON32 "
 #elif defined CONFIG_CPU_LOONGSON2EF
 #define MODULE_PROC_FAMILY "LOONGSON2EF "
 #elif defined CONFIG_CPU_LOONGSON64
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c849991..105d89c 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1571,7 +1571,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 	case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
 		decode_configs(c);
 
-		c->cputype = CPU_LOONGSON1;
+		c->cputype = CPU_LOONGSON32;
 
 		switch (c->processor_id & PRID_REV_MASK) {
 		case PRID_REV_LOONGSON1B:
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 57dfa6c..37f8e78 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -173,7 +173,7 @@ void __init check_wait(void)
 	case CPU_CAVIUM_OCTEON2:
 	case CPU_CAVIUM_OCTEON3:
 	case CPU_XBURST:
-	case CPU_LOONGSON1:
+	case CPU_LOONGSON32:
 	case CPU_XLR:
 	case CPU_XLP:
 		cpu_wait = r4k_wait;
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 0af456a..128fc99 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1764,7 +1764,7 @@ init_hw_perf_events(void)
 		mipspmu.general_event_map = &mipsxxcore_event_map;
 		mipspmu.cache_event_map = &mipsxxcore_cache_map;
 		break;
-	case CPU_LOONGSON1:
+	case CPU_LOONGSON32:
 		mipspmu.name = "mips/loongson1";
 		mipspmu.general_event_map = &mipsxxcore_event_map;
 		mipspmu.cache_event_map = &mipsxxcore_cache_map;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 0c2570e..83f2a43 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1761,7 +1761,7 @@ static inline void parity_protection_init(void)
 
 	case CPU_5KC:
 	case CPU_5KE:
-	case CPU_LOONGSON1:
+	case CPU_LOONGSON32:
 		write_c0_ecc(0x80000000);
 		back_to_back_c0_hazard();
 		/* Set the PE bit (bit 31) in the c0_errctl register. */
diff --git a/arch/mips/loongson32/Kconfig b/arch/mips/loongson32/Kconfig
index 6dacc14..e27879b 100644
--- a/arch/mips/loongson32/Kconfig
+++ b/arch/mips/loongson32/Kconfig
@@ -38,7 +38,7 @@ endchoice
 menuconfig CEVT_CSRC_LS1X
 	bool "Use PWM Timer for clockevent/clocksource"
 	select MIPS_EXTERNAL_TIMER
-	depends on CPU_LOONGSON1
+	depends on CPU_LOONGSON32
 	help
 	  This option changes the default clockevent/clocksource to PWM Timer,
 	  and is required by Loongson1 CPUFreq support.
diff --git a/arch/mips/loongson32/Platform b/arch/mips/loongson32/Platform
index 3332155..7f8e342 100644
--- a/arch/mips/loongson32/Platform
+++ b/arch/mips/loongson32/Platform
@@ -1,4 +1,4 @@
-cflags-$(CONFIG_CPU_LOONGSON1)		+= -march=mips32r2 -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON32)		+= -march=mips32r2 -Wa,--trap
 platform-$(CONFIG_MACH_LOONGSON32)	+= loongson32/
 cflags-$(CONFIG_MACH_LOONGSON32)	+= -I$(srctree)/arch/mips/include/asm/mach-loongson32
-load-$(CONFIG_CPU_LOONGSON1)		+= 0xffffffff80200000
+load-$(CONFIG_CPU_LOONGSON32)		+= 0xffffffff80200000
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 25cfa70..03db268 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -93,7 +93,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
 	case CPU_P5600:
 	case CPU_I6400:
 	case CPU_M5150:
-	case CPU_LOONGSON1:
+	case CPU_LOONGSON32:
 	case CPU_SB1:
 	case CPU_SB1A:
 	case CPU_R10000:
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 96c13a0..a537bf9 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -420,7 +420,7 @@ static int __init mipsxx_init(void)
 		op_model_mipsxx_ops.cpu_type = "mips/sb1";
 		break;
 
-	case CPU_LOONGSON1:
+	case CPU_LOONGSON32:
 		op_model_mipsxx_ops.cpu_type = "mips/loongson1";
 		break;
 
-- 
2.7.0


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH V2 2/2] MIPS: Loongson: Unify LOONGSON3/LOONGSON64 Kconfig usage
  2019-11-04  6:11 [PATCH V2 1/2] MIPS: Loongson: Rename LOONGSON1 to LOONGSON32 Huacai Chen
@ 2019-11-04  6:11 ` Huacai Chen
  2019-11-09  8:39   ` Jiaxun Yang
  2019-11-09 11:10 ` [PATCH V2 1/2] MIPS: Loongson: Rename LOONGSON1 to LOONGSON32 Huacai Chen
  2019-11-11 19:51 ` Paul Burton
  2 siblings, 1 reply; 5+ messages in thread
From: Huacai Chen @ 2019-11-04  6:11 UTC (permalink / raw)
  To: Ralf Baechle, James Hogan
  Cc: Paul Burton, Paul Burton, linux-mips, linux-mips, Fuxin Zhang,
	Zhangjin Wu, Huacai Chen, Huacai Chen

There are mixed LOONGSON3/LOONGSON64 usages in recently changes, let's
establish some rules:

1, In Kconfig symbols, we only use CPU_LOONGSON64, MACH_LOONGSON64 and
SYS_HAS_CPU_LOONGSON64, all other derived symbols use "LOONGSON3" since
they all not widely-used symbols and sometimes not suitable for all
64-bit Loongson processors. E.g., we use symbols LOONGSON3_ENHANCEMENT,
CPU_LOONGSON3_WORKAROUNDS, etc.

2, Hide GSx64/GSx64E in Kconfig title since it is not useful for
general users. However, in the full description we use a more detailed
manner. E.g., GS264/GS464/GS464E/GS464V.

All Kconfig titles and descriptions of Loongson processors and machines
have also been updated in this patch for consistency.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/Kconfig               | 35 +++++++++++++++++++++--------------
 arch/mips/include/asm/hazards.h |  4 ++--
 arch/mips/loongson64/Kconfig    |  2 +-
 3 files changed, 24 insertions(+), 17 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 02b869d..7831111 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -444,7 +444,7 @@ config LASAT
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config MACH_LOONGSON32
-	bool "Loongson-1 family of machines"
+	bool "Loongson 32-bit family of machines"
 	select SYS_SUPPORTS_ZBOOT
 	help
 	  This enables support for the Loongson-1 family of machines.
@@ -460,7 +460,7 @@ config MACH_LOONGSON2EF
 	  This enables the support of early Loongson-2E/F family of machines.
 
 config MACH_LOONGSON64
-	bool "Loongson-2/3 GSx64 family of machines"
+	bool "Loongson 64-bit family of machines"
 	select ARCH_SPARSEMEM_ENABLE
 	select ARCH_MIGHT_HAVE_PC_PARPORT
 	select ARCH_MIGHT_HAVE_PC_SERIO
@@ -489,8 +489,12 @@ config MACH_LOONGSON64
 	select ZONE_DMA32
 	select NUMA
 	help
-	  This enables the support of Loongson-2/3 family of processors with
-	  GSx64 microarchitecture.
+	  This enables the support of Loongson-2/3 family of machines.
+
+	  Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
+	  GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
+	  and Loongson-2F which will be removed), developed by the Institute
+	  of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
 
 config MACH_PISTACHIO
 	bool "IMG Pistachio SoC based boards"
@@ -1432,7 +1436,7 @@ choice
 	default CPU_R4X00
 
 config CPU_LOONGSON64
-	bool "Loongson GSx64 CPU"
+	bool "Loongson 64-bit CPU"
 	depends on SYS_HAS_CPU_LOONGSON64
 	select ARCH_HAS_PHYS_TO_DMA
 	select CPU_SUPPORTS_64BIT_KERNEL
@@ -1448,17 +1452,20 @@ config CPU_LOONGSON64
 	select GPIOLIB
 	select SWIOTLB
 	help
-		The Loongson GSx64 series of processor cores implements the
-		MIPS64R2 instruction set with many extensions.
+		The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
+		cores implements the MIPS64R2 instruction set with many extensions,
+		including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
+		3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
+		Loongson-2E/2F is not covered here and will be removed in future.
 
-config LOONGSON64_ENHANCEMENT
-	bool "New Loongson GSx64E CPU Enhancements"
+config LOONGSON3_ENHANCEMENT
+	bool "New Loongson-3 CPU Enhancements"
 	default n
 	select CPU_MIPSR2
 	select CPU_HAS_PREFETCH
 	depends on CPU_LOONGSON64
 	help
-	  New Loongson GSx64E cores (since Loongson-3A R2, as opposed to Loongson-3A
+	  New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
 	  R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
 	  FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
 	  Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
@@ -1467,17 +1474,17 @@ config LOONGSON64_ENHANCEMENT
 	  This option enable those enhancements which are not probed at run
 	  time. If you want a generic kernel to run on all Loongson 3 machines,
 	  please say 'N' here. If you want a high-performance kernel to run on
-	  new Loongson 3 machines only, please say 'Y' here.
+	  new Loongson-3 machines only, please say 'Y' here.
 
 config CPU_LOONGSON3_WORKAROUNDS
-	bool "Old Loongson 3 LLSC Workarounds"
+	bool "Old Loongson-3 LLSC Workarounds"
 	default y if SMP
 	depends on CPU_LOONGSON64
 	help
-	  Loongson 3 processors have the llsc issues which require workarounds.
+	  Loongson-3 processors have the llsc issues which require workarounds.
 	  Without workarounds the system may hang unexpectedly.
 
-	  Newer Loongson 3 will fix these issues and no workarounds are needed.
+	  Newer Loongson-3 will fix these issues and no workarounds are needed.
 	  The workarounds have no significant side effect on them but may
 	  decrease the performance of the system so this option should be
 	  disabled unless the kernel is intended to be run on old systems.
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index ea6a8c4..a4f48b0 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -23,7 +23,7 @@
  * TLB hazards
  */
 #if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \
-	!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON64_ENHANCEMENT)
+	!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON3_ENHANCEMENT)
 
 /*
  * MIPSR2 defines ehb for hazard avoidance
@@ -158,7 +158,7 @@ do {									\
 } while (0)
 
 #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
-	defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON64_ENHANCEMENT) || \
+	defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \
 	defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
 
 /*
diff --git a/arch/mips/loongson64/Kconfig b/arch/mips/loongson64/Kconfig
index b1aefd0..48b29c1 100644
--- a/arch/mips/loongson64/Kconfig
+++ b/arch/mips/loongson64/Kconfig
@@ -3,7 +3,7 @@ if MACH_LOONGSON64
 
 config RS780_HPET
 	bool "RS780/SBX00 HPET Timer"
-	depends on CONFIG_MACH_LOONGSON64
+	depends on MACH_LOONGSON64
 	select MIPS_EXTERNAL_TIMER
 	help
 	  This option enables the hpet timer of AMD RS780/SBX00.
-- 
2.7.0


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH V2 2/2] MIPS: Loongson: Unify LOONGSON3/LOONGSON64 Kconfig usage
  2019-11-04  6:11 ` [PATCH V2 2/2] MIPS: Loongson: Unify LOONGSON3/LOONGSON64 Kconfig usage Huacai Chen
@ 2019-11-09  8:39   ` Jiaxun Yang
  0 siblings, 0 replies; 5+ messages in thread
From: Jiaxun Yang @ 2019-11-09  8:39 UTC (permalink / raw)
  To: Huacai Chen, Ralf Baechle, James Hogan
  Cc: Paul Burton, Paul Burton, linux-mips, linux-mips, Fuxin Zhang,
	Zhangjin Wu, Huacai Chen



在 2019/11/4 下午2:11, Huacai Chen 写道:
> There are mixed LOONGSON3/LOONGSON64 usages in recently changes, let's
> establish some rules:
> 
> 1, In Kconfig symbols, we only use CPU_LOONGSON64, MACH_LOONGSON64 and
> SYS_HAS_CPU_LOONGSON64, all other derived symbols use "LOONGSON3" since
> they all not widely-used symbols and sometimes not suitable for all
> 64-bit Loongson processors. E.g., we use symbols LOONGSON3_ENHANCEMENT,
> CPU_LOONGSON3_WORKAROUNDS, etc.
> 
> 2, Hide GSx64/GSx64E in Kconfig title since it is not useful for
> general users. However, in the full description we use a more detailed
> manner. E.g., GS264/GS464/GS464E/GS464V.
> 
> All Kconfig titles and descriptions of Loongson processors and machines
> have also been updated in this patch for consistency.
> 
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---Acked-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Thanks,
I'll obey the rule you established.

--
Jiaxun Yang

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH V2 1/2] MIPS: Loongson: Rename LOONGSON1 to LOONGSON32
  2019-11-04  6:11 [PATCH V2 1/2] MIPS: Loongson: Rename LOONGSON1 to LOONGSON32 Huacai Chen
  2019-11-04  6:11 ` [PATCH V2 2/2] MIPS: Loongson: Unify LOONGSON3/LOONGSON64 Kconfig usage Huacai Chen
@ 2019-11-09 11:10 ` Huacai Chen
  2019-11-11 19:51 ` Paul Burton
  2 siblings, 0 replies; 5+ messages in thread
From: Huacai Chen @ 2019-11-09 11:10 UTC (permalink / raw)
  To: Ralf Baechle, James Hogan
  Cc: Paul Burton, Paul Burton, Linux MIPS Mailing List,
	open list:MIPS, Fuxin Zhang, Zhangjin Wu

Hi, Paul,

On Mon, Nov 4, 2019 at 2:08 PM Huacai Chen <chenhc@lemote.com> wrote:
>
> Now old Loongson-2E/2F use LOONGSON2EF and will be removed in future,
> newer Loongson-2/3 use LOONGSON64. So rename LOONGSON1 to LOONGSON32
> will make the naming style more unified.
I think it is important to make Kconfig symbols stable, so could you
please review this seris and make all
LOONGSON32/LOONGSON64/LOONGSON2EF symbols renaming be completed in the
5.5 cycle.

Thanks,
Huacai

>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
>  arch/mips/Kconfig                    | 6 +++---
>  arch/mips/include/asm/cpu-type.h     | 2 +-
>  arch/mips/include/asm/cpu.h          | 2 +-
>  arch/mips/include/asm/irqflags.h     | 2 +-
>  arch/mips/include/asm/module.h       | 4 ++--
>  arch/mips/kernel/cpu-probe.c         | 2 +-
>  arch/mips/kernel/idle.c              | 2 +-
>  arch/mips/kernel/perf_event_mipsxx.c | 2 +-
>  arch/mips/kernel/traps.c             | 2 +-
>  arch/mips/loongson32/Kconfig         | 2 +-
>  arch/mips/loongson32/Platform        | 4 ++--
>  arch/mips/oprofile/common.c          | 2 +-
>  arch/mips/oprofile/op_model_mipsxx.c | 2 +-
>  13 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 7cb8947..02b869d 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -1511,7 +1511,7 @@ config CPU_LOONGSON2F
>  config CPU_LOONGSON1B
>         bool "Loongson 1B"
>         depends on SYS_HAS_CPU_LOONGSON1B
> -       select CPU_LOONGSON1
> +       select CPU_LOONGSON32
>         select LEDS_GPIO_REGISTER
>         help
>           The Loongson 1B is a 32-bit SoC, which implements the MIPS32
> @@ -1521,7 +1521,7 @@ config CPU_LOONGSON1B
>  config CPU_LOONGSON1C
>         bool "Loongson 1C"
>         depends on SYS_HAS_CPU_LOONGSON1C
> -       select CPU_LOONGSON1
> +       select CPU_LOONGSON32
>         select LEDS_GPIO_REGISTER
>         help
>           The Loongson 1C is a 32-bit SoC, which implements the MIPS32
> @@ -1920,7 +1920,7 @@ config CPU_LOONGSON2EF
>         select ARCH_HAS_PHYS_TO_DMA
>         select CPU_HAS_LOAD_STORE_LR
>
> -config CPU_LOONGSON1
> +config CPU_LOONGSON32
>         bool
>         select CPU_MIPS32
>         select CPU_MIPSR2
> diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
> index 5117e91..c46c59b 100644
> --- a/arch/mips/include/asm/cpu-type.h
> +++ b/arch/mips/include/asm/cpu-type.h
> @@ -25,7 +25,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
>
>  #if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \
>      defined(CONFIG_SYS_HAS_CPU_LOONGSON1C)
> -       case CPU_LOONGSON1:
> +       case CPU_LOONGSON32:
>  #endif
>
>  #ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
> index 0e3a8d4..ea83078 100644
> --- a/arch/mips/include/asm/cpu.h
> +++ b/arch/mips/include/asm/cpu.h
> @@ -312,7 +312,7 @@ enum cpu_type_enum {
>          */
>         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
>         CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
> -       CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON1, CPU_M14KC,
> +       CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON32, CPU_M14KC,
>         CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
>         CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
>
> diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
> index 4d742ac..881754d 100644
> --- a/arch/mips/include/asm/irqflags.h
> +++ b/arch/mips/include/asm/irqflags.h
> @@ -41,7 +41,7 @@ static inline unsigned long arch_local_irq_save(void)
>         "       .set    push                                            \n"
>         "       .set    reorder                                         \n"
>         "       .set    noat                                            \n"
> -#if defined(CONFIG_CPU_LOONGSON64) || defined (CONFIG_CPU_LOONGSON1)
> +#if defined(CONFIG_CPU_LOONGSON64) || defined (CONFIG_CPU_LOONGSON32)
>         "       mfc0    %[flags], $12                                   \n"
>         "       di                                                      \n"
>  #else
> diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
> index 9fe9515..9846047 100644
> --- a/arch/mips/include/asm/module.h
> +++ b/arch/mips/include/asm/module.h
> @@ -119,8 +119,8 @@ search_module_dbetables(unsigned long addr)
>  #define MODULE_PROC_FAMILY "RM7000 "
>  #elif defined CONFIG_CPU_SB1
>  #define MODULE_PROC_FAMILY "SB1 "
> -#elif defined CONFIG_CPU_LOONGSON1
> -#define MODULE_PROC_FAMILY "LOONGSON1 "
> +#elif defined CONFIG_CPU_LOONGSON32
> +#define MODULE_PROC_FAMILY "LOONGSON32 "
>  #elif defined CONFIG_CPU_LOONGSON2EF
>  #define MODULE_PROC_FAMILY "LOONGSON2EF "
>  #elif defined CONFIG_CPU_LOONGSON64
> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
> index c849991..105d89c 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -1571,7 +1571,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
>         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
>                 decode_configs(c);
>
> -               c->cputype = CPU_LOONGSON1;
> +               c->cputype = CPU_LOONGSON32;
>
>                 switch (c->processor_id & PRID_REV_MASK) {
>                 case PRID_REV_LOONGSON1B:
> diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
> index 57dfa6c..37f8e78 100644
> --- a/arch/mips/kernel/idle.c
> +++ b/arch/mips/kernel/idle.c
> @@ -173,7 +173,7 @@ void __init check_wait(void)
>         case CPU_CAVIUM_OCTEON2:
>         case CPU_CAVIUM_OCTEON3:
>         case CPU_XBURST:
> -       case CPU_LOONGSON1:
> +       case CPU_LOONGSON32:
>         case CPU_XLR:
>         case CPU_XLP:
>                 cpu_wait = r4k_wait;
> diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
> index 0af456a..128fc99 100644
> --- a/arch/mips/kernel/perf_event_mipsxx.c
> +++ b/arch/mips/kernel/perf_event_mipsxx.c
> @@ -1764,7 +1764,7 @@ init_hw_perf_events(void)
>                 mipspmu.general_event_map = &mipsxxcore_event_map;
>                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
>                 break;
> -       case CPU_LOONGSON1:
> +       case CPU_LOONGSON32:
>                 mipspmu.name = "mips/loongson1";
>                 mipspmu.general_event_map = &mipsxxcore_event_map;
>                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index 0c2570e..83f2a43 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -1761,7 +1761,7 @@ static inline void parity_protection_init(void)
>
>         case CPU_5KC:
>         case CPU_5KE:
> -       case CPU_LOONGSON1:
> +       case CPU_LOONGSON32:
>                 write_c0_ecc(0x80000000);
>                 back_to_back_c0_hazard();
>                 /* Set the PE bit (bit 31) in the c0_errctl register. */
> diff --git a/arch/mips/loongson32/Kconfig b/arch/mips/loongson32/Kconfig
> index 6dacc14..e27879b 100644
> --- a/arch/mips/loongson32/Kconfig
> +++ b/arch/mips/loongson32/Kconfig
> @@ -38,7 +38,7 @@ endchoice
>  menuconfig CEVT_CSRC_LS1X
>         bool "Use PWM Timer for clockevent/clocksource"
>         select MIPS_EXTERNAL_TIMER
> -       depends on CPU_LOONGSON1
> +       depends on CPU_LOONGSON32
>         help
>           This option changes the default clockevent/clocksource to PWM Timer,
>           and is required by Loongson1 CPUFreq support.
> diff --git a/arch/mips/loongson32/Platform b/arch/mips/loongson32/Platform
> index 3332155..7f8e342 100644
> --- a/arch/mips/loongson32/Platform
> +++ b/arch/mips/loongson32/Platform
> @@ -1,4 +1,4 @@
> -cflags-$(CONFIG_CPU_LOONGSON1)         += -march=mips32r2 -Wa,--trap
> +cflags-$(CONFIG_CPU_LOONGSON32)                += -march=mips32r2 -Wa,--trap
>  platform-$(CONFIG_MACH_LOONGSON32)     += loongson32/
>  cflags-$(CONFIG_MACH_LOONGSON32)       += -I$(srctree)/arch/mips/include/asm/mach-loongson32
> -load-$(CONFIG_CPU_LOONGSON1)           += 0xffffffff80200000
> +load-$(CONFIG_CPU_LOONGSON32)          += 0xffffffff80200000
> diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
> index 25cfa70..03db268 100644
> --- a/arch/mips/oprofile/common.c
> +++ b/arch/mips/oprofile/common.c
> @@ -93,7 +93,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
>         case CPU_P5600:
>         case CPU_I6400:
>         case CPU_M5150:
> -       case CPU_LOONGSON1:
> +       case CPU_LOONGSON32:
>         case CPU_SB1:
>         case CPU_SB1A:
>         case CPU_R10000:
> diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
> index 96c13a0..a537bf9 100644
> --- a/arch/mips/oprofile/op_model_mipsxx.c
> +++ b/arch/mips/oprofile/op_model_mipsxx.c
> @@ -420,7 +420,7 @@ static int __init mipsxx_init(void)
>                 op_model_mipsxx_ops.cpu_type = "mips/sb1";
>                 break;
>
> -       case CPU_LOONGSON1:
> +       case CPU_LOONGSON32:
>                 op_model_mipsxx_ops.cpu_type = "mips/loongson1";
>                 break;
>
> --
> 2.7.0
>

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH V2 1/2] MIPS: Loongson: Rename LOONGSON1 to LOONGSON32
  2019-11-04  6:11 [PATCH V2 1/2] MIPS: Loongson: Rename LOONGSON1 to LOONGSON32 Huacai Chen
  2019-11-04  6:11 ` [PATCH V2 2/2] MIPS: Loongson: Unify LOONGSON3/LOONGSON64 Kconfig usage Huacai Chen
  2019-11-09 11:10 ` [PATCH V2 1/2] MIPS: Loongson: Rename LOONGSON1 to LOONGSON32 Huacai Chen
@ 2019-11-11 19:51 ` Paul Burton
  2 siblings, 0 replies; 5+ messages in thread
From: Paul Burton @ 2019-11-11 19:51 UTC (permalink / raw)
  To: Huacai Chen
  Cc: Ralf Baechle, James Hogan, Paul Burton, Paul Burton, linux-mips,
	linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Huacai Chen,
	linux-mips

Hello,

Huacai Chen wrote:
> Now old Loongson-2E/2F use LOONGSON2EF and will be removed in future,
> newer Loongson-2/3 use LOONGSON64. So rename LOONGSON1 to LOONGSON32
> will make the naming style more unified.

Series applied to mips-next.

> MIPS: Loongson: Rename LOONGSON1 to LOONGSON32
>   commit b2afb64cccd2
>   https://git.kernel.org/mips/c/b2afb64cccd2
>   
>   Signed-off-by: Huacai Chen <chenhc@lemote.com>
>   [paulburton@kernel.org: Fix checkpatch whitespace warning in irqflags.h]
>   Signed-off-by: Paul Burton <paulburton@kernel.org>
> 
> MIPS: Loongson: Unify LOONGSON3/LOONGSON64 Kconfig usage
>   commit caed1d1b20cb
>   https://git.kernel.org/mips/c/caed1d1b20cb
>   
>   Signed-off-by: Huacai Chen <chenhc@lemote.com>
>   Signed-off-by: Paul Burton <paulburton@kernel.org>

Thanks,
    Paul

[ This message was auto-generated; if you believe anything is incorrect
  then please email paulburton@kernel.org to report it. ]

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-11-11 19:51 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-04  6:11 [PATCH V2 1/2] MIPS: Loongson: Rename LOONGSON1 to LOONGSON32 Huacai Chen
2019-11-04  6:11 ` [PATCH V2 2/2] MIPS: Loongson: Unify LOONGSON3/LOONGSON64 Kconfig usage Huacai Chen
2019-11-09  8:39   ` Jiaxun Yang
2019-11-09 11:10 ` [PATCH V2 1/2] MIPS: Loongson: Rename LOONGSON1 to LOONGSON32 Huacai Chen
2019-11-11 19:51 ` Paul Burton

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