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From: "周琰杰 (Zhou Yanjie)" <>
Subject: [PATCH v8 4/5] dt-bindings: pinctrl: Add bindings for Ingenic X1830.
Date: Mon, 16 Dec 2019 00:21:03 +0800	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

Add the pinctrl bindings for the X1830 Soc from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) <>
Acked-by: Rob Herring <>

    New patch.
    No change.
    No change.
    No change.
    No change.
    Change my Signed-off-by from "Zhou Yanjie <>"
    to "周琰杰 (Zhou Yanjie) <>" because
    the old mailbox is in an unstable state.
    Adjust order from [3/4] in v7 to [4/5] in v8.

 Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
index 0014d98..d9b2100 100644
--- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
@@ -10,9 +10,9 @@ GPIO port configuration registers and it is typical to refer to pins using the
 naming scheme "PxN" where x is a character identifying the GPIO port with
 which the pin is associated and N is an integer from 0 to 31 identifying the
 pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
-PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO
-ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780
-contains 6 GPIO ports, PA to PF, for a total of 192 pins.
+PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
+contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
+jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
 Required properties:
@@ -28,6 +28,7 @@ Required properties:
     - "ingenic,x1000-pinctrl"
     - "ingenic,x1000e-pinctrl"
     - "ingenic,x1500-pinctrl"
+    - "ingenic,x1830-pinctrl"
  - reg: Address range of the pinctrl registers.
@@ -40,6 +41,7 @@ Required properties for sub-nodes (GPIO chips):
     - "ingenic,jz4770-gpio"
     - "ingenic,jz4780-gpio"
     - "ingenic,x1000-gpio"
+    - "ingenic,x1830-gpio"
  - reg: The GPIO bank number.
  - interrupt-controller: Marks the device node as an interrupt controller.
  - interrupts: Interrupt specifier for the controllers interrupt.

  parent reply	other threads:[~2019-12-15 16:21 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-15 16:20 Fix bugs in X1000/X1500 and add X1830 pinctrl driver v8 周琰杰 (Zhou Yanjie)
2019-12-15 16:20 ` [PATCH v8 0/5] " 周琰杰 (Zhou Yanjie)
2020-01-06 22:46   ` Linus Walleij
2019-12-15 16:21 ` [PATCH v8 1/5] pinctrl: Ingenic: Fix bugs in X1000 and X1500 周琰杰 (Zhou Yanjie)
2019-12-15 16:21 ` [PATCH v8 2/5] pinctrl: Ingenic: Add missing parts for " 周琰杰 (Zhou Yanjie)
2019-12-15 16:21 ` [PATCH v8 3/5] pinctrl: Ingenic: Introduce reg_offset and use it instead hard code 周琰杰 (Zhou Yanjie)
2019-12-15 16:21 ` 周琰杰 (Zhou Yanjie) [this message]
2019-12-15 16:21 ` [PATCH v8 5/5] pinctrl: Ingenic: Add pinctrl driver for X1830 周琰杰 (Zhou Yanjie)

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