From: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>
To: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
mips-creator-ci20-dev@googlegroups.com, robh+dt@kernel.org,
paul.burton@mips.com, paulburton@kernel.org, jhogan@kernel.org,
mark.rutland@arm.com, syq@debian.org, ralf@linux-mips.org,
rick.tyliu@ingenic.com, jason@lakedaemon.net,
keescook@chromium.org, geert+renesas@glider.be, krzk@kernel.org,
paul@crapouillou.net, prasannatsmkumar@gmail.com,
sernia.zhou@foxmail.com, zhenwenjin@gmail.com,
ebiederm@xmission.com, hns@goldelico.com, paul@boddie.org.uk
Subject: [PATCH v2 3/6] dt-bindings: MIPS: Document Ingenic SoCs binding.
Date: Fri, 17 Jan 2020 01:23:46 +0800 [thread overview]
Message-ID: <1579195429-59828-5-git-send-email-zhouyanjie@wanyeetech.com> (raw)
In-Reply-To: <1579195429-59828-1-git-send-email-zhouyanjie@wanyeetech.com>
Document the available properties for the SoC root node and the
CPU nodes of the devicetree for the Ingenic XBurst SoCs.
Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v1->v2:
Change the two Document from txt to yaml.
.../bindings/mips/ingenic/ingenic,cpu.yaml | 53 ++++++++++++++++++++++
.../bindings/mips/ingenic/ingenic,soc,yaml | 35 ++++++++++++++
2 files changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
new file mode 100644
index 00000000..91041a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic XBurst family CPUs
+
+maintainers:
+ - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
+description: |
+ Ingenic XBurst family CPUs shall have the following properties.
+
+properties:
+ compatible:
+ oneOf:
+ - "ingenic,xburst".
+ - "ingenic,xburst2".
+
+ reg:
+ description: |
+ The number of the CPU.
+
+required:
+ - device_type
+ - compatible
+ - reg
+
+Example:
+ - |
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <0>;
+
+ clocks = <&cgu JZ4780_CLK_CPU>;
+ clock-names = "cpu";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <1>;
+
+ clocks = <&cgu JZ4780_CLK_CORE1>;
+ clock-names = "cpu";
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml
new file mode 100644
index 00000000..6269da7
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/ingenic/ingenic,soc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic SoCs with XBurst CPU inside.
+
+maintainers:
+ - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
+description: |
+ Ingenic SoCs with XBurst CPU inside shall have the following properties.
+
+properties:
+ compatible:
+ oneOf:
+ - "ingenic,jz4740".
+ - "ingenic,jz4725b".
+ - "ingenic,jz4760".
+ - "ingenic,jz4760b".
+ - "ingenic,jz4770".
+ - "ingenic,jz4780".
+ - "ingenic,x1000".
+ - "ingenic,x1000e".
+ - "ingenic,x1500".
+
+required:
+ - compatible
+
+examples:
+ - |
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ingenic,jz4780";
+...
--
2.7.4
next prev parent reply other threads:[~2020-01-16 18:34 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-16 17:23 Introduce SMP support for CI20 (based on JZ4780) v2 周琰杰 (Zhou Yanjie)
2020-01-16 17:23 ` [PATCH v2 0/6] Introduce SMP support for JZ4780 周琰杰 (Zhou Yanjie)
2020-01-16 17:23 ` [PATCH v2 1/6] MIPS: JZ4780: Introduce SMP support 周琰杰 (Zhou Yanjie)
2020-01-17 0:33 ` Jiaxun Yang
2020-01-24 4:54 ` Zhou Yanjie
2020-01-17 2:12 ` Paul Cercueil
2020-01-24 4:56 ` Zhou Yanjie
2020-01-17 3:36 ` Jiaxun Yang
2020-01-16 17:23 ` [PATCH v2 2/6] clocksource: Ingenic: Add high resolution timer support for SMP 周琰杰 (Zhou Yanjie)
2020-01-16 17:23 ` 周琰杰 (Zhou Yanjie) [this message]
2020-01-17 16:31 ` [PATCH v2 3/6] dt-bindings: MIPS: Document Ingenic SoCs binding Rob Herring
2020-01-16 17:23 ` [PATCH v2 4/6] MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-01-16 17:23 ` [PATCH v2 5/6] MIPS: CI20: Modify DTS to support high resolution timer for SMP 周琰杰 (Zhou Yanjie)
2020-01-16 17:23 ` [PATCH v2 6/6] MIPS: CI20: Update defconfig to support SMP 周琰杰 (Zhou Yanjie)
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