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From: Huacai Chen <chenhc@lemote.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Cc: kvm@vger.kernel.org, linux-mips@vger.kernel.org,
	Fuxin Zhang <zhangfx@lemote.com>,
	Huacai Chen <chenhuacai@gmail.com>,
	Jiaxun Yang <jiaxun.yang@flygoat.com>,
	Xing Li <lixing@loongson.cn>, Stable <stable@vger.kernel.org>,
	Huacai Chen <chenhc@lemote.com>
Subject: [PATCH V7 02/15] KVM: MIPS: Fix VPN2_MASK definition for variable cpu_vmbits
Date: Sat, 23 May 2020 15:56:29 +0800
Message-ID: <1590220602-3547-3-git-send-email-chenhc@lemote.com> (raw)
In-Reply-To: <1590220602-3547-1-git-send-email-chenhc@lemote.com>

From: Xing Li <lixing@loongson.cn>

If a CPU support more than 32bit vmbits (which is true for 64bit CPUs),
VPN2_MASK set to fixed 0xffffe000 will lead to a wrong EntryHi in some
functions such as _kvm_mips_host_tlb_inv().

The cpu_vmbits definition of 32bit CPU in cpu-features.h is 31, so we
still use the old definition.

Cc: Stable <stable@vger.kernel.org>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Xing Li <lixing@loongson.cn>
[Huacai: Improve commit messages]
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/include/asm/kvm_host.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index a01cee9..caa2b936 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -274,7 +274,11 @@ enum emulation_result {
 #define MIPS3_PG_SHIFT		6
 #define MIPS3_PG_FRAME		0x3fffffc0
 
+#if defined(CONFIG_64BIT)
+#define VPN2_MASK		GENMASK(cpu_vmbits - 1, 13)
+#else
 #define VPN2_MASK		0xffffe000
+#endif
 #define KVM_ENTRYHI_ASID	cpu_asid_mask(&boot_cpu_data)
 #define TLB_IS_GLOBAL(x)	((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
 #define TLB_VPN2(x)		((x).tlb_hi & VPN2_MASK)
-- 
2.7.0


  parent reply index

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-23  7:56 [PATCH V7 00/15] KVM: MIPS: Add Loongson-3 support (Host Side) Huacai Chen
2020-05-23  7:56 ` [PATCH V7 01/15] KVM: MIPS: Define KVM_ENTRYHI_ASID to cpu_asid_mask(&boot_cpu_data) Huacai Chen
2020-05-23  7:56 ` Huacai Chen [this message]
2020-05-23  7:56 ` [PATCH V7 03/15] KVM: MIPS: Increase KVM_MAX_VCPUS and KVM_USER_MEM_SLOTS to 16 Huacai Chen
2020-05-23  7:56 ` [PATCH V7 04/15] KVM: MIPS: Add EVENTFD support which is needed by VHOST Huacai Chen
2020-05-23  7:56 ` [PATCH V7 05/15] KVM: MIPS: Use lddir/ldpte instructions to lookup gpa_mm.pgd Huacai Chen
2020-05-23  7:56 ` [PATCH V7 06/15] KVM: MIPS: Introduce and use cpu_guest_has_ldpte Huacai Chen
2020-05-23  7:56 ` [PATCH V7 07/15] KVM: MIPS: Use root tlb to control guest's CCA for Loongson-3 Huacai Chen
2020-05-23  7:56 ` [PATCH V7 08/15] KVM: MIPS: Let indexed cacheops cause guest exit on Loongson-3 Huacai Chen
2020-05-23  7:56 ` [PATCH V7 09/15] KVM: MIPS: Add more types of virtual interrupts Huacai Chen
2020-05-23  7:56 ` [PATCH V7 10/15] KVM: MIPS: Add Loongson-3 Virtual IPI interrupt support Huacai Chen
2020-05-23  7:56 ` [PATCH V7 11/15] KVM: MIPS: Add CPUCFG emulation for Loongson-3 Huacai Chen
2020-05-23  7:56 ` [PATCH V7 12/15] KVM: MIPS: Add CONFIG6 and DIAG registers emulation Huacai Chen
2020-05-23 13:27   ` WANG Xuerui
     [not found]     ` <CAHiYmc6YDw7=mqXfMdgSfeR-HVd2Ec+sQVquM=Z6jLke2s-VEw@mail.gmail.com>
2020-05-24  2:45       ` Huacai Chen
2020-05-23  7:56 ` [PATCH V7 13/15] KVM: MIPS: Add more MMIO load/store instructions emulation Huacai Chen
2020-05-23  7:56 ` [PATCH V7 14/15] KVM: MIPS: Enable KVM support for Loongson-3 Huacai Chen
2020-05-23  7:56 ` [PATCH V7 15/15] MAINTAINERS: Update KVM/MIPS maintainers Huacai Chen
2020-05-23  9:01 ` [PATCH V7 00/15] KVM: MIPS: Add Loongson-3 support (Host Side) Aleksandar Markovic

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