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* [PATCH] clk: baikal-t1: Mark Ethernet PLL as critical
@ 2020-09-20 11:03 Serge Semin
  2020-10-14  2:48 ` Stephen Boyd
  0 siblings, 1 reply; 2+ messages in thread
From: Serge Semin @ 2020-09-20 11:03 UTC (permalink / raw)
  To: Michael Turquette, Stephen Boyd
  Cc: Serge Semin, Serge Semin, Alexey Malahov, linux-mips, linux-clk,
	linux-kernel

We've discovered that disabling the so called Ethernet PLL causes reset of
the devices consuming its outgoing clock. The resets happen automatically
even if each underlying clock gate is turned off. Due to that we can't
disable the Ethernet PLL until the kernel is prepared for the corresponding
resets. So for now just mark the PLL clock provider as critical.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: linux-mips@vger.kernel.org
---
 drivers/clk/baikal-t1/clk-ccu-pll.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/baikal-t1/clk-ccu-pll.c b/drivers/clk/baikal-t1/clk-ccu-pll.c
index 1eec8c0b8f50..2445d4b12baf 100644
--- a/drivers/clk/baikal-t1/clk-ccu-pll.c
+++ b/drivers/clk/baikal-t1/clk-ccu-pll.c
@@ -51,11 +51,13 @@ struct ccu_pll_info {
 };
 
 /*
- * Mark as critical all PLLs except Ethernet one. CPU and DDR PLLs are sources
- * of CPU cores and DDR controller reference clocks, due to which they
- * obviously shouldn't be ever gated. SATA and PCIe PLLs are the parents of
- * APB-bus and DDR controller AXI-bus clocks. If they are gated the system will
- * be unusable.
+ * Alas we have to mark all PLLs as critical. CPU and DDR PLLs are sources of
+ * CPU cores and DDR controller reference clocks, due to which they obviously
+ * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
+ * DDR controller AXI-bus clocks. If they are gated the system will be
+ * unusable. Moreover disabling SATA and Ethernet PLLs causes automatic reset
+ * of the corresponding subsystems. So until we aren't ready to re-initialize
+ * all the devices consuming those PLLs, they will be marked as critical too.
  */
 static const struct ccu_pll_info pll_info[] = {
 	CCU_PLL_INFO(CCU_CPU_PLL, "cpu_pll", "ref_clk", CCU_CPU_PLL_BASE,
@@ -67,7 +69,7 @@ static const struct ccu_pll_info pll_info[] = {
 	CCU_PLL_INFO(CCU_PCIE_PLL, "pcie_pll", "ref_clk", CCU_PCIE_PLL_BASE,
 		     CLK_IS_CRITICAL),
 	CCU_PLL_INFO(CCU_ETH_PLL, "eth_pll", "ref_clk", CCU_ETH_PLL_BASE,
-		     CLK_SET_RATE_GATE)
+		     CLK_IS_CRITICAL | CLK_SET_RATE_GATE)
 };
 
 struct ccu_pll_data {
-- 
2.27.0


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] clk: baikal-t1: Mark Ethernet PLL as critical
  2020-09-20 11:03 [PATCH] clk: baikal-t1: Mark Ethernet PLL as critical Serge Semin
@ 2020-10-14  2:48 ` Stephen Boyd
  0 siblings, 0 replies; 2+ messages in thread
From: Stephen Boyd @ 2020-10-14  2:48 UTC (permalink / raw)
  To: Michael Turquette, Serge Semin
  Cc: Serge Semin, Serge Semin, Alexey Malahov, linux-mips, linux-clk,
	linux-kernel

Quoting Serge Semin (2020-09-20 04:03:35)
> We've discovered that disabling the so called Ethernet PLL causes reset of
> the devices consuming its outgoing clock. The resets happen automatically
> even if each underlying clock gate is turned off. Due to that we can't
> disable the Ethernet PLL until the kernel is prepared for the corresponding
> resets. So for now just mark the PLL clock provider as critical.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: linux-mips@vger.kernel.org
> ---

Applied to clk-next

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2020-09-20 11:03 [PATCH] clk: baikal-t1: Mark Ethernet PLL as critical Serge Semin
2020-10-14  2:48 ` Stephen Boyd

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