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Date: Wed, 25 Jan 2017 14:39:36 +0000
From: "Maciej W. Rozycki" <macro@imgtec.com>
Subject: Re: [PATCH v2 1/2] MIPS: ptrace: disallow setting watchpoints in
 kernel address space
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To: James Hogan <james.hogan@imgtec.com>
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On Tue, 24 Jan 2017, Maciej W. Rozycki wrote:

> However if we can prove that we won't need the IP[1:0] bits in scenarios 
> that involve a TLB refill, then we could just quickly do a short sequence, 
> say:
> 
> 	lui	$k0, 1 << 23

 Umm, thinko here, this obviously has to be:

	li	$k0, 1 << 23

or alternatively:

	lui	$k0, 1 << (23 - 16)

(GAS will emit a single LUI instruction in either case).

> 	mtc0	$13, $k0
> 	eret
> 
> Otherwise we'll have to do a full RMW sequence; fortunately a single INS 
> from $0 will do here again to clear CP0.Cause.WP and keep the remaining 
> bits.  Maybe we could do just the same in the regular exception epilogue 
> to avoid the dependency on a hazard (and consequently an issue with QEMU).

 Of course a similar hazard is still there, so the same precautions apply.  

 Also I think we do need to clear CP0.Cause.WP in all cases before ERET, 
including the various exception fast paths, such as in the TLBL/TLBS/TLBM 
handlers, which also means we don't have to fiddle with CP0.EntryHi.ASID 
in handler execution paths that run at EXL entirely to completion.

  Maciej