From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-00010702.pphosted.com ([148.163.156.75]:40366 "EHLO mx0b-00010702.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S23993876AbdCFUGeU-5fU (ORCPT ); Mon, 6 Mar 2017 21:06:34 +0100 From: Nathan Sullivan Subject: [PATCH 1/2] gpio: mmio: add support for NI 169445 NAND GPIO Date: Mon, 6 Mar 2017 14:06:00 -0600 Message-ID: <1488830761-681-2-git-send-email-nathan.sullivan@ni.com> In-Reply-To: <1488830761-681-1-git-send-email-nathan.sullivan@ni.com> References: <1488830761-681-1-git-send-email-nathan.sullivan@ni.com> MIME-Version: 1.0 Content-Type: text/plain Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: linus.walleij@linaro.org, gnurou@gmail.com, mark.rutland@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, ralf@linux-mips.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mips@linux-mips.org, Nathan Sullivan Message-ID: <20170306200600.0NIOE7aWnWWOurd0Q2i-dFrNRGpm2gdE5WLAPID5Wag@z> The GPIO-based NAND controller on National Instruments 169445 hardware exposes a set of simple lines for the control signals. Signed-off-by: Nathan Sullivan --- .../bindings/gpio/ni,169445-nand-gpio.txt | 36 ++++++++++++++++++++++ drivers/gpio/gpio-mmio.c | 1 + 2 files changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt diff --git a/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt b/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt new file mode 100644 index 0000000..ca2c14f --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt @@ -0,0 +1,36 @@ +Bindings for the National Instruments 169445 GPIO NAND controller + +The 169445 GPIO NAND controller has two memory mapped GPIO registers, one +for input (the ready signal) and one for output (control signals). It is +intended to be used with the GPIO NAND driver. + +Required properties: + - compatible: should be "ni,169445-nand-gpio" + - reg-names: must contain + "dat" - data register + - reg: address + size pairs describing the GPIO register sets; + order must correspond with the order of entries in reg-names + - #gpio-cells: must be set to 2. The first cell is the pin number and + the second cell is used to specify the gpio polarity: + 0 = active high + 1 = active low + - gpio-controller: Marks the device node as a gpio controller. + +Examples: + gpio1: nand-gpio-out@1f300010 { + compatible = "ni,169445-nand-gpio"; + reg = <0x1f300010 0x4>; + reg-names = "dat"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <5>; + }; + + gpio2: nand-gpio-in@1f300014 { + compatible = "ni,169445-nand-gpio"; + reg = <0x1f300014 0x4>; + reg-names = "dat"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <1>; + }; diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c index d7d03ad..f7da40e 100644 --- a/drivers/gpio/gpio-mmio.c +++ b/drivers/gpio/gpio-mmio.c @@ -575,6 +575,7 @@ static void __iomem *bgpio_map(struct platform_device *pdev, static const struct of_device_id bgpio_of_match[] = { { .compatible = "brcm,bcm6345-gpio" }, { .compatible = "wd,mbl-gpio" }, + { .compatible = "ni,169445-nand-gpio" }, { } }; MODULE_DEVICE_TABLE(of, bgpio_of_match); -- 2.1.4