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* [PATCH 1/2] MIPS: lantiq: Fix IPI interrupt handling
@ 2019-01-06 18:44 Hauke Mehrtens
  2019-01-06 18:44 ` [PATCH 2/2] MIPS: lantiq: Use CP0_LEGACY_COMPARE_IRQ Hauke Mehrtens
  2019-01-07 21:40 ` [PATCH 1/2] MIPS: lantiq: Fix IPI interrupt handling Paul Burton
  0 siblings, 2 replies; 3+ messages in thread
From: Hauke Mehrtens @ 2019-01-06 18:44 UTC (permalink / raw)
  To: paul.burton
  Cc: jhogan, ralf, john, linux-mips, linux-mips, Hauke Mehrtens, stable

This makes SMP on the vrx200 work again, by removing all the MIPS CPU
interrupt specific code and making it fully use the generic MIPS CPU
interrupt controller.

The mti,cpu-interrupt-controller from irq-mips-cpu.c now handles the CPU
interrupts and also the IPI interrupts which are used to communication
between the CPUs in a SMP system. The generic interrupt code was
already used before but the interrupt vectors were overwritten again
when we called set_vi_handler() in the lantiq interrupt driver and we
also provided our own plat_irq_dispatch() function which overwrote the
weak generic implementation. Now the code uses the generic handler for
the MIPS CPU interrupts including the IPI interrupts and registers a
handler for the CPU interrupts which are handled by the lantiq ICU with
irq_set_chained_handler() which was already called before.

Calling the set_c0_status() function is also not needed any more because
the generic MIPS CPU interrupt already activates the needed bits.

Fixes 1eed40043579 ("MIPS: smp-mt: Use CPU interrupt controller IPI IRQ domain support")
Cc: stable@kernel.org # v4.12
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 arch/mips/lantiq/irq.c | 68 ++++--------------------------------------
 1 file changed, 5 insertions(+), 63 deletions(-)

diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index f0bc3312ed11..c4ef1c31e0c4 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -224,9 +224,11 @@ static struct irq_chip ltq_eiu_type = {
 	.irq_set_type = ltq_eiu_settype,
 };
 
-static void ltq_hw_irqdispatch(int module)
+static void ltq_hw_irq_handler(struct irq_desc *desc)
 {
+	int module = irq_desc_get_irq(desc) - 2;
 	u32 irq;
+	int hwirq;
 
 	irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
 	if (irq == 0)
@@ -237,7 +239,8 @@ static void ltq_hw_irqdispatch(int module)
 	 * other bits might be bogus
 	 */
 	irq = __fls(irq);
-	do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
+	hwirq = irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module);
+	generic_handle_irq(irq_linear_revmap(ltq_domain, hwirq));
 
 	/* if this is a EBU irq, we need to ack it or get a deadlock */
 	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
@@ -245,49 +248,6 @@ static void ltq_hw_irqdispatch(int module)
 			LTQ_EBU_PCC_ISTAT);
 }
 
-#define DEFINE_HWx_IRQDISPATCH(x)					\
-	static void ltq_hw ## x ## _irqdispatch(void)			\
-	{								\
-		ltq_hw_irqdispatch(x);					\
-	}
-DEFINE_HWx_IRQDISPATCH(0)
-DEFINE_HWx_IRQDISPATCH(1)
-DEFINE_HWx_IRQDISPATCH(2)
-DEFINE_HWx_IRQDISPATCH(3)
-DEFINE_HWx_IRQDISPATCH(4)
-
-#if MIPS_CPU_TIMER_IRQ == 7
-static void ltq_hw5_irqdispatch(void)
-{
-	do_IRQ(MIPS_CPU_TIMER_IRQ);
-}
-#else
-DEFINE_HWx_IRQDISPATCH(5)
-#endif
-
-static void ltq_hw_irq_handler(struct irq_desc *desc)
-{
-	ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
-	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
-	int irq;
-
-	if (!pending) {
-		spurious_interrupt();
-		return;
-	}
-
-	pending >>= CAUSEB_IP;
-	while (pending) {
-		irq = fls(pending) - 1;
-		do_IRQ(MIPS_CPU_IRQ_BASE + irq);
-		pending &= ~BIT(irq);
-	}
-}
-
 static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 {
 	struct irq_chip *chip = &ltq_irq_type;
@@ -343,28 +303,10 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
 	for (i = 0; i < MAX_IM; i++)
 		irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
 
-	if (cpu_has_vint) {
-		pr_info("Setting up vectored interrupts\n");
-		set_vi_handler(2, ltq_hw0_irqdispatch);
-		set_vi_handler(3, ltq_hw1_irqdispatch);
-		set_vi_handler(4, ltq_hw2_irqdispatch);
-		set_vi_handler(5, ltq_hw3_irqdispatch);
-		set_vi_handler(6, ltq_hw4_irqdispatch);
-		set_vi_handler(7, ltq_hw5_irqdispatch);
-	}
-
 	ltq_domain = irq_domain_add_linear(node,
 		(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
 		&irq_domain_ops, 0);
 
-#ifndef CONFIG_MIPS_MT_SMP
-	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
-		IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
-#else
-	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
-		IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
-#endif
-
 	/* tell oprofile which irq to use */
 	ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
 
-- 
2.20.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* [PATCH 2/2] MIPS: lantiq: Use CP0_LEGACY_COMPARE_IRQ
  2019-01-06 18:44 [PATCH 1/2] MIPS: lantiq: Fix IPI interrupt handling Hauke Mehrtens
@ 2019-01-06 18:44 ` Hauke Mehrtens
  2019-01-07 21:40 ` [PATCH 1/2] MIPS: lantiq: Fix IPI interrupt handling Paul Burton
  1 sibling, 0 replies; 3+ messages in thread
From: Hauke Mehrtens @ 2019-01-06 18:44 UTC (permalink / raw)
  To: paul.burton; +Cc: jhogan, ralf, john, linux-mips, linux-mips, Hauke Mehrtens

Instead of using the lantiq specific MIPS_CPU_TIMER_IRQ use the generic
CP0_LEGACY_COMPARE_IRQ constant for the timer interrupt number.
MIPS_CPU_TIMER_IRQ was already defined to 7 for both supported SoC
families.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h | 2 --
 arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h   | 2 --
 arch/mips/lantiq/irq.c                                | 9 +--------
 3 files changed, 1 insertion(+), 12 deletions(-)

diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
index c6b63a409641..6dd8ad2409dc 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
@@ -18,8 +18,6 @@
 #define INT_NUM_EXTRA_START		(INT_NUM_IM4_IRL0 + 32)
 #define INT_NUM_IM_OFFSET		(INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
 
-#define MIPS_CPU_TIMER_IRQ			7
-
 #define MAX_IM			5
 
 #endif /* _FALCON_IRQ__ */
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
index 141076325307..0b424214a5e9 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -19,8 +19,6 @@
 
 #define LTQ_DMA_CH0_INT		(INT_NUM_IM2_IRL0)
 
-#define MIPS_CPU_TIMER_IRQ	7
-
 #define MAX_IM			5
 
 #endif
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index c4ef1c31e0c4..6549499eb202 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -310,13 +310,6 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
 	/* tell oprofile which irq to use */
 	ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
 
-	/*
-	 * if the timer irq is not one of the mips irqs we need to
-	 * create a mapping
-	 */
-	if (MIPS_CPU_TIMER_IRQ != 7)
-		irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
-
 	/* the external interrupts are optional and xway only */
 	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
 	if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
@@ -353,7 +346,7 @@ EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
 
 unsigned int get_c0_compare_int(void)
 {
-	return MIPS_CPU_TIMER_IRQ;
+	return CP0_LEGACY_COMPARE_IRQ;
 }
 
 static struct of_device_id __initdata of_irq_ids[] = {
-- 
2.20.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH 1/2] MIPS: lantiq: Fix IPI interrupt handling
  2019-01-06 18:44 [PATCH 1/2] MIPS: lantiq: Fix IPI interrupt handling Hauke Mehrtens
  2019-01-06 18:44 ` [PATCH 2/2] MIPS: lantiq: Use CP0_LEGACY_COMPARE_IRQ Hauke Mehrtens
@ 2019-01-07 21:40 ` Paul Burton
  1 sibling, 0 replies; 3+ messages in thread
From: Paul Burton @ 2019-01-07 21:40 UTC (permalink / raw)
  To: Hauke Mehrtens
  Cc: Paul Burton, jhogan, ralf, john, linux-mips, linux-mips,
	Hauke Mehrtens, stable, linux-mips

Hello,

Hauke Mehrtens wrote:
> This makes SMP on the vrx200 work again, by removing all the MIPS CPU
> interrupt specific code and making it fully use the generic MIPS CPU
> interrupt controller.
> 
> The mti,cpu-interrupt-controller from irq-mips-cpu.c now handles the CPU
> interrupts and also the IPI interrupts which are used to communication
> between the CPUs in a SMP system. The generic interrupt code was
> already used before but the interrupt vectors were overwritten again
> when we called set_vi_handler() in the lantiq interrupt driver and we
> also provided our own plat_irq_dispatch() function which overwrote the
> weak generic implementation. Now the code uses the generic handler for
> the MIPS CPU interrupts including the IPI interrupts and registers a
> handler for the CPU interrupts which are handled by the lantiq ICU with
> irq_set_chained_handler() which was already called before.
> 
> Calling the set_c0_status() function is also not needed any more because
> the generic MIPS CPU interrupt already activates the needed bits.
> 
> Fixes 1eed40043579 ("MIPS: smp-mt: Use CPU interrupt controller IPI IRQ domain support")
> Cc: stable@kernel.org # v4.12
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

Series applied to mips-fixes.

Thanks,
    Paul

[ This message was auto-generated; if you believe anything is incorrect
  then please email paul.burton@mips.com to report it. ]

^ permalink raw reply	[flat|nested] 3+ messages in thread

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Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2019-01-06 18:44 [PATCH 1/2] MIPS: lantiq: Fix IPI interrupt handling Hauke Mehrtens
2019-01-06 18:44 ` [PATCH 2/2] MIPS: lantiq: Use CP0_LEGACY_COMPARE_IRQ Hauke Mehrtens
2019-01-07 21:40 ` [PATCH 1/2] MIPS: lantiq: Fix IPI interrupt handling Paul Burton

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