From 510d8c6cce97c7fb62ee2bf81c1856438583c328 Mon Sep 17 00:00:00 2001 From: Huang Pei Date: Sat, 12 Jan 2019 09:37:18 +0800 Subject: [PATCH 1/3] loongson64: add helper for ll/sc bugfix in loongson3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit there is a bug in ll/sc operation on loongson 3， that it causes two concurrent ll/sc on same variable both succeed, which is unacceptable clearly Signed-off-by: Huang Pei --- arch/mips/include/asm/barrier.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index a5eb1bb..fc21eb5 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -203,6 +203,16 @@ #define __WEAK_LLSC_MB " \n" #endif +#if defined(CONFIG_CPU_LOONGSON3) +#define __LS3A_WAR_LLSC " .set mips64r2\nsynci 0\n.set mips0\n" +#define __ls3a_war_llsc() __asm__ __volatile__("synci 0" : : :"memory") +#define __LS_WAR_LLSC " .set mips3\nsync\n.set mips0\n" +#else +#define __LS3A_WAR_LLSC +#define __ls3a_war_llsc() +#define __LS_WAR_LLSC +#endif + #define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") #ifdef CONFIG_CPU_CAVIUM_OCTEON -- 2.7.4